Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26819

1

T1

24

T2

18

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20768

1

T1

13

T2

18

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

6051

1

T1

11

T4

15

T5

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20778

1

T2

18

T3

1

T4

277

auto[1]

6041

1

T1

24

T3

2

T5

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22590

1

T1

24

T2

18

T3

3

auto[1]

4229

1

T4

23

T5

30

T10

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	3	1			T49	2		T235	1		-	-
values[0]	5	1			T175	1		T236	1		T19	1
values[1]	907	1			T3	1		T5	19		T12	23
values[2]	644	1			T60	2		T155	11		T164	14
values[3]	724	1			T11	6		T12	8		T85	17
values[4]	672	1			T1	11		T60	31		T151	46
values[5]	689	1			T1	13		T4	15		T5	17
values[6]	621	1			T184	1		T154	2		T161	33
values[7]	777	1			T3	1		T4	23		T10	32
values[8]	1011	1			T5	20		T7	5		T55	12
values[9]	3386	1			T3	1		T9	10		T11	10
minimum	17380	1			T2	18		T4	239		T6	163

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1038	1			T3	1		T5	19		T12	23
values[1]	2964	1			T9	10		T12	8		T56	6
values[2]	684	1			T11	6		T60	2		T237	12
values[3]	671	1			T1	11		T4	15		T48	1
values[4]	692	1			T1	13		T5	17		T7	17
values[5]	535	1			T48	1		T154	1		T237	17
values[6]	1002	1			T3	1		T4	23		T10	32
values[7]	757	1			T7	5		T59	12		T238	20
values[8]	901	1			T5	20		T11	10		T60	23
values[9]	195	1			T3	1		T62	13		T174	4
minimum	17380	1			T2	18		T4	239		T6	163

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22552

1

T1

2

T2

18

T3

3

auto[1]

4267

1

T1

22

T4

13

T5

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T3	1		T5	11		T161	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T12	13		T154	1		T164	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T62	14		T85	15		T46	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1580	1			T9	10		T12	4		T56	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T60	1		T237	3		T239	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T11	1		T171	14		T186	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T60	20		T151	23		T160	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T1	11		T4	3		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	13		T5	5		T10	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T7	17		T156	3		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T154	1		T172	1		T44	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T48	1		T237	8		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T3	1		T4	12		T10	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T85	1		T161	9		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T238	11		T240	8		T49	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T7	5		T59	6		T47	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T156	14		T172	1		T49	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T5	10		T11	1		T60	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T3	1		T62	3		T174	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T62	6		T119	4		T175	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17230	1			T2	18		T4	239		T6	163
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T5	8		T161	8		T119	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T12	10		T164	9		T39	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T62	2		T85	2		T46	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	954	1			T12	4		T56	5		T61	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T60	1		T237	9		T239	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T11	5		T186	6		T241	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T60	11		T151	23		T220	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	12		T44	9		T169	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T5	12		T10	3		T238	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T156	6		T161	15		T241	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T44	2		T27	2		T110	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T237	9		T164	10		T32	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T4	11		T10	10		T11	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T85	14		T161	11		T158	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T238	9		T240	7		T49	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T59	6		T47	2		T242	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T156	14		T49	12		T118	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T5	10		T11	9		T60	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T243	10		T244	2		T245	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T62	4		T119	3		T246	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	2		T55	1		T85	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T49	1		T235	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T175	1		T19	1		T247	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T236	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T3	1		T5	11		T62	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T12	13		T154	1		T39	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T60	1		T165	1		T248	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T155	1		T164	5		T239	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T85	15		T46	4		T237	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T11	1		T12	4		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T60	20		T151	23		T220	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T1	11		T174	13		T163	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	13		T5	5		T10	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T4	3		T7	17		T48	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T184	1		T154	2		T238	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T161	18		T237	8		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	1		T4	12		T10	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T85	1		T158	1		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T55	5		T219	15		T238	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T5	10		T7	5		T59	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T3	1		T62	3		T156	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1731	1			T9	10		T11	1		T56	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17230	1			T2	18		T4	239		T6	163
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T49	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	8		T62	2		T161	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	10		T39	12		T169	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T60	1		T165	17		T248	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T155	10		T164	9		T239	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T85	2		T46	7		T237	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T11	5		T12	4		T155	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T60	11		T151	23		T220	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T169	8		T186	6		T249	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T5	12		T10	3		T237	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T4	12		T156	6		T44	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T238	4		T44	2		T27	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T161	15		T237	9		T164	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T4	11		T10	10		T11	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T85	14		T158	12		T162	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T55	7		T238	9		T166	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T5	10		T59	6		T156	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T156	14		T240	7		T49	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1143	1			T11	9		T56	5		T60	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	2		T55	1		T85	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T3	1		T5	9		T161	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T12	14		T154	1		T164	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T62	3		T85	3		T46	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1291	1			T9	1		T12	8		T56	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T60	2		T237	10		T239	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	6		T171	1		T186	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T60	12		T151	25		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T1	1		T4	13		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T1	1		T5	13		T10	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	2		T156	7		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T154	1		T172	1		T44	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T48	1		T237	10		T164	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T3	1		T4	12		T10	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T85	15		T161	12		T158	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T238	10		T240	8		T49	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T7	1		T59	7		T47	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T156	15		T172	1		T49	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T5	11		T11	10		T60	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T3	1		T62	1		T174	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T62	5		T119	4		T175	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17380	1			T2	18		T4	239		T6	163
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T5	10		T161	7		T43	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T12	9		T164	4		T39	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T62	13		T85	14		T47	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1243	1			T9	9		T153	4		T250	38
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T237	2		T42	14		T251	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T171	13		T216	7		T217	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T60	19		T151	21		T160	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T1	10		T4	2		T174	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T1	12		T5	4		T10	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T7	15		T156	2		T161	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T27	2		T252	14		T253	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T237	7		T32	15		T251	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T4	11		T10	21		T55	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T161	8		T42	15		T254	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T238	10		T240	7		T243	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T7	4		T59	5		T47	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T156	13		T242	14		T63	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	9		T60	12		T156	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T62	2		T174	3		T243	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T62	5		T119	3		T255	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum , values[0]]	*	--	--	4
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T49	2		T235	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T175	1		T19	1		T247	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T236	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	1		T5	9		T62	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T12	14		T154	1		T39	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T60	2		T165	18		T248	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T155	11		T164	10		T239	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T85	3		T46	11		T237	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T11	6		T12	8		T155	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T60	12		T151	25		T220	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T1	1		T174	1		T163	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	1		T5	13		T10	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T4	13		T7	2		T48	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T184	1		T154	2		T238	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T161	16		T237	10		T164	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	1		T4	12		T10	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T85	15		T158	13		T162	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T55	8		T219	1		T238	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T5	11		T7	1		T59	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T3	1		T62	1		T156	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1514	1			T9	1		T11	10		T56	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17380	1			T2	18		T4	239		T6	163
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T5	10		T62	13		T161	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T12	9		T39	10		T43	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T256	12		T26	2		T257	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T164	4		T239	7		T171	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T85	14		T237	2		T47	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T164	11		T171	13		T188	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T60	19		T151	21		T220	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T1	10		T174	12		T43	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T1	12		T5	4		T10	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T4	2		T7	15		T156	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T238	4		T167	4		T27	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T161	17		T237	7		T32	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T4	11		T10	21		T258	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T42	15		T254	13		T211	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T55	4		T219	14		T238	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T5	9		T7	4		T59	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T62	2		T156	13		T174	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1360	1			T9	9		T60	12		T62	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22552

1

T1

2

T2

18

T3

3

auto[1]

auto[0]

4267

1

T1

22

T4

13

T5

23

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26819

1

T1

24

T2

18

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23479

1

T1

11

T2

18

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3340

1

T1

13

T3

2

T4

38

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20703

1

T1

11

T2

18

T3

3

auto[1]

6116

1

T1

13

T4

15

T5

39

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22590

1

T1

24

T2

18

T3

3

auto[1]

4229

1

T4

23

T5

30

T10

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	93	1			T221	21		T259	18		T260	25
values[1]	735	1			T11	10		T156	9		T46	11
values[2]	662	1			T1	13		T12	23		T159	1
values[3]	685	1			T60	23		T151	31		T156	28
values[4]	699	1			T5	39		T10	5		T11	6
values[5]	744	1			T3	1		T4	23		T10	32
values[6]	830	1			T1	11		T4	15		T60	2
values[7]	677	1			T7	13		T48	1		T59	12
values[8]	2821	1			T5	17		T7	4		T9	10
values[9]	1493	1			T3	2		T7	5		T12	8
minimum	17380	1			T2	18		T4	239		T6	163

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	884	1			T156	9		T159	1		T46	11
values[1]	745	1			T1	13		T12	23		T60	23
values[2]	732	1			T5	19		T156	28		T237	22
values[3]	673	1			T5	20		T10	5		T11	6
values[4]	725	1			T3	1		T4	23		T10	32
values[5]	792	1			T1	11		T4	15		T60	2
values[6]	2844	1			T7	17		T9	10		T48	1
values[7]	662	1			T3	1		T5	17		T10	2
values[8]	1180	1			T3	1		T7	5		T12	8
values[9]	185	1			T261	1		T237	17		T42	16
minimum	17397	1			T2	18		T4	239		T6	163

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22552

1

T1

2

T2

18

T3

3

auto[1]

4267

1

T1

22

T4

13

T5

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T156	3		T159	1		T46	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T174	4		T47	4		T32	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T151	15		T240	8		T248	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	13		T12	13		T60	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T5	11		T156	16		T237	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T239	1		T171	12		T43	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T5	10		T10	3		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T59	12		T160	13		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T11	1		T48	1		T85	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T3	1		T4	12		T10	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T1	11		T60	1		T156	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T4	3		T154	1		T164	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1672	1			T7	17		T9	10		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T155	1		T164	12		T171	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	5		T164	1		T220	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	1		T10	1		T39	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	380	1			T3	1		T60	20		T62	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T7	5		T12	4		T85	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T261	1		T237	8		T42	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T168	1		T262	10		T244	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17236	1			T2	18		T4	239		T6	163
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T156	6		T46	7		T49	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T47	2		T170	14		T186	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T151	16		T240	7		T248	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	10		T60	10		T239	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	8		T156	12		T237	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T239	7		T256	13		T254	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	10		T10	2		T11	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T54	1		T263	13		T264	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	16		T85	14		T158	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T4	11		T10	10		T161	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T60	1		T156	14		T238	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T4	12		T164	9		T166	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	981	1			T55	7		T56	5		T59	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T155	3		T211	1		T243	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	12		T164	10		T220	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T10	1		T39	12		T44	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T60	11		T62	4		T151	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T12	4		T85	2		T155	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T237	9		T26	2		T128	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T262	9		T244	10		T246	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	9		T12	2		T55	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T260	14		T265	7		T266	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T221	11		T259	7		T267	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	1		T156	3		T46	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T174	4		T47	4		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T159	1		T240	8		T167	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T1	13		T12	13		T239	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T151	15		T156	16		T237	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T60	13		T239	1		T171	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T5	21		T10	3		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T256	13		T254	14		T51	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	1		T48	1		T85	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T3	1		T4	12		T10	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T1	11		T60	1		T156	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T4	3		T164	5		T172	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T7	13		T48	1		T59	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T154	1		T155	1		T211	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1598	1			T5	5		T7	4		T9	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T10	1		T164	12		T171	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	477	1			T3	1		T60	20		T62	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T3	1		T7	5		T12	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17230	1			T2	18		T4	239		T6	163
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T260	11		T265	14		T266	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T221	10		T259	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	9		T156	6		T46	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T47	2		T170	14		T186	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T240	7		T188	12		T121	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T12	10		T239	7		T268	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T151	16		T156	12		T237	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T60	10		T239	7		T51	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	18		T10	2		T11	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T256	13		T254	10		T54	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	16		T85	14		T163	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T4	11		T10	10		T161	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T60	1		T156	14		T238	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T4	12		T164	9		T169	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T59	6		T162	12		T251	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T155	3		T211	2		T242	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	969	1			T5	12		T55	7		T56	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T10	1		T39	12		T44	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	414	1			T60	11		T62	4		T151	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T12	4		T85	2		T155	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	2		T55	1		T85	1