Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26819

1

T1

24

T2

18

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23433

1

T1

11

T2

18

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3386

1

T1

13

T3

2

T4

38

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20763

1

T1

11

T2

18

T3

3

auto[1]

6056

1

T1

13

T4

15

T5

39

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22590

1

T1

24

T2

18

T3

3

auto[1]

4229

1

T4

23

T5

30

T10

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	356	1			T12	8		T62	10		T261	1
values[0]	25	1			T310	1		T259	18		T311	6
values[1]	773	1			T11	10		T156	9		T159	1
values[2]	689	1			T1	13		T12	23		T239	15
values[3]	747	1			T5	19		T60	23		T151	31
values[4]	644	1			T5	20		T10	5		T11	6
values[5]	702	1			T3	1		T4	23		T10	32
values[6]	856	1			T1	11		T4	15		T60	2
values[7]	706	1			T7	13		T48	1		T59	12
values[8]	2819	1			T3	1		T5	17		T7	4
values[9]	1122	1			T3	1		T7	5		T60	31
minimum	17380	1			T2	18		T4	239		T6	163

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	639	1			T159	1		T46	11		T174	4
values[1]	775	1			T1	13		T12	23		T60	23
values[2]	708	1			T5	19		T156	28		T237	22
values[3]	649	1			T5	20		T10	5		T11	6
values[4]	756	1			T3	1		T4	23		T10	32
values[5]	840	1			T1	11		T4	15		T60	2
values[6]	2771	1			T7	17		T9	10		T48	1
values[7]	728	1			T3	1		T5	17		T10	2
values[8]	1164	1			T3	1		T7	5		T12	8
values[9]	166	1			T261	1		T243	25		T262	19
minimum	17623	1			T2	18		T4	239		T6	163

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22552

1

T1

2

T2

18

T3

3

auto[1]

4267

1

T1

22

T4

13

T5

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T159	1		T46	4		T171	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T174	4		T47	4		T32	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T151	15		T239	8		T240	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T1	13		T12	13		T60	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	11		T156	16		T237	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T239	1		T171	12		T43	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T5	10		T10	3		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T59	12		T160	13		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	1		T48	1		T85	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T3	1		T4	12		T10	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T1	11		T60	1		T156	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T4	3		T154	1		T164	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1640	1			T7	17		T9	10		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T155	1		T164	12		T171	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T5	5		T55	5		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	1		T10	1		T39	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	398	1			T3	1		T60	20		T62	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T7	5		T12	4		T85	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T261	1		T243	15		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T262	10		T244	1		T246	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17279	1			T2	18		T4	239		T6	163
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T186	1		T259	7		T253	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T46	7		T117	10		T189	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T47	2		T170	14		T52	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T151	16		T239	7		T240	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	10		T60	10		T268	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	8		T156	12		T237	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T239	7		T188	12		T256	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	10		T10	2		T11	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T54	1		T264	4		T223	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	16		T85	14		T158	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T4	11		T10	10		T161	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T60	1		T156	14		T163	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T4	12		T164	9		T50	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	939	1			T56	5		T59	6		T61	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T155	3		T211	1		T243	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	12		T55	7		T164	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T10	1		T39	12		T44	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	367	1			T60	11		T62	4		T151	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	4		T85	2		T155	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T243	10		T128	12		T312	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T262	9		T244	10		T246	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T11	9		T12	2		T55	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T186	15		T259	11		T253	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T62	6		T261	1		T237	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T12	4		T166	16		T291	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T310	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T259	7		T311	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	1		T156	3		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T174	4		T47	4		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T239	8		T240	8		T167	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T1	13		T12	13		T268	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T5	11		T151	15		T156	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T60	13		T239	1		T171	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T5	10		T10	3		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T256	13		T254	14		T51	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T11	1		T48	1		T85	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	1		T4	12		T10	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T1	11		T60	1		T156	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T4	3		T164	5		T172	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T7	13		T48	1		T59	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T154	1		T155	1		T171	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1573	1			T5	5		T7	4		T9	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T3	1		T10	1		T164	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	409	1			T3	1		T60	20		T184	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T7	5		T85	15		T154	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17230	1			T2	18		T4	239		T6	163
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T62	4		T237	9		T165	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T12	4		T166	11		T291	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T259	11		T311	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T11	9		T156	6		T46	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T47	2		T170	14		T186	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T239	7		T240	7		T121	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	10		T268	4		T169	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	8		T151	16		T156	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T60	10		T239	7		T188	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T5	10		T10	2		T11	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T256	13		T254	10		T54	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T11	16		T85	14		T158	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T4	11		T10	10		T161	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T60	1		T156	14		T163	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T4	12		T164	9		T50	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T59	6		T162	12		T251	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T155	3		T211	1		T242	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	965	1			T5	12		T55	7		T56	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T10	1		T39	12		T44	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	355	1			T60	11		T151	7		T161	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T85	2		T155	10		T53	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	2		T55	1		T85	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T159	1		T46	11		T171	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T174	1		T47	4		T32	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T151	17		T239	8		T240	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T1	1		T12	14		T60	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	9		T156	13		T237	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T239	8		T171	1		T43	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	11		T10	3		T11	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T59	1		T160	1		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T11	17		T48	1		T85	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T3	1		T4	12		T10	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T1	1		T60	2		T156	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T4	13		T154	1		T164	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1279	1			T7	2		T9	1		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T155	4		T164	1		T171	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T5	13		T55	8		T164	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	1		T10	2		T39	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	443	1			T3	1		T60	12		T62	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T7	1		T12	8		T85	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T261	1		T243	11		T128	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T262	10		T244	11		T246	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17459	1			T2	18		T4	239		T6	163
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T186	16		T259	12		T253	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T171	13		T189	6		T280	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T174	3		T47	2		T262	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T151	14		T239	7		T240	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	12		T12	9		T60	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	10		T156	15		T237	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T171	11		T43	9		T188	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	9		T10	2		T62	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T59	11		T160	12		T54	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T238	14		T270	15		T313	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T4	11		T10	21		T161	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T1	10		T156	13		T174	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T4	2		T164	4		T242	25
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T7	15		T9	9		T59	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T164	11		T171	2		T243	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	4		T55	4		T220	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T39	10		T216	7		T100	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T60	19		T62	5		T151	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T7	4		T85	14		T160	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T243	14		T314	20		T312	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T262	9		T246	12		T315	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T156	2		T295	13		T260	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T259	6		T253	11		T290	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T62	5		T261	1		T237	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T12	8		T166	12		T291	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T310	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T259	12		T311	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T11	10		T156	7		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T174	1		T47	4		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T239	8		T240	8		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	1		T12	14		T268	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T5	9		T151	17		T156	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T60	11		T239	8		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	11		T10	3		T11	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T256	14		T254	11		T51	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T11	17		T48	1		T85	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T3	1		T4	12		T10	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	1		T60	2		T156	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T4	13		T164	10		T172	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T7	1		T48	1		T59	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T154	1		T155	4		T171	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T5	13		T7	1		T9	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T3	1		T10	2		T164	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	431	1			T3	1		T60	12		T184	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	1		T85	3		T154	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17380	1			T2	18		T4	239		T6	163
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T62	5		T237	7		T42	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T166	15		T100	9		T262	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T259	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T156	2		T171	13		T189	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T174	3		T47	2		T262	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T239	7		T240	7		T167	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T1	12		T12	9		T268	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	10		T151	14		T156	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T60	12		T171	11		T43	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	9		T10	2		T62	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T256	12		T254	13		T54	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T238	10		T268	10		T270	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T4	11		T10	21		T59	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T1	10		T156	13		T174	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	2		T164	4		T242	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T7	12		T59	5		T62	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T171	2		T242	11		T243	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1238	1			T5	4		T7	3		T9	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T164	11		T39	10		T100	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T60	19		T151	7		T219	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T7	4		T85	14		T160	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22552

1

T1

2

T2

18

T3

3

auto[1]

auto[0]

4267

1

T1

22

T4

13

T5

23