Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26819

1

T1

24

T2

18

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23472

1

T1

13

T2

18

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3347

1

T1

11

T3

1

T4

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20810

1

T2

18

T3

1

T4

254

auto[1]

6009

1

T1

24

T3

2

T4

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22590

1

T1

24

T2

18

T3

3

auto[1]

4229

1

T4

23

T5

30

T10

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	15	1			T193	13		T316	2		-	-
values[0]	69	1			T49	2		T205	19		T295	23
values[1]	590	1			T3	1		T5	17		T10	5
values[2]	887	1			T12	23		T62	10		T184	1
values[3]	647	1			T60	23		T155	4		T156	9
values[4]	708	1			T4	15		T48	1		T156	28
values[5]	2753	1			T7	5		T9	10		T11	6
values[6]	868	1			T1	24		T3	1		T4	23
values[7]	796	1			T5	39		T10	34		T154	1
values[8]	617	1			T3	1		T55	12		T59	12
values[9]	1489	1			T7	13		T11	27		T12	8
minimum	17380	1			T2	18		T4	239		T6	163

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	898	1			T3	1		T5	17		T10	5
values[1]	748	1			T62	10		T156	9		T160	13
values[2]	687	1			T12	23		T60	23		T154	1
values[3]	2886	1			T4	15		T9	10		T48	2
values[4]	653	1			T3	1		T7	5		T11	6
values[5]	801	1			T1	13		T4	23		T5	19
values[6]	722	1			T1	11		T3	1		T5	20
values[7]	734	1			T154	1		T157	3		T174	4
values[8]	1007	1			T7	13		T11	27		T12	8
values[9]	291	1			T62	16		T161	20		T119	13
minimum	17392	1			T2	18		T4	239		T6	163

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22552

1

T1

2

T2

18

T3

3

auto[1]

4267

1

T1

22

T4

13

T5

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T3	1		T10	3		T60	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T5	5		T156	16		T174	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T166	24		T44	1		T188	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T62	6		T156	3		T160	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T60	13		T155	1		T174	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	13		T154	1		T161	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1637	1			T9	10		T48	1		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T4	3		T48	1		T116	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T7	5		T158	1		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	1		T11	1		T60	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T1	13		T4	12		T5	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T7	4		T10	22		T62	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T3	1		T5	10		T55	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T1	11		T46	4		T239	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T174	4		T162	1		T237	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T154	1		T157	3		T47	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	390	1			T151	15		T155	1		T161	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T7	13		T11	2		T12	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T262	5		T264	7		T306	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T62	14		T161	9		T119	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17231	1			T2	18		T4	239		T6	163
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T53	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T10	2		T60	1		T151	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T5	12		T156	12		T239	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T166	16		T44	9		T188	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T62	4		T156	6		T163	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T60	10		T155	3		T243	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	10		T161	15		T251	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	982	1			T56	5		T61	17		T182	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T4	12		T189	7		T244	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T158	12		T238	9		T189	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	5		T60	11		T32	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T4	11		T5	8		T10	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T10	10		T85	2		T165	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T5	10		T55	7		T85	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T46	7		T239	7		T220	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T162	12		T237	9		T164	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T47	2		T169	8		T242	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T151	16		T155	10		T161	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T11	25		T12	4		T170	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T262	2		T264	4		T193	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T62	2		T161	11		T119	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	2		T55	1		T85	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T53	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T193	7		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T316	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T205	1		T317	1		T318	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T49	1		T205	1		T295	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T3	1		T10	3		T60	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	5		T156	16		T174	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T184	1		T151	8		T166	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T12	13		T62	6		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T60	13		T155	1		T166	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T156	3		T161	18		T171	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T48	1		T156	14		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T4	3		T251	4		T116	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1619	1			T7	5		T9	10		T56	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T11	1		T48	1		T219	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T1	13		T4	12		T59	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T1	11		T3	1		T7	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T5	21		T10	1		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T10	22		T46	4		T239	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T3	1		T55	5		T174	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T59	12		T154	1		T157	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	475	1			T151	15		T155	1		T161	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T7	13		T11	2		T12	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17230	1			T2	18		T4	239		T6	163
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T193	6		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T316	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T205	13		T317	1		T318	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T49	1		T205	4		T295	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T10	2		T60	1		T169	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T5	12		T156	12		T49	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T151	7		T166	5		T170	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T12	10		T62	4		T163	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T60	10		T155	3		T166	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T156	6		T161	15		T186	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T156	14		T51	5		T101	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T4	12		T251	12		T189	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	931	1			T56	5		T61	17		T182	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T11	5		T50	2		T169	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T4	11		T59	6		T85	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T60	11		T85	2		T32	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T5	18		T10	1		T119	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T10	10		T46	7		T239	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T55	7		T162	12		T237	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T169	8		T242	13		T258	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	373	1			T151	16		T155	10		T161	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T11	25		T12	4		T62	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	2		T55	1		T85	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T3	1		T10	3		T60	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T5	13		T156	13		T174	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T166	18		T44	10		T188	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T62	5		T156	7		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T60	11		T155	4		T174	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	14		T154	1		T161	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T9	1		T48	1		T56	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T4	13		T48	1		T116	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	1		T158	13		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T3	1		T11	6		T60	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T1	1		T4	12		T5	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	1		T10	11		T62	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T3	1		T5	11		T55	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	1		T46	11		T239	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T174	1		T162	13		T237	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T154	1		T157	1		T47	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	368	1			T151	17		T155	11		T161	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T7	1		T11	27		T12	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T262	3		T264	5		T306	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T62	3		T161	12		T119	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17387	1			T2	18		T4	239		T6	163
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T53	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T10	2		T151	7		T211	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	4		T156	15		T174	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T166	22		T188	11		T286	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T62	5		T156	2		T160	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T60	12		T174	12		T43	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T12	9		T161	17		T171	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T9	9		T153	4		T156	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T4	2		T189	6		T259	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	4		T238	10		T164	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T60	19		T219	14		T32	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T1	12		T4	11		T5	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	3		T10	21		T62	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	9		T55	4		T251	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T1	10		T239	7		T220	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T174	3		T237	2		T164	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T157	2		T47	3		T242	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T151	14		T161	7		T237	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T7	12		T59	11		T100	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T262	4		T264	6		T306	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T62	13		T161	8		T119	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T53	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T193	7		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T316	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T205	14		T317	2		T318	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T49	2		T205	5		T295	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T3	1		T10	3		T60	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T5	13		T156	13		T174	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T184	1		T151	8		T166	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T12	14		T62	5		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T60	11		T155	4		T166	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T156	7		T161	16		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T48	1		T156	15		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T4	13		T251	13		T116	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1270	1			T7	1		T9	1		T56	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	6		T48	1		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T1	1		T4	12		T59	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T1	1		T3	1		T7	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T5	20		T10	2		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T10	11		T46	11		T239	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	1		T55	8		T174	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T59	1		T154	1		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	458	1			T151	17		T155	11		T161	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	408	1			T7	1		T11	27		T12	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17380	1			T2	18		T4	239		T6	163
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T193	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T318	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T295	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T10	2		T211	9		T100	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T5	4		T156	15		T174	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T151	7		T166	7		T242	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T12	9		T62	5		T160	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T60	12		T166	15		T188	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T156	2		T161	17		T171	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T156	13		T174	12		T43	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T4	2		T251	3		T189	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1280	1			T7	4		T9	9		T153	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T219	14		T98	13		T259	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T1	12		T4	11		T59	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	10		T7	3		T60	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T5	19		T251	15		T119	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T10	21		T239	7		T220	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T55	4		T174	3		T237	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T59	11		T157	2		T216	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	390	1			T151	14		T161	7		T237	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T7	12		T62	13		T161	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22552

1

T1

2

T2

18

T3

3

auto[1]

auto[0]

4267

1

T1

22

T4

13

T5

23