Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26819

1

T1

24

T2

18

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22782

1

T1

13

T2

18

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

4037

1

T1

11

T3

2

T4

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20538

1

T1

24

T2

18

T3

2

auto[1]

6281

1

T3

1

T4

15

T7

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22590

1

T1

24

T2

18

T3

3

auto[1]

4229

1

T4

23

T5

30

T10

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	277	1			T85	17		T47	11		T251	16
values[0]	34	1			T155	4		T118	16		T206	14
values[1]	787	1			T1	11		T4	38		T7	13
values[2]	2963	1			T9	10		T56	6		T61	19
values[3]	567	1			T5	19		T7	5		T48	1
values[4]	706	1			T12	23		T62	19		T151	31
values[5]	785	1			T3	1		T10	32		T12	8
values[6]	711	1			T3	1		T11	6		T85	15
values[7]	612	1			T5	17		T7	4		T10	2
values[8]	740	1			T1	13		T3	1		T11	10
values[9]	1257	1			T5	20		T10	5		T62	10
minimum	17380	1			T2	18		T4	239		T6	163

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	717	1			T1	11		T4	23		T7	13
values[1]	2954	1			T9	10		T56	6		T59	12
values[2]	587	1			T5	19		T7	5		T12	23
values[3]	701	1			T10	32		T12	8		T62	19
values[4]	734	1			T3	1		T60	54		T160	6
values[5]	814	1			T3	1		T5	17		T7	4
values[6]	592	1			T1	13		T3	1		T10	2
values[7]	705	1			T10	5		T11	10		T55	12
values[8]	1114	1			T5	20		T62	10		T154	1
values[9]	206	1			T85	17		T161	20		T174	4
minimum	17695	1			T2	18		T4	254		T6	163

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22552

1

T1

2

T2

18

T3

3

auto[1]

4267

1

T1

22

T4

13

T5

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T162	1		T171	14		T53	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T1	11		T4	12		T7	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1571	1			T9	10		T56	1		T59	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T261	1		T237	8		T39	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T7	5		T12	13		T160	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	11		T48	1		T154	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T12	4		T151	15		T156	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T10	22		T62	17		T219	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	1		T160	6		T47	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T60	33		T220	11		T166	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T7	4		T11	1		T59	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T3	1		T5	5		T85	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T1	13		T48	1		T60	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T3	1		T10	1		T184	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T55	5		T171	3		T169	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T10	3		T11	1		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T5	10		T62	6		T156	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T154	1		T47	9		T240	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T161	9		T174	4		T32	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T85	15		T238	11		T245	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17275	1			T2	18		T4	242		T6	163
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T239	1		T118	1		T212	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T162	12		T241	4		T270	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T4	11		T11	16		T268	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	940	1			T56	5		T61	17		T182	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T237	9		T39	12		T44	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T12	10		T164	19		T239	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	8		T237	9		T166	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T12	4		T151	16		T156	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T10	10		T62	2		T33	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T47	2		T51	5		T242	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T60	21		T220	11		T166	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	5		T59	6		T155	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T5	12		T85	14		T188	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T60	1		T188	14		T256	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T10	1		T151	7		T237	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T55	7		T169	9		T186	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T10	2		T11	9		T163	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T5	10		T62	4		T156	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T47	2		T240	7		T32	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T161	11		T49	1		T29	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T85	2		T238	9		T245	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T4	12		T12	2		T55	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T239	7		T118	15		T190	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T211	1		T249	18		T35	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T85	15		T47	9		T251	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T155	1		T206	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T118	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T4	3		T162	1		T171	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T1	11		T4	12		T7	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1550	1			T9	10		T56	1		T61	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T261	1		T237	8		T39	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T7	5		T59	12		T174	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	11		T48	1		T154	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T12	13		T151	15		T156	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T62	17		T219	15		T237	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T3	1		T12	4		T160	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T10	22		T60	33		T220	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T11	1		T155	1		T156	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T3	1		T85	1		T172	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T7	4		T59	6		T60	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T5	5		T10	1		T184	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T1	13		T48	1		T55	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T3	1		T11	1		T171	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T5	10		T62	6		T156	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T10	3		T154	1		T163	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17230	1			T2	18		T4	239		T6	163
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T211	1		T249	14		T35	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T85	2		T47	2		T251	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T155	3		T206	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T118	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T4	12		T162	12		T49	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T4	11		T11	16		T239	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	940	1			T56	5		T61	17		T182	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T237	9		T39	12		T44	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T164	19		T239	7		T166	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T5	8		T166	8		T186	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T12	10		T151	16		T156	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T62	2		T237	9		T211	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T12	4		T47	2		T51	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T10	10		T60	21		T220	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	5		T155	10		T156	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T85	14		T188	12		T245	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T59	6		T60	1		T188	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	12		T10	1		T151	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T55	7		T256	13		T186	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	9		T119	3		T101	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	365	1			T5	10		T62	4		T156	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T10	2		T163	16		T238	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	2		T55	1		T85	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T162	13		T171	1		T53	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T1	1		T4	12		T7	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1274	1			T9	1		T56	6		T59	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T261	1		T237	10		T39	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T7	1		T12	14		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T5	9		T48	1		T154	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T12	8		T151	17		T156	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T10	11		T62	4		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T3	1		T160	1		T47	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T60	23		T220	12		T166	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T7	1		T11	6		T59	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T3	1		T5	13		T85	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T1	1		T48	1		T60	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	1		T10	2		T184	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T55	8		T171	1		T169	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T10	3		T11	10		T163	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	384	1			T5	11		T62	5		T156	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T154	1		T47	8		T240	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T161	12		T174	1		T32	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T85	3		T238	10		T245	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17435	1			T2	18		T4	252		T6	163
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T239	8		T118	16		T212	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T171	13		T279	11		T270	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	10		T4	11		T7	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T9	9		T59	11		T153	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T237	7		T39	10		T119	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T7	4		T12	9		T160	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T5	10		T237	2		T189	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T151	14		T156	13		T157	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T10	21		T62	15		T219	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T160	5		T47	2		T43	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T60	31		T220	10		T166	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	3		T59	5		T156	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	4		T188	11		T305	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T1	12		T188	14		T256	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T151	7		T237	11		T243	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T55	4		T171	2		T101	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	2		T171	11		T119	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T5	9		T62	5		T156	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T47	3		T240	7		T32	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T161	8		T174	3		T221	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T85	14		T238	10		T319	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T4	2		T43	9		T110	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T104	3		T275	6		T320	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T211	2		T249	15		T35	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T85	3		T47	8		T251	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T155	4		T206	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T118	16		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T4	13		T162	13		T171	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T1	1		T4	12		T7	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T9	1		T56	6		T61	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T261	1		T237	10		T39	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T7	1		T59	1		T174	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T5	9		T48	1		T154	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T12	14		T151	17		T156	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T62	4		T219	1		T237	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	1		T12	8		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T10	11		T60	23		T220	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T11	6		T155	11		T156	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T3	1		T85	15		T172	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T7	1		T59	7		T60	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T5	13		T10	2		T184	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	1		T48	1		T55	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	1		T11	10		T171	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	430	1			T5	11		T62	5		T156	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T10	3		T154	1		T163	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17380	1			T2	18		T4	239		T6	163
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T249	17		T189	6		T221	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T85	14		T47	3		T251	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T206	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T4	2		T171	13		T43	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	10		T4	11		T7	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1217	1			T9	9		T153	4		T250	38
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T237	7		T39	10		T119	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T7	4		T59	11		T174	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T5	10		T309	2		T110	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	9		T151	14		T156	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T62	15		T219	14		T237	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T160	5		T47	2		T51	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T10	21		T60	31		T220	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T156	15		T42	14		T43	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T188	11		T206	2		T321	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T7	3		T59	5		T188	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	4		T151	7		T237	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T1	12		T55	4		T171	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T171	11		T119	3		T100	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T5	9		T62	5		T156	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T10	2		T238	10		T240	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22552

1

T1

2

T2

18

T3

3

auto[1]

auto[0]

4267

1

T1

22

T4

13

T5

23