Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26819

1

T1

24

T2

18

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22979

1

T1

11

T2

18

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3840

1

T1

13

T3

1

T4

38

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20596

1

T1

13

T2

18

T3

2

auto[1]

6223

1

T1

11

T3

1

T4

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22590

1

T1

24

T2

18

T3

3

auto[1]

4229

1

T4

23

T5

30

T10

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	483	1			T4	2		T6	6		T8	2
values[0]	109	1			T251	27		T54	6		T263	14
values[1]	753	1			T4	15		T5	19		T7	4
values[2]	2826	1			T1	11		T3	1		T9	10
values[3]	843	1			T1	13		T154	2		T46	11
values[4]	730	1			T7	13		T59	12		T85	17
values[5]	721	1			T4	23		T48	1		T174	13
values[6]	578	1			T5	17		T7	5		T10	5
values[7]	668	1			T85	15		T156	9		T164	23
values[8]	888	1			T3	1		T11	27		T59	12
values[9]	1264	1			T3	1		T5	20		T10	34
minimum	16956	1			T2	18		T4	237		T6	157

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	940	1			T4	15		T5	19		T7	4
values[1]	2973	1			T3	1		T9	10		T56	6
values[2]	776	1			T1	24		T59	12		T184	1
values[3]	695	1			T7	13		T85	17		T154	1
values[4]	756	1			T4	23		T10	5		T48	2
values[5]	583	1			T5	17		T7	5		T154	1
values[6]	674	1			T59	12		T60	23		T62	3
values[7]	786	1			T3	1		T10	32		T11	27
values[8]	1039	1			T3	1		T5	20		T10	2
values[9]	192	1			T12	23		T164	14		T43	16
minimum	17405	1			T2	18		T4	239		T6	163

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22552

1

T1

2

T2

18

T3

3

auto[1]

4267

1

T1

22

T4

13

T5

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T159	1		T161	18		T174	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	389	1			T4	3		T5	11		T7	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1672	1			T9	10		T56	1		T60	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T3	1		T62	6		T46	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T1	11		T59	6		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T1	13		T184	1		T160	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T7	13		T85	15		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T174	4		T239	1		T188	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T48	2		T174	13		T171	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T4	12		T10	3		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	5		T151	8		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	5		T154	1		T156	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T59	12		T60	13		T164	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T62	3		T85	1		T151	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T3	1		T238	11		T220	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T10	22		T11	2		T156	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T3	1		T5	10		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T11	1		T155	1		T157	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T51	1		T216	8		T285	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T12	13		T164	5		T43	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17235	1			T2	18		T4	239		T6	163
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T322	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T161	15		T166	8		T54	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T4	12		T5	8		T55	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	999	1			T56	5		T60	11		T61	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T62	4		T46	7		T163	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T59	6		T238	4		T188	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T237	9		T169	8		T98	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T85	2		T158	12		T44	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T239	7		T188	14		T243	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T39	12		T211	1		T243	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T4	11		T10	2		T162	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T5	12		T151	7		T155	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T156	6		T164	10		T211	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T60	10		T268	7		T263	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T85	14		T151	16		T165	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T238	9		T220	11		T47	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T10	10		T11	25		T156	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T5	10		T10	1		T12	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T11	5		T155	3		T166	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T285	9		T300	2		T209	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T12	10		T164	9		T242	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	2		T55	1		T85	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	443	1			T4	2		T6	6		T8	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T166	16		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T54	5		T323	2		T307	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T251	15		T263	1		T324	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T159	1		T174	13		T240	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T4	3		T5	11		T7	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1603	1			T1	11		T9	10		T56	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T3	1		T55	5		T60	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T154	2		T248	1		T32	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T1	13		T46	4		T160	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T7	13		T59	6		T85	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T184	1		T174	4		T188	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T48	1		T174	13		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T4	12		T162	1		T239	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	5		T48	1		T151	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T7	5		T10	3		T62	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T164	12		T43	10		T268	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T85	1		T156	3		T164	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T3	1		T59	12		T60	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T11	2		T151	15		T156	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T3	1		T5	10		T10	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T10	22		T11	1		T12	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16806	1			T2	18		T4	237		T6	157
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T325	1		T326	12		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T166	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T54	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T251	12		T263	13		T326	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T240	7		T166	8		T274	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T4	12		T5	8		T156	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	932	1			T56	5		T60	11		T61	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T55	7		T60	1		T62	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T248	11		T32	12		T268	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T46	7		T237	9		T49	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T59	6		T85	2		T238	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T188	14		T169	8		T242	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T158	12		T47	2		T39	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T4	11		T162	12		T239	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	12		T151	7		T155	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T10	2		T237	10		T51	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T268	7		T33	15		T283	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T85	14		T156	6		T164	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T60	10		T238	9		T220	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T11	25		T151	16		T156	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T5	10		T10	1		T12	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T10	10		T11	5		T12	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	2		T55	1		T85	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T159	1		T161	16		T174	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T4	13		T5	9		T7	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T9	1		T56	6		T60	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T3	1		T62	5		T46	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T1	1		T59	7		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T1	1		T184	1		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T7	1		T85	3		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T174	1		T239	8		T188	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T48	2		T174	1		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T4	12		T10	3		T162	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	13		T151	8		T155	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	1		T154	1		T156	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T59	1		T60	11		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T62	1		T85	15		T151	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T3	1		T238	10		T220	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T10	11		T11	27		T156	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T3	1		T5	11		T10	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T11	6		T155	4		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T51	1		T216	1		T285	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T12	14		T164	10		T43	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17385	1			T2	18		T4	239		T6	163
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T322	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T161	17		T174	12		T54	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T4	2		T5	10		T7	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T9	9		T60	19		T153	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T62	5		T160	12		T239	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	10		T59	5		T238	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T1	12		T160	5		T219	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T7	12		T85	14		T211	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T174	3		T188	14		T243	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T174	12		T171	11		T39	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T4	11		T10	2		T237	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T5	4		T151	7		T47	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T7	4		T156	2		T286	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T59	11		T60	12		T164	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T62	2		T151	14		T51	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T238	10		T220	10		T47	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T10	21		T156	15		T216	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T5	9		T62	13		T161	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T157	2		T166	15		T241	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T216	7		T209	13		T277	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T12	9		T164	4		T43	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T274	4		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T322	15		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	439	1			T4	2		T6	6		T8	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T166	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T54	5		T323	2		T307	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T251	13		T263	14		T324	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T159	1		T174	1		T240	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T4	13		T5	9		T7	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1267	1			T1	1		T9	1		T56	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	1		T55	8		T60	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T154	2		T248	12		T32	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T1	1		T46	11		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T7	1		T59	7		T85	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T184	1		T174	1		T188	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T48	1		T174	1		T158	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T4	12		T162	13		T239	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	13		T48	1		T151	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T7	1		T10	3		T62	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T164	1		T43	1		T268	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T85	15		T156	7		T164	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T3	1		T59	1		T60	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T11	27		T151	17		T156	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	364	1			T3	1		T5	11		T10	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	380	1			T10	11		T11	6		T12	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16956	1			T2	18		T4	237		T6	157
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T326	17		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T166	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T54	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T251	14		T322	15		T327	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T174	12		T240	7		T42	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T4	2		T5	10		T7	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T1	10		T9	9		T60	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T55	4		T62	5		T160	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T32	15		T268	8		T258	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T1	12		T160	5		T219	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T7	12		T59	5		T85	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T174	3		T188	14		T217	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T174	12		T47	2		T171	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T4	11		T171	13		T254	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T5	4		T151	7		T287	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T7	4		T10	2		T62	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T164	11		T43	9		T268	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T156	2		T216	10		T100	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T59	11		T60	12		T238	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T151	14		T156	15		T100	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T5	9		T62	13		T161	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T10	21		T12	9		T157	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22552

1

T1

2

T2

18

T3

3

auto[1]

auto[0]

4267

1

T1

22

T4

13

T5

23