Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26819

1

T1

24

T2

18

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22813

1

T1

11

T2

18

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

4006

1

T1

13

T3

2

T4

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20223

1

T1

24

T2

18

T3

3

auto[1]

6596

1

T4

2

T5

39

T6

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22590

1

T1

24

T2

18

T3

3

auto[1]

4229

1

T4

23

T5

30

T10

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	688	1			T4	2		T6	6		T8	2
values[0]	59	1			T5	19		T322	16		T323	1
values[1]	740	1			T4	15		T7	4		T55	12
values[2]	2941	1			T1	11		T3	1		T9	10
values[3]	835	1			T1	13		T154	2		T160	6
values[4]	663	1			T7	13		T59	12		T85	17
values[5]	770	1			T4	23		T10	5		T48	1
values[6]	565	1			T5	17		T7	5		T48	1
values[7]	726	1			T59	12		T85	15		T156	9
values[8]	767	1			T3	1		T11	27		T60	23
values[9]	1109	1			T3	1		T5	20		T10	34
minimum	16956	1			T2	18		T4	237		T6	157

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	645	1			T7	4		T55	12		T60	2
values[1]	3030	1			T1	11		T3	1		T9	10
values[2]	776	1			T1	13		T184	1		T154	1
values[3]	687	1			T7	13		T59	12		T85	17
values[4]	799	1			T4	23		T10	5		T48	2
values[5]	575	1			T5	17		T7	5		T62	3
values[6]	696	1			T59	12		T60	23		T85	15
values[7]	764	1			T3	1		T10	32		T11	27
values[8]	1122	1			T3	1		T10	2		T11	6
values[9]	103	1			T5	20		T216	8		T27	5
minimum	17622	1			T2	18		T4	254		T5	19

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22552

1

T1

2

T2

18

T3

3

auto[1]

4267

1

T1

22

T4

13

T5

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T161	9		T43	14		T118	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T7	4		T55	5		T60	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1664	1			T1	11		T9	10		T56	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	1		T62	6		T46	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T154	1		T238	5		T248	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T1	13		T184	1		T160	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T7	13		T59	6		T85	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T154	1		T239	1		T188	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T48	1		T174	13		T162	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T4	12		T10	3		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	5		T62	3		T99	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T7	5		T154	1		T151	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T85	1		T164	12		T43	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T59	12		T60	13		T151	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T10	22		T220	11		T47	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	1		T11	2		T156	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T3	1		T10	1		T12	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	375	1			T11	1		T12	13		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T5	10		T216	8		T328	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T27	3		T329	1		T285	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17265	1			T2	18		T4	242		T6	163
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T5	11		T271	9		T269	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T161	11		T186	6		T54	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T55	7		T60	1		T156	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	984	1			T56	5		T60	11		T61	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T62	4		T46	7		T163	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T238	4		T248	11		T188	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T237	9		T268	4		T49	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T59	6		T85	2		T44	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T239	7		T188	14		T243	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T162	12		T237	10		T254	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T4	11		T10	2		T158	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T5	12		T101	1		T330	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T151	7		T155	10		T156	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T85	14		T263	14		T283	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T60	10		T151	16		T165	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T10	10		T220	11		T47	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T11	25		T156	12		T238	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T10	1		T12	4		T62	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T11	5		T12	10		T155	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T5	10		T328	11		T209	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T27	2		T329	13		T285	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T4	12		T12	2		T55	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T5	8		T273	8		T282	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	521	1			T4	2		T6	6		T8	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T155	1		T116	1		T242	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T323	1		T307	1		T331	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T5	11		T322	16		T327	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T4	3		T161	9		T166	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T7	4		T55	5		T156	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1611	1			T1	11		T9	10		T56	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T3	1		T60	1		T62	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T154	1		T248	1		T32	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T1	13		T154	1		T160	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T7	13		T59	6		T85	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T184	1		T188	15		T49	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T174	13		T162	1		T171	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T4	12		T10	3		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T5	5		T48	1		T62	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T7	5		T154	1		T151	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T85	1		T164	12		T43	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T59	12		T156	3		T164	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T220	11		T47	9		T171	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T3	1		T11	2		T60	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T3	1		T5	10		T10	23
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	377	1			T11	1		T12	13		T261	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16806	1			T2	18		T4	237		T6	157
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T119	10		T241	7		T303	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T155	3		T27	2		T108	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T331	3		T332	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T5	8		T333	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T4	12		T161	11		T166	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T55	7		T156	14		T237	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	931	1			T56	5		T60	11		T61	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T60	1		T62	4		T46	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T248	11		T32	12		T49	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T237	9		T268	4		T170	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T59	6		T85	2		T238	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T188	14		T49	11		T169	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T162	12		T44	9		T254	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T4	11		T10	2		T158	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T5	12		T237	10		T211	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T151	7		T155	10		T211	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T85	14		T270	10		T263	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T156	6		T164	10		T165	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T220	11		T47	2		T166	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T11	25		T60	10		T151	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	10		T10	11		T12	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T11	5		T12	10		T166	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	2		T55	1		T85	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T161	12		T43	1		T118	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	1		T55	8		T60	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1328	1			T1	1		T9	1		T56	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T3	1		T62	5		T46	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T154	1		T238	5		T248	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T1	1		T184	1		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T7	1		T59	7		T85	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T154	1		T239	8		T188	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T48	1		T174	1		T162	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T4	12		T10	3		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	13		T62	1		T99	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	1		T154	1		T151	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T85	15		T164	1		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T59	1		T60	11		T151	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T10	11		T220	12		T47	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T3	1		T11	27		T156	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T3	1		T10	2		T12	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	365	1			T11	6		T12	14		T155	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T5	11		T216	1		T328	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T27	3		T329	14		T285	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17443	1			T2	18		T4	252		T6	163
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T5	9		T271	1		T269	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T161	8		T43	13		T54	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	3		T55	4		T156	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1320	1			T1	10		T9	9		T60	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T62	5		T239	7		T42	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T238	4		T42	15		T188	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	12		T160	5		T219	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	12		T59	5		T85	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T188	14		T243	14		T309	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T174	12		T237	11		T171	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T4	11		T10	2		T47	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T5	4		T62	2		T287	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T7	4		T151	7		T156	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T164	11		T43	9		T263	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T59	11		T60	12		T151	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T10	21		T220	10		T47	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T156	15		T238	10		T100	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T62	13		T161	7		T164	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T12	9		T157	2		T166	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T5	9		T216	7		T209	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T27	2		T266	4		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T4	2		T274	4		T203	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T5	10		T271	8		T269	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	531	1			T4	2		T6	6		T8	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T155	4		T116	1		T242	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T323	1		T307	1		T331	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T5	9		T322	1		T327	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T4	13		T161	12		T166	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T7	1		T55	8		T156	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1267	1			T1	1		T9	1		T56	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T3	1		T60	2		T62	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T154	1		T248	12		T32	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	1		T154	1		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T7	1		T59	7		T85	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T184	1		T188	15		T49	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T174	1		T162	13		T171	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T4	12		T10	3		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	13		T48	1		T62	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T7	1		T154	1		T151	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T85	15		T164	1		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T59	1		T156	7		T164	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T220	12		T47	8		T171	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T3	1		T11	27		T60	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T3	1		T5	11		T10	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	392	1			T11	6		T12	14		T261	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16956	1			T2	18		T4	237		T6	157
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T119	2		T241	7		T303	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T27	2		T108	13		T334	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T331	1		T332	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T5	10		T322	15		T327	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T4	2		T161	8		T43	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T7	3		T55	4		T156	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1275	1			T1	10		T9	9		T60	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T62	5		T174	12		T239	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T32	15		T42	15		T251	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T1	12		T160	5		T219	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	12		T59	5		T85	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T188	14		T309	2		T335	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T174	12		T171	11		T254	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T4	11		T10	2		T47	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	4		T62	2		T237	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T7	4		T151	7		T283	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T164	11		T43	9		T263	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T59	11		T156	2		T268	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T220	10		T47	3		T171	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T60	12		T151	14		T156	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T5	9		T10	21		T62	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T12	9		T157	2		T166	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22552

1

T1

2

T2

18

T3

3

auto[1]

auto[0]

4267

1

T1

22

T4

13

T5

23