Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26819

1

T1

24

T2

18

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23462

1

T2

18

T3

2

T4

262

auto[ADC_CTRL_FILTER_COND_OUT]

3357

1

T1

24

T3

1

T4

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20857

1

T2

18

T3

1

T4

254

auto[1]

5962

1

T1

24

T3

2

T4

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22590

1

T1

24

T2

18

T3

3

auto[1]

4229

1

T4

23

T5

30

T10

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	306	1			T155	11		T161	16		T237	17
values[0]	52	1			T49	2		T205	19		T295	23
values[1]	673	1			T3	1		T5	17		T10	5
values[2]	780	1			T12	23		T62	10		T151	15
values[3]	720	1			T60	23		T154	1		T155	4
values[4]	733	1			T4	15		T48	2		T156	28
values[5]	2729	1			T7	5		T9	10		T11	6
values[6]	857	1			T1	24		T3	1		T4	23
values[7]	767	1			T5	39		T10	2		T85	15
values[8]	633	1			T3	1		T55	12		T59	12
values[9]	1189	1			T7	13		T11	27		T12	8
minimum	17380	1			T2	18		T4	239		T6	163

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	697	1			T3	1		T5	17		T10	5
values[1]	724	1			T62	10		T154	1		T156	9
values[2]	719	1			T12	23		T60	23		T155	4
values[3]	2846	1			T4	15		T9	10		T48	2
values[4]	663	1			T3	1		T7	5		T11	6
values[5]	835	1			T1	24		T4	23		T5	19
values[6]	696	1			T3	1		T5	20		T55	12
values[7]	749	1			T59	12		T154	1		T157	3
values[8]	1065	1			T7	13		T11	27		T12	8
values[9]	217	1			T62	16		T119	13		T123	9
minimum	17608	1			T2	18		T4	239		T6	163

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22552

1

T1

2

T2

18

T3

3

auto[1]

4267

1

T1

22

T4

13

T5

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	1		T60	1		T184	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	5		T10	3		T156	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T171	3		T166	16		T44	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T62	6		T154	1		T156	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T60	13		T161	18		T174	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T12	13		T155	1		T237	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1628	1			T9	10		T56	1		T61	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T4	3		T48	2		T42	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T7	5		T158	1		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T3	1		T11	1		T60	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T4	12		T10	1		T160	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T1	24		T5	11		T7	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T3	1		T5	10		T55	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T46	4		T239	8		T220	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T174	4		T162	1		T237	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T59	12		T154	1		T157	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T11	1		T151	15		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T7	13		T11	1		T12	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T245	1		T264	7		T193	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T62	14		T119	3		T123	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17276	1			T2	18		T4	239		T6	163
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T49	3		T249	8		T30	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T60	1		T151	7		T169	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	12		T10	2		T156	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T166	11		T44	9		T188	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T62	4		T156	6		T163	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T60	10		T161	15		T243	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	10		T155	3		T237	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	970	1			T56	5		T61	17		T182	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T4	12		T189	7		T244	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T158	12		T238	9		T32	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T11	5		T60	11		T50	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T4	11		T10	1		T238	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T5	8		T10	10		T59	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T5	10		T55	7		T85	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T46	7		T239	7		T220	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T162	12		T237	9		T164	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T47	2		T169	8		T258	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T11	9		T151	16		T155	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	16		T12	4		T161	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T245	10		T264	4		T193	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T62	2		T119	10		T211	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T12	2		T55	1		T85	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T49	13		T249	7		T191	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T155	1		T161	8		T237	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T119	3		T123	9		T170	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T205	1		T318	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T49	1		T205	1		T295	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	1		T60	1		T184	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	5		T10	3		T156	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T151	8		T171	3		T212	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	13		T62	6		T160	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T60	13		T161	18		T166	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T154	1		T155	1		T156	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T156	14		T159	1		T174	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T4	3		T48	2		T251	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1585	1			T7	5		T9	10		T56	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T11	1		T219	15		T42	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T4	12		T160	6		T238	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T1	24		T3	1		T7	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T5	10		T10	1		T85	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	11		T46	4		T239	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T3	1		T55	5		T174	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T59	12		T154	1		T157	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	375	1			T11	1		T151	15		T42	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T7	13		T11	1		T12	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17230	1			T2	18		T4	239		T6	163
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T155	10		T161	8		T237	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T119	10		T170	14		T313	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T205	13		T318	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T49	1		T205	4		T295	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T60	1		T169	7		T211	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	12		T10	2		T156	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T151	7		T52	3		T242	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	10		T62	4		T163	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T60	10		T161	15		T166	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T155	3		T156	6		T186	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T156	14		T51	5		T101	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T4	12		T251	12		T189	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	945	1			T56	5		T61	17		T182	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T11	5		T50	2		T186	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T4	11		T238	4		T47	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T10	10		T59	6		T60	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	10		T10	1		T85	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	8		T46	7		T239	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T55	7		T162	12		T237	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T169	8		T118	15		T258	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T11	9		T151	16		T33	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T11	16		T12	4		T62	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	2		T55	1		T85	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	1		T60	2		T184	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	13		T10	3		T156	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T171	1		T166	12		T44	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T62	5		T154	1		T156	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T60	11		T161	16		T174	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	14		T155	4		T237	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1311	1			T9	1		T56	6		T61	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T4	13		T48	2		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T7	1		T158	13		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	1		T11	6		T60	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T4	12		T10	2		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T1	2		T5	9		T7	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T3	1		T5	11		T55	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T46	11		T239	8		T220	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T174	1		T162	13		T237	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T59	1		T154	1		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	379	1			T11	10		T151	17		T155	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T7	1		T11	17		T12	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T245	11		T264	5		T193	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T62	3		T119	11		T123	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17440	1			T2	18		T4	239		T6	163
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T49	16		T249	8		T30	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T151	7		T211	9		T100	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T5	4		T10	2		T156	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T171	2		T166	15		T188	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T62	5		T156	2		T160	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T60	12		T161	17		T174	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T12	9		T237	11		T171	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1287	1			T9	9		T153	4		T156	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T4	2		T42	15		T189	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	4		T238	10		T164	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T60	19		T62	2		T219	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T4	11		T160	5		T238	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T1	22		T5	10		T7	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T5	9		T55	4		T251	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T239	7		T220	10		T268	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T174	3		T237	2		T164	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T59	11		T157	2		T47	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T151	14		T161	7		T237	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	12		T161	8		T100	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T264	6		T193	6		T207	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T62	13		T119	2		T123	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T336	2		T337	11		T308	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T249	7		T281	12		T338	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T155	11		T161	9		T237	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T119	11		T123	1		T170	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T205	14		T318	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T49	2		T205	5		T295	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	1		T60	2		T184	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	13		T10	3		T156	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T151	8		T171	1		T212	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T12	14		T62	5		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T60	11		T161	16		T166	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T154	1		T155	4		T156	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T156	15		T159	1		T174	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T4	13		T48	2		T251	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1287	1			T7	1		T9	1		T56	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T11	6		T219	1		T42	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T4	12		T160	1		T238	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T1	2		T3	1		T7	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	11		T10	2		T85	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T5	9		T46	11		T239	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T3	1		T55	8		T174	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T59	1		T154	1		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	368	1			T11	10		T151	17		T42	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T7	1		T11	17		T12	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17380	1			T2	18		T4	239		T6	163
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T161	7		T237	7		T270	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T119	2		T123	8		T313	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T318	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T295	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T211	9		T100	9		T255	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T5	4		T10	2		T156	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T151	7		T171	2		T242	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	9		T62	5		T160	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T60	12		T161	17		T166	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T156	2		T171	13		T338	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T156	13		T174	12		T51	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T4	2		T251	3		T189	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1243	1			T7	4		T9	9		T153	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T219	14		T42	15		T259	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T4	11		T160	5		T238	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T1	22		T7	3		T10	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	9		T251	15		T119	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	10		T239	7		T220	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T55	4		T174	3		T237	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T59	11		T157	2		T258	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T151	14		T42	14		T33	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	12		T62	13		T161	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22552

1

T1

2

T2

18

T3

3

auto[1]

auto[0]

4267

1

T1

22

T4

13

T5

23