Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26819

1

T1

24

T2

18

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22955

1

T1

13

T2

18

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3864

1

T1

11

T4

15

T5

56

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20638

1

T1

11

T2

18

T3

1

auto[1]

6181

1

T1

13

T3

2

T4

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22590

1

T1

24

T2

18

T3

3

auto[1]

4229

1

T4

23

T5

30

T10

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	231	1			T5	19		T151	15		T163	17
values[0]	49	1			T62	3		T100	10		T290	14
values[1]	972	1			T3	1		T4	23		T10	5
values[2]	801	1			T1	11		T11	10		T62	10
values[3]	621	1			T7	4		T184	1		T157	3
values[4]	838	1			T1	13		T5	17		T7	13
values[5]	651	1			T10	2		T11	17		T55	12
values[6]	667	1			T48	1		T62	16		T159	1
values[7]	781	1			T7	5		T11	6		T12	8
values[8]	641	1			T3	1		T10	32		T155	4
values[9]	3187	1			T3	1		T4	15		T5	20
minimum	17380	1			T2	18		T4	239		T6	163

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	831	1			T3	1		T4	23		T11	10
values[1]	778	1			T1	11		T62	10		T219	15
values[2]	693	1			T7	4		T60	23		T184	1
values[3]	826	1			T1	13		T5	17		T11	17
values[4]	624	1			T7	13		T10	2		T48	1
values[5]	678	1			T12	8		T59	12		T62	16
values[6]	2942	1			T7	5		T9	10		T11	6
values[7]	598	1			T3	1		T10	32		T155	4
values[8]	990	1			T3	1		T4	15		T5	39
values[9]	104	1			T151	15		T186	16		T53	1
minimum	17755	1			T2	18		T4	239		T6	163

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22552

1

T1

2

T2

18

T3

3

auto[1]

4267

1

T1

22

T4

13

T5

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T3	1		T4	12		T11	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T151	15		T156	14		T174	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T161	8		T158	1		T32	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T1	11		T62	6		T219	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T60	13		T160	13		T157	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T7	4		T184	1		T161	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	13		T46	4		T261	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T5	5		T11	1		T85	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T7	13		T55	5		T50	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T10	1		T48	1		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	4		T239	1		T43	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T59	6		T62	14		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1647	1			T7	5		T9	10		T56	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T11	1		T154	1		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T3	1		T155	1		T174	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T10	22		T44	1		T190	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T3	1		T85	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	371	1			T4	3		T5	21		T59	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T297	10		T339	1		T288	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T151	8		T186	1		T53	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17296	1			T2	18		T4	239		T6	163
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T10	3		T12	13		T243	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T4	11		T11	9		T164	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T151	16		T156	14		T237	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T161	8		T158	12		T29	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T62	4		T161	15		T238	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T60	10		T268	7		T101	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T161	11		T32	12		T249	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T46	7		T47	2		T166	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T5	12		T11	16		T85	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T55	7		T50	2		T118	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T10	1		T188	12		T119	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	4		T239	7		T268	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T59	6		T62	2		T155	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	993	1			T56	5		T60	11		T61	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T11	5		T164	10		T44	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T155	3		T287	2		T263	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T10	10		T44	2		T190	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T85	14		T163	16		T239	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T4	12		T5	18		T60	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T297	8		T288	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T151	7		T186	15		T35	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T12	2		T55	1		T85	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T10	2		T12	10		T243	15

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T163	1		T270	1		T104	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T5	11		T151	8		T186	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T62	3		T100	10		T290	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T289	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T3	1		T4	12		T48	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T10	3		T12	13		T151	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T11	1		T158	1		T164	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T1	11		T62	6		T219	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T157	3		T161	8		T167	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	4		T184	1		T161	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T1	13		T7	13		T60	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T5	5		T85	15		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T55	5		T166	8		T188	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T10	1		T11	1		T119	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T239	1		T268	9		T118	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T48	1		T62	14		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T7	5		T12	4		T60	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	1		T59	6		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T3	1		T155	1		T156	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T10	22		T44	2		T216	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1651	1			T3	1		T9	10		T56	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	368	1			T4	3		T5	10		T59	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17230	1			T2	18		T4	239		T6	163
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T163	16		T270	10		T104	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T5	8		T151	7		T186	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T290	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T289	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T4	11		T240	7		T170	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T10	2		T12	10		T151	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T11	9		T158	12		T164	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T62	4		T161	15		T238	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T161	8		T101	16		T242	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T161	11		T237	9		T32	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T60	10		T46	7		T47	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	12		T85	2		T162	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T55	7		T166	5		T188	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T10	1		T11	16		T119	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T239	7		T268	4		T118	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T62	2		T188	12		T49	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T12	4		T60	11		T156	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T11	5		T59	6		T155	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T155	3		T156	6		T241	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T10	10		T44	11		T98	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	967	1			T56	5		T61	17		T85	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T4	12		T5	10		T60	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	2		T55	1		T85	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T3	1		T4	12		T11	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T151	17		T156	15		T174	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T161	9		T158	13		T32	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T1	1		T62	5		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T60	11		T160	1		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T7	1		T184	1		T161	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T1	1		T46	11		T261	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T5	13		T11	17		T85	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T7	1		T55	8		T50	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T10	2		T48	1		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T12	8		T239	8		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T59	7		T62	3		T155	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1339	1			T7	1		T9	1		T56	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	6		T154	1		T164	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	1		T155	4		T174	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T10	11		T44	3		T190	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T3	1		T85	15		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T4	13		T5	20		T59	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T297	9		T339	1		T288	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T151	8		T186	16		T53	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17462	1			T2	18		T4	239		T6	163
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T10	3		T12	14		T243	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T4	11		T62	2		T160	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T151	14		T156	13		T174	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T161	7		T42	15		T167	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T1	10		T62	5		T219	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T60	12		T160	12		T157	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	3		T161	8		T171	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T1	12		T47	3		T171	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	4		T85	14		T237	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T7	12		T55	4		T243	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T188	11		T119	2		T211	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T43	15		T268	8		T251	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T59	5		T62	13		T42	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T7	4		T9	9		T60	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T216	7		T53	2		T98	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T174	3		T43	13		T216	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T10	21		T221	9		T282	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T239	7		T47	2		T271	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T4	2		T5	19		T59	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T297	9		T288	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T151	7		T286	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T240	7		T270	6		T208	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T10	2		T12	9		T243	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T163	17		T270	11		T104	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T5	9		T151	8		T186	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T62	1		T100	1		T290	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T289	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T3	1		T4	12		T48	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	352	1			T10	3		T12	14		T151	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T11	10		T158	13		T164	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	1		T62	5		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T157	1		T161	9		T167	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T7	1		T184	1		T161	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T1	1		T7	1		T60	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T5	13		T85	3		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T55	8		T166	6		T188	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T10	2		T11	17		T119	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T239	8		T268	5		T118	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T48	1		T62	3		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T7	1		T12	8		T60	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T11	6		T59	7		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	1		T155	4		T156	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T10	11		T44	13		T216	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1316	1			T3	1		T9	1		T56	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T4	13		T5	11		T59	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17380	1			T2	18		T4	239		T6	163
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T104	3		T340	5		T341	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T5	10		T151	7		T242	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T62	2		T100	9		T290	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T289	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T4	11		T160	5		T171	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T10	2		T12	9		T151	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T164	4		T166	15		T42	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	10		T62	5		T219	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T157	2		T161	7		T167	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	3		T161	8		T237	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T1	12		T7	12		T60	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	4		T85	14		T237	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T55	4		T166	7		T188	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T119	2		T211	9		T189	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T268	8		T241	7		T296	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T62	13		T42	14		T188	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T7	4		T60	19		T156	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T59	5		T251	14		T53	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T156	2		T174	3		T43	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T10	21		T216	7		T98	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T9	9		T153	4		T250	38
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T4	2		T5	9		T59	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22552

1

T1

2

T2

18

T3

3

auto[1]

auto[0]

4267

1

T1

22

T4

13

T5

23