Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T156	7		T159	1		T46	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T174	1		T47	4		T32	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T151	17		T240	8		T248	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	1		T12	14		T60	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T5	9		T156	13		T237	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T239	8		T171	1		T43	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	11		T10	3		T11	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T59	1		T160	1		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T11	17		T48	1		T85	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T3	1		T4	12		T10	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T1	1		T60	2		T156	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T4	13		T154	1		T164	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1327	1			T7	2		T9	1		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T155	4		T164	1		T171	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T5	13		T164	11		T220	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	1		T10	2		T39	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	419	1			T3	1		T60	12		T62	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T7	1		T12	8		T85	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T261	1		T237	10		T42	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T168	1		T262	10		T244	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17393	1			T2	18		T4	239		T6	163
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T156	2		T171	13		T269	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T174	3		T47	2		T262	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T151	14		T240	7		T167	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T1	12		T12	9		T60	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	10		T156	15		T237	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T171	11		T43	9		T256	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T5	9		T10	2		T62	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T59	11		T160	12		T54	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T238	10		T42	14		T270	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T4	11		T10	21		T161	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T1	10		T156	13		T174	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T4	2		T164	4		T166	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T7	15		T9	9		T55	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T164	11		T171	2		T216	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	4		T220	10		T271	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T39	10		T216	7		T100	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T60	19		T62	5		T151	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	4		T85	14		T160	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T237	7		T42	15		T26	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T262	9		T246	12		T272	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T266	4		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T260	12		T265	15		T266	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T221	11		T259	12		T267	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T11	10		T156	7		T46	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T174	1		T47	4		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T159	1		T240	8		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	1		T12	14		T239	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T151	17		T156	13		T237	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T60	11		T239	8		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T5	20		T10	3		T11	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T256	14		T254	11		T51	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T11	17		T48	1		T85	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T3	1		T4	12		T10	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T1	1		T60	2		T156	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T4	13		T164	10		T172	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T7	1		T48	1		T59	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T154	1		T155	4		T211	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T5	13		T7	1		T9	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T10	2		T164	1		T171	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	505	1			T3	1		T60	12		T62	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T3	1		T7	1		T12	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17380	1			T2	18		T4	239		T6	163
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T260	13		T265	6		T266	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T221	10		T259	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T156	2		T171	13		T189	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T174	3		T47	2		T262	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T240	7		T167	4		T188	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	12		T12	9		T239	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T151	14		T156	15		T237	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T60	12		T171	11		T43	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T5	19		T10	2		T62	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T256	12		T254	13		T54	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T238	10		T42	14		T268	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T4	11		T10	21		T59	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T1	10		T156	13		T174	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T4	2		T164	4		T216	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T7	12		T59	5		T62	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T242	11		T243	14		T207	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1259	1			T5	4		T7	3		T9	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T164	11		T171	2		T39	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	386	1			T60	19		T62	5		T151	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T7	4		T85	14		T160	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22552

1

T1

2

T2

18

T3

3

auto[1]

auto[0]

4267

1

T1

22

T4

13

T5

23