Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26819

1

T1

24

T2

18

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23099

1

T2

18

T3

2

T4

254

auto[ADC_CTRL_FILTER_COND_OUT]

3720

1

T1

24

T3

1

T4

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20747

1

T2

18

T4

262

T5

39

auto[1]

6072

1

T1

24

T3

3

T4

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22590

1

T1

24

T2

18

T3

3

auto[1]

4229

1

T4

23

T5

30

T10

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T175	1		-	-		-	-
values[0]	43	1			T151	15		T212	1		T97	1
values[1]	883	1			T155	4		T156	28		T219	15
values[2]	870	1			T1	24		T7	13		T10	32
values[3]	697	1			T10	2		T55	12		T60	2
values[4]	621	1			T3	1		T7	5		T10	5
values[5]	3045	1			T3	1		T4	23		T5	19
values[6]	749	1			T5	17		T7	4		T11	6
values[7]	725	1			T5	20		T12	23		T48	1
values[8]	619	1			T11	10		T60	54		T156	9
values[9]	1186	1			T3	1		T4	15		T59	12
minimum	17380	1			T2	18		T4	239		T6	163

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1170	1			T1	13		T7	13		T10	32
values[1]	730	1			T48	1		T161	20		T237	34
values[2]	742	1			T1	11		T10	2		T12	8
values[3]	2750	1			T3	1		T5	19		T7	5
values[4]	904	1			T3	1		T4	23		T11	23
values[5]	643	1			T7	4		T154	2		T151	31
values[6]	791	1			T5	37		T11	10		T12	23
values[7]	561	1			T4	15		T60	23		T62	16
values[8]	826	1			T3	1		T59	12		T154	1
values[9]	274	1			T237	17		T171	14		T188	29
minimum	17428	1			T2	18		T4	239		T6	163

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22552

1

T1

2

T2

18

T3

3

auto[1]

4267

1

T1

22

T4

13

T5

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T7	13		T10	22		T151	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T1	13		T156	16		T219	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T48	1		T268	9		T50	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T161	9		T237	15		T49	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T12	4		T55	5		T157	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T1	11		T10	1		T60	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1598	1			T3	1		T5	11		T7	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T273	1		T175	1		T259	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	1		T11	1		T85	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T4	12		T11	1		T156	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T164	1		T47	9		T166	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	4		T154	2		T151	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	5		T12	13		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T5	10		T11	1		T85	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T4	3		T60	13		T62	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T261	1		T116	1		T186	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T59	6		T159	1		T161	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T3	1		T154	1		T160	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T188	15		T51	1		T117	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T237	8		T171	14		T110	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17245	1			T2	18		T4	239		T6	163
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T274	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T10	10		T151	7		T155	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T156	12		T47	2		T166	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T268	4		T50	2		T63	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T161	11		T237	19		T49	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T12	4		T55	7		T164	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T10	1		T60	1		T46	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	931	1			T5	8		T10	2		T56	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T273	8		T259	11		T245	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T11	16		T85	14		T162	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T4	11		T11	5		T156	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T164	10		T47	2		T166	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T151	16		T239	7		T44	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T5	12		T12	10		T60	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	10		T11	9		T85	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T4	12		T60	10		T62	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T186	16		T241	11		T242	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T59	6		T161	15		T238	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T239	7		T244	12		T275	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T188	14		T117	10		T249	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T237	9		T110	11		T252	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	2		T55	1		T85	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T274	14		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T175	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T151	8		T97	1		T194	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T212	1		T276	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T155	1		T163	1		T43	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T156	16		T219	15		T47	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T7	13		T10	22		T48	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T1	24		T161	9		T237	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T55	5		T157	3		T268	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T10	1		T60	1		T62	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T3	1		T7	5		T10	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T158	1		T163	1		T211	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1608	1			T3	1		T5	11		T9	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T4	12		T156	14		T174	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	5		T85	1		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T7	4		T11	1		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	13		T48	1		T42	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T5	10		T85	15		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T60	33		T156	3		T174	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	1		T261	1		T174	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T4	3		T59	6		T62	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	375	1			T3	1		T154	1		T160	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17230	1			T2	18		T4	239		T6	163
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T151	7		T277	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T155	3		T49	1		T256	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T156	12		T47	2		T166	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T10	10		T249	14		T278	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T161	11		T237	19		T49	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T55	7		T268	4		T50	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T10	1		T60	1		T46	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T10	2		T12	4		T62	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T158	12		T163	16		T211	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1020	1			T5	8		T11	16		T56	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T4	11		T156	14		T51	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T5	12		T85	14		T164	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	5		T151	16		T44	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T12	10		T268	7		T254	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	10		T85	2		T239	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T60	21		T156	6		T165	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T11	9		T186	16		T241	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T4	12		T59	6		T62	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T237	9		T239	7		T244	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	2		T55	1		T85	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T7	1		T10	11		T151	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	385	1			T1	1		T156	13		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T48	1		T268	5		T50	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T161	12		T237	21		T49	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T12	8		T55	8		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	1		T10	2		T60	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T3	1		T5	9		T7	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T273	9		T175	1		T259	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T3	1		T11	17		T85	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T4	12		T11	6		T156	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T164	11		T47	8		T166	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T7	1		T154	2		T151	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T5	13		T12	14		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T5	11		T11	10		T85	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T4	13		T60	11		T62	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T261	1		T116	1		T186	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T59	7		T159	1		T161	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	1		T154	1		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T188	15		T51	1		T117	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T237	10		T171	1		T110	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17390	1			T2	18		T4	239		T6	163
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T274	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T7	12		T10	21		T151	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T1	12		T156	15		T219	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T268	8		T63	6		T262	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T161	8		T237	13		T279	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T55	4		T157	2		T164	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T1	10		T62	2		T220	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T5	10		T7	4		T9	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T259	6		T280	10		T281	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T238	4		T240	7		T98	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T4	11		T156	13		T174	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T47	3		T166	7		T254	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T7	3		T151	14		T160	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T5	4		T12	9		T60	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T5	9		T85	14		T39	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T4	2		T60	12		T62	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T241	7		T242	11		T282	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T59	5		T161	17		T238	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T160	12		T174	12		T164	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T188	14		T249	7		T283	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T237	7		T171	13		T110	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T277	14		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T274	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T175	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T151	8		T97	1		T194	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T212	1		T276	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T155	4		T163	1		T43	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T156	13		T219	1		T47	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T7	1		T10	11		T48	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T1	2		T161	12		T237	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T55	8		T157	1		T268	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T10	2		T60	2		T62	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	1		T7	1		T10	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T158	13		T163	17		T211	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1361	1			T3	1		T5	9		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T4	12		T156	15		T174	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T5	13		T85	15		T164	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T7	1		T11	6		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T12	14		T48	1		T42	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T5	11		T85	3		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T60	23		T156	7		T174	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	10		T261	1		T174	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	357	1			T4	13		T59	7		T62	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T3	1		T154	1		T160	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17380	1			T2	18		T4	239		T6	163
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T151	7		T277	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T43	13		T256	12		T217	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T156	15		T219	14		T47	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T7	12		T10	21		T249	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	22		T161	8		T237	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T55	4		T157	2		T268	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T62	2		T220	10		T166	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T7	4		T10	2		T59	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T211	9		T26	2		T259	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1267	1			T5	10		T9	9		T153	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T4	11		T156	13		T174	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	4		T47	3		T240	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T7	3		T151	14		T160	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	9		T42	14		T268	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T5	9		T85	14		T171	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T60	31		T156	2		T174	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T174	12		T242	11		T269	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T4	2		T59	5		T62	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T160	12		T237	7		T164	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22552

1

T1

2

T2

18

T3

3

auto[1]

auto[0]

4267

1

T1

22

T4

13

T5

23