Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26819

1

T1

24

T2

18

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22898

1

T1

13

T2

18

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3921

1

T1

11

T4

15

T5

56

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20584

1

T1

11

T2

18

T3

1

auto[1]

6235

1

T1

13

T3

2

T4

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22590

1

T1

24

T2

18

T3

3

auto[1]

4229

1

T4

23

T5

30

T10

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	59	1			T186	16		T242	23		T284	20
values[0]	86	1			T62	3		T100	10		T128	13
values[1]	946	1			T3	1		T4	23		T10	5
values[2]	746	1			T11	10		T62	10		T219	15
values[3]	697	1			T1	11		T7	4		T184	1
values[4]	832	1			T1	13		T5	17		T7	13
values[5]	650	1			T10	2		T11	17		T55	12
values[6]	628	1			T48	1		T62	16		T154	1
values[7]	828	1			T7	5		T11	6		T12	8
values[8]	634	1			T3	1		T5	20		T10	32
values[9]	3333	1			T3	1		T4	15		T5	19
minimum	17380	1			T2	18		T4	239		T6	163

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1258	1			T3	1		T4	23		T10	5
values[1]	717	1			T1	11		T62	10		T219	15
values[2]	693	1			T5	17		T7	4		T60	23
values[3]	860	1			T1	13		T11	17		T85	17
values[4]	611	1			T7	13		T10	2		T48	1
values[5]	679	1			T59	12		T155	11		T156	28
values[6]	2926	1			T7	5		T9	10		T11	6
values[7]	628	1			T3	1		T10	32		T155	4
values[8]	878	1			T3	1		T4	15		T5	39
values[9]	189	1			T163	17		T186	16		T53	1
minimum	17380	1			T2	18		T4	239		T6	163

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22552

1

T1

2

T2

18

T3

3

auto[1]

4267

1

T1

22

T4

13

T5

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T3	1		T4	12		T11	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T10	3		T12	13		T151	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T62	6		T158	1		T32	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T1	11		T219	15		T161	27
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T60	13		T160	13		T157	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T5	5		T7	4		T184	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T1	13		T85	15		T46	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T11	1		T154	1		T162	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T7	13		T55	5		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T10	1		T48	1		T62	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T156	16		T239	1		T268	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T59	6		T155	1		T172	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1622	1			T7	5		T9	10		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T154	1		T164	1		T116	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T3	1		T155	1		T174	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T10	22		T44	1		T51	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T3	1		T85	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T4	3		T5	21		T59	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T163	1		T53	1		T285	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T186	1		T35	1		T286	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17230	1			T2	18		T4	239		T6	163
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T4	11		T11	9		T164	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	400	1			T10	2		T12	10		T151	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T62	4		T158	12		T54	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T161	26		T238	4		T237	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T60	10		T161	8		T268	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	12		T32	12		T249	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T85	2		T46	7		T166	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T11	16		T162	12		T237	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T55	7		T50	2		T118	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T10	1		T62	2		T188	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T156	12		T239	7		T268	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T59	6		T155	10		T49	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	995	1			T11	5		T12	4		T56	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T164	10		T53	2		T98	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T155	3		T287	2		T263	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T10	10		T44	2		T190	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T85	14		T239	7		T47	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T4	12		T5	18		T60	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T163	16		T285	9		T288	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T186	15		T35	3		T286	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	2		T55	1		T85	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T284	11		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T186	1		T242	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T62	3		T100	10		T108	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T128	1		T289	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	1		T4	12		T48	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T10	3		T12	13		T151	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T11	1		T62	6		T164	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T219	15		T161	18		T238	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T157	3		T161	8		T167	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T1	11		T7	4		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T1	13		T7	13		T60	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	5		T154	1		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T55	5		T166	8		T188	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T10	1		T11	1		T119	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T163	1		T239	1		T268	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T48	1		T62	14		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T7	5		T11	1		T12	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T59	6		T155	1		T164	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T3	1		T155	1		T174	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T5	10		T10	22		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1683	1			T3	1		T9	10		T56	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	404	1			T4	3		T5	11		T59	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17230	1			T2	18		T4	239		T6	163
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T284	9		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T186	15		T242	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T108	11		T290	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T128	12		T289	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T4	11		T158	12		T240	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T10	2		T12	10		T151	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T11	9		T62	4		T164	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T161	15		T238	4		T237	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T161	8		T101	16		T242	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T161	11		T237	9		T32	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T60	10		T85	2		T46	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T5	12		T162	12		T237	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T55	7		T166	5		T188	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T10	1		T11	16		T119	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T239	7		T268	4		T118	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T62	2		T188	12		T49	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T11	5		T12	4		T60	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T59	6		T155	10		T164	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T155	3		T239	7		T44	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T5	10		T10	10		T44	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	996	1			T56	5		T61	17		T85	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T4	12		T5	8		T60	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	2		T55	1		T85	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T3	1		T4	12		T11	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	466	1			T10	3		T12	14		T151	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T62	5		T158	13		T32	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T1	1		T219	1		T161	28
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T60	11		T160	1		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T5	13		T7	1		T184	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T1	1		T85	3		T46	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T11	17		T154	1		T162	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T7	1		T55	8		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T10	2		T48	1		T62	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T156	13		T239	8		T268	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T59	7		T155	11		T172	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T7	1		T9	1		T11	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T154	1		T164	11		T116	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T3	1		T155	4		T174	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T10	11		T44	3		T51	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T3	1		T85	15		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T4	13		T5	20		T59	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T163	17		T53	1		T285	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T186	16		T35	4		T286	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17380	1			T2	18		T4	239		T6	163
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T4	11		T62	2		T160	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T10	2		T12	9		T151	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T62	5		T42	15		T167	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T1	10		T219	14		T161	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T60	12		T160	12		T157	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	4		T7	3		T171	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T1	12		T85	14		T171	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T237	7		T220	10		T47	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T7	12		T55	4		T241	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T62	13		T188	11		T119	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T156	15		T268	8		T251	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T59	5		T42	14		T43	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1274	1			T7	4		T9	9		T60	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T216	7		T53	2		T98	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T174	3		T43	13		T216	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T10	21		T221	9		T282	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T239	7		T47	2		T271	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T4	2		T5	19		T59	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T288	9		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T286	11		T110	10		T275	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T284	10		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T186	16		T242	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T62	1		T100	1		T108	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T128	13		T289	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T3	1		T4	12		T48	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	382	1			T10	3		T12	14		T151	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T11	10		T62	5		T164	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T219	1		T161	16		T238	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T157	1		T161	9		T167	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T1	1		T7	1		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	1		T7	1		T60	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T5	13		T154	1		T162	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T55	8		T166	6		T188	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T10	2		T11	17		T119	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T163	1		T239	8		T268	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T48	1		T62	3		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T7	1		T11	6		T12	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T59	7		T155	11		T164	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	1		T155	4		T174	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T5	11		T10	11		T44	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1362	1			T3	1		T9	1		T56	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T4	13		T5	9		T59	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17380	1			T2	18		T4	239		T6	163
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T284	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T242	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T62	2		T100	9		T108	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T289	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T4	11		T160	5		T171	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T10	2		T12	9		T151	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T62	5		T164	4		T166	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T219	14		T161	17		T238	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T157	2		T161	7		T167	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	10		T7	3		T161	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	12		T7	12		T60	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	4		T237	7		T220	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T55	4		T166	7		T188	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T119	2		T211	9		T189	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T268	8		T241	7		T262	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T62	13		T42	14		T188	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T7	4		T60	19		T156	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T59	5		T43	15		T251	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T174	3		T239	7		T43	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T5	9		T10	21		T216	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T9	9		T153	4		T250	38
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T4	2		T5	10		T59	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22552

1

T1

2

T2

18

T3

3

auto[1]

auto[0]

4267

1

T1

22

T4

13

T5

23