interrupt_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
223 |
1 |
|
|
T10 |
22 |
|
T155 |
1 |
|
T163 |
1 |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
246 |
1 |
|
|
T1 |
13 |
|
T156 |
16 |
|
T219 |
15 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
234 |
1 |
|
|
T7 |
13 |
|
T48 |
1 |
|
T55 |
5 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
220 |
1 |
|
|
T161 |
9 |
|
T237 |
15 |
|
T49 |
1 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
164 |
1 |
|
|
T12 |
4 |
|
T157 |
3 |
|
T43 |
10 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
221 |
1 |
|
|
T1 |
11 |
|
T10 |
1 |
|
T60 |
1 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
1575 |
1 |
|
|
T3 |
2 |
|
T5 |
11 |
|
T7 |
5 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
120 |
1 |
|
|
T273 |
1 |
|
T175 |
1 |
|
T259 |
7 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
214 |
1 |
|
|
T11 |
1 |
|
T85 |
1 |
|
T155 |
1 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
250 |
1 |
|
|
T4 |
12 |
|
T11 |
1 |
|
T156 |
14 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
166 |
1 |
|
|
T5 |
5 |
|
T164 |
1 |
|
T47 |
9 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
143 |
1 |
|
|
T7 |
4 |
|
T154 |
2 |
|
T151 |
15 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
194 |
1 |
|
|
T12 |
13 |
|
T48 |
1 |
|
T60 |
20 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
298 |
1 |
|
|
T5 |
10 |
|
T11 |
1 |
|
T85 |
15 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
185 |
1 |
|
|
T4 |
3 |
|
T60 |
13 |
|
T156 |
3 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
99 |
1 |
|
|
T261 |
1 |
|
T116 |
1 |
|
T186 |
1 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
237 |
1 |
|
|
T59 |
6 |
|
T62 |
14 |
|
T159 |
1 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
343 |
1 |
|
|
T3 |
1 |
|
T154 |
1 |
|
T160 |
13 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
35 |
1 |
|
|
T116 |
1 |
|
T249 |
8 |
|
T283 |
4 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
46 |
1 |
|
|
T171 |
14 |
|
T252 |
15 |
|
T15 |
5 |
auto[0] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
17315 |
1 |
|
|
T2 |
18 |
|
T4 |
239 |
|
T6 |
163 |
auto[0] |
minimum |
auto[ADC_CTRL_FILTER_COND_OUT] |
62 |
1 |
|
|
T166 |
1 |
|
T170 |
1 |
|
T28 |
21 |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
176 |
1 |
|
|
T10 |
10 |
|
T155 |
3 |
|
T49 |
1 |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
280 |
1 |
|
|
T156 |
12 |
|
T47 |
2 |
|
T44 |
9 |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
151 |
1 |
|
|
T55 |
7 |
|
T268 |
4 |
|
T291 |
14 |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
182 |
1 |
|
|
T161 |
11 |
|
T237 |
19 |
|
T49 |
11 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
138 |
1 |
|
|
T12 |
4 |
|
T50 |
2 |
|
T186 |
15 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
167 |
1 |
|
|
T10 |
1 |
|
T60 |
1 |
|
T46 |
7 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
931 |
1 |
|
|
T5 |
8 |
|
T10 |
2 |
|
T56 |
5 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
104 |
1 |
|
|
T273 |
8 |
|
T259 |
11 |
|
T245 |
12 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
233 |
1 |
|
|
T11 |
16 |
|
T85 |
14 |
|
T155 |
10 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
200 |
1 |
|
|
T4 |
11 |
|
T11 |
5 |
|
T156 |
14 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
180 |
1 |
|
|
T5 |
12 |
|
T164 |
10 |
|
T47 |
2 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
150 |
1 |
|
|
T151 |
16 |
|
T239 |
7 |
|
T44 |
2 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
101 |
1 |
|
|
T12 |
10 |
|
T60 |
11 |
|
T268 |
7 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
236 |
1 |
|
|
T5 |
10 |
|
T11 |
9 |
|
T85 |
2 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
157 |
1 |
|
|
T4 |
12 |
|
T60 |
10 |
|
T156 |
6 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
93 |
1 |
|
|
T186 |
16 |
|
T241 |
4 |
|
T242 |
11 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
193 |
1 |
|
|
T59 |
6 |
|
T62 |
2 |
|
T161 |
15 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
189 |
1 |
|
|
T237 |
9 |
|
T239 |
7 |
|
T244 |
12 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
46 |
1 |
|
|
T249 |
7 |
|
T283 |
3 |
|
T252 |
11 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
26 |
1 |
|
|
T252 |
12 |
|
T15 |
2 |
|
T292 |
12 |
auto[1] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
225 |
1 |
|
|
T12 |
2 |
|
T55 |
1 |
|
T85 |
1 |
auto[1] |
minimum |
auto[ADC_CTRL_FILTER_COND_OUT] |
71 |
1 |
|
|
T166 |
8 |
|
T170 |
5 |
|
T28 |
14 |
interrupt_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
maximum |
auto[ADC_CTRL_FILTER_COND_IN] |
67 |
1 |
|
|
T59 |
6 |
|
T32 |
1 |
|
T117 |
1 |
auto[0] |
maximum |
auto[ADC_CTRL_FILTER_COND_OUT] |
108 |
1 |
|
|
T171 |
14 |
|
T216 |
11 |
|
T100 |
10 |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
17 |
1 |
|
|
T97 |
1 |
|
T194 |
1 |
|
T277 |
15 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
231 |
1 |
|
|
T10 |
22 |
|
T151 |
8 |
|
T155 |
1 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
208 |
1 |
|
|
T156 |
16 |
|
T219 |
15 |
|
T47 |
4 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
235 |
1 |
|
|
T7 |
13 |
|
T48 |
1 |
|
T242 |
1 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
267 |
1 |
|
|
T1 |
24 |
|
T161 |
9 |
|
T237 |
15 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
164 |
1 |
|
|
T55 |
5 |
|
T157 |
3 |
|
T268 |
9 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
248 |
1 |
|
|
T10 |
1 |
|
T60 |
1 |
|
T62 |
3 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
212 |
1 |
|
|
T3 |
1 |
|
T7 |
5 |
|
T10 |
3 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
111 |
1 |
|
|
T158 |
1 |
|
T163 |
1 |
|
T211 |
10 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
1596 |
1 |
|
|
T3 |
1 |
|
T5 |
11 |
|
T9 |
10 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
246 |
1 |
|
|
T4 |
12 |
|
T156 |
14 |
|
T174 |
13 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
178 |
1 |
|
|
T5 |
5 |
|
T85 |
1 |
|
T162 |
1 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
168 |
1 |
|
|
T7 |
4 |
|
T11 |
1 |
|
T154 |
1 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
170 |
1 |
|
|
T12 |
13 |
|
T42 |
15 |
|
T254 |
14 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
264 |
1 |
|
|
T5 |
10 |
|
T11 |
1 |
|
T85 |
15 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
191 |
1 |
|
|
T4 |
3 |
|
T48 |
1 |
|
T60 |
33 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
155 |
1 |
|
|
T261 |
1 |
|
T174 |
13 |
|
T271 |
9 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
251 |
1 |
|
|
T62 |
14 |
|
T159 |
1 |
|
T161 |
18 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
273 |
1 |
|
|
T3 |
1 |
|
T154 |
1 |
|
T160 |
13 |
auto[0] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
17230 |
1 |
|
|
T2 |
18 |
|
T4 |
239 |
|
T6 |
163 |
auto[1] |
maximum |
auto[ADC_CTRL_FILTER_COND_IN] |
74 |
1 |
|
|
T59 |
6 |
|
T117 |
10 |
|
T119 |
10 |
auto[1] |
maximum |
auto[ADC_CTRL_FILTER_COND_OUT] |
36 |
1 |
|
|
T275 |
7 |
|
T293 |
11 |
|
T209 |
9 |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
9 |
1 |
|
|
T277 |
9 |
|
- |
- |
|
- |
- |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
190 |
1 |
|
|
T10 |
10 |
|
T151 |
7 |
|
T155 |
3 |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
254 |
1 |
|
|
T156 |
12 |
|
T47 |
2 |
|
T166 |
8 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
155 |
1 |
|
|
T249 |
14 |
|
T262 |
9 |
|
T278 |
15 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
249 |
1 |
|
|
T161 |
11 |
|
T237 |
19 |
|
T49 |
11 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
158 |
1 |
|
|
T55 |
7 |
|
T268 |
4 |
|
T50 |
2 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
144 |
1 |
|
|
T10 |
1 |
|
T60 |
1 |
|
T46 |
7 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
117 |
1 |
|
|
T10 |
2 |
|
T12 |
4 |
|
T62 |
4 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
129 |
1 |
|
|
T158 |
12 |
|
T163 |
16 |
|
T211 |
11 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
998 |
1 |
|
|
T5 |
8 |
|
T11 |
16 |
|
T56 |
5 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
185 |
1 |
|
|
T4 |
11 |
|
T156 |
14 |
|
T51 |
5 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
226 |
1 |
|
|
T5 |
12 |
|
T85 |
14 |
|
T162 |
12 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
171 |
1 |
|
|
T11 |
5 |
|
T151 |
16 |
|
T44 |
2 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
83 |
1 |
|
|
T12 |
10 |
|
T254 |
10 |
|
T101 |
1 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
228 |
1 |
|
|
T5 |
10 |
|
T11 |
9 |
|
T85 |
2 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
176 |
1 |
|
|
T4 |
12 |
|
T60 |
21 |
|
T156 |
6 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
122 |
1 |
|
|
T186 |
16 |
|
T241 |
4 |
|
T242 |
11 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
195 |
1 |
|
|
T62 |
2 |
|
T161 |
15 |
|
T238 |
9 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
180 |
1 |
|
|
T237 |
9 |
|
T239 |
7 |
|
T244 |
12 |
auto[1] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
150 |
1 |
|
|
T12 |
2 |
|
T55 |
1 |
|
T85 |
1 |
wakeup_cp | min_v_cp | cond_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
215 |
1 |
|
|
T10 |
11 |
|
T155 |
4 |
|
T163 |
1 |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
320 |
1 |
|
|
T1 |
1 |
|
T156 |
13 |
|
T219 |
1 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
196 |
1 |
|
|
T7 |
1 |
|
T48 |
1 |
|
T55 |
8 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
221 |
1 |
|
|
T161 |
12 |
|
T237 |
21 |
|
T49 |
12 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
181 |
1 |
|
|
T12 |
8 |
|
T157 |
1 |
|
T43 |
1 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
210 |
1 |
|
|
T1 |
1 |
|
T10 |
2 |
|
T60 |
2 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
1263 |
1 |
|
|
T3 |
2 |
|
T5 |
9 |
|
T7 |
1 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
127 |
1 |
|
|
T273 |
9 |
|
T175 |
1 |
|
T259 |
12 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
273 |
1 |
|
|
T11 |
17 |
|
T85 |
15 |
|
T155 |
11 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
254 |
1 |
|
|
T4 |
12 |
|
T11 |
6 |
|
T156 |
15 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
225 |
1 |
|
|
T5 |
13 |
|
T164 |
11 |
|
T47 |
8 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
193 |
1 |
|
|
T7 |
1 |
|
T154 |
2 |
|
T151 |
17 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
135 |
1 |
|
|
T12 |
14 |
|
T48 |
1 |
|
T60 |
12 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
290 |
1 |
|
|
T5 |
11 |
|
T11 |
10 |
|
T85 |
3 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
193 |
1 |
|
|
T4 |
13 |
|
T60 |
11 |
|
T156 |
7 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
122 |
1 |
|
|
T261 |
1 |
|
T116 |
1 |
|
T186 |
17 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
247 |
1 |
|
|
T59 |
7 |
|
T62 |
3 |
|
T159 |
1 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
244 |
1 |
|
|
T3 |
1 |
|
T154 |
1 |
|
T160 |
1 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
59 |
1 |
|
|
T116 |
1 |
|
T249 |
8 |
|
T283 |
4 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
34 |
1 |
|
|
T171 |
1 |
|
T252 |
13 |
|
T15 |
6 |
auto[0] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
17470 |
1 |
|
|
T2 |
18 |
|
T4 |
239 |
|
T6 |
163 |
auto[0] |
minimum |
auto[ADC_CTRL_FILTER_COND_OUT] |
80 |
1 |
|
|
T166 |
9 |
|
T170 |
6 |
|
T28 |
15 |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
184 |
1 |
|
|
T10 |
21 |
|
T43 |
13 |
|
T256 |
12 |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_OUT] |
206 |
1 |
|
|
T1 |
12 |
|
T156 |
15 |
|
T219 |
14 |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
189 |
1 |
|
|
T7 |
12 |
|
T55 |
4 |
|
T268 |
8 |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
181 |
1 |
|
|
T161 |
8 |
|
T237 |
13 |
|
T279 |
11 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
121 |
1 |
|
|
T157 |
2 |
|
T43 |
9 |
|
T54 |
1 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
178 |
1 |
|
|
T1 |
10 |
|
T62 |
2 |
|
T220 |
10 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
1243 |
1 |
|
|
T5 |
10 |
|
T7 |
4 |
|
T9 |
9 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
97 |
1 |
|
|
T259 |
6 |
|
T246 |
12 |
|
T280 |
10 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
174 |
1 |
|
|
T238 |
4 |
|
T240 |
7 |
|
T98 |
13 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
196 |
1 |
|
|
T4 |
11 |
|
T156 |
13 |
|
T174 |
12 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
121 |
1 |
|
|
T5 |
4 |
|
T47 |
3 |
|
T166 |
7 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
100 |
1 |
|
|
T7 |
3 |
|
T151 |
14 |
|
T160 |
5 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
160 |
1 |
|
|
T12 |
9 |
|
T60 |
19 |
|
T42 |
14 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
244 |
1 |
|
|
T5 |
9 |
|
T85 |
14 |
|
T171 |
2 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
149 |
1 |
|
|
T4 |
2 |
|
T60 |
12 |
|
T156 |
2 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
70 |
1 |
|
|
T242 |
11 |
|
T282 |
1 |
|
T208 |
8 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
183 |
1 |
|
|
T59 |
5 |
|
T62 |
13 |
|
T161 |
17 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
288 |
1 |
|
|
T160 |
12 |
|
T174 |
12 |
|
T237 |
7 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
22 |
1 |
|
|
T249 |
7 |
|
T283 |
3 |
|
T294 |
5 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
38 |
1 |
|
|
T171 |
13 |
|
T252 |
14 |
|
T15 |
1 |
auto[1] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
70 |
1 |
|
|
T151 |
7 |
|
T264 |
6 |
|
T36 |
7 |
auto[1] |
minimum |
auto[ADC_CTRL_FILTER_COND_OUT] |
53 |
1 |
|
|
T28 |
20 |
|
T253 |
11 |
|
T295 |
12 |
wakeup_cp | max_v_cp | cond_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
maximum |
auto[ADC_CTRL_FILTER_COND_IN] |
96 |
1 |
|
|
T59 |
7 |
|
T32 |
1 |
|
T117 |
11 |
auto[0] |
maximum |
auto[ADC_CTRL_FILTER_COND_OUT] |
53 |
1 |
|
|
T171 |
1 |
|
T216 |
1 |
|
T100 |
1 |
auto[0] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
12 |
1 |
|
|
T97 |
1 |
|
T194 |
1 |
|
T277 |
10 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
231 |
1 |
|
|
T10 |
11 |
|
T151 |
8 |
|
T155 |
4 |
auto[0] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
291 |
1 |
|
|
T156 |
13 |
|
T219 |
1 |
|
T47 |
4 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
198 |
1 |
|
|
T7 |
1 |
|
T48 |
1 |
|
T242 |
1 |
auto[0] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
296 |
1 |
|
|
T1 |
2 |
|
T161 |
12 |
|
T237 |
21 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
200 |
1 |
|
|
T55 |
8 |
|
T157 |
1 |
|
T268 |
5 |
auto[0] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
182 |
1 |
|
|
T10 |
2 |
|
T60 |
2 |
|
T62 |
1 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
155 |
1 |
|
|
T3 |
1 |
|
T7 |
1 |
|
T10 |
3 |
auto[0] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
154 |
1 |
|
|
T158 |
13 |
|
T163 |
17 |
|
T211 |
12 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
1334 |
1 |
|
|
T3 |
1 |
|
T5 |
9 |
|
T9 |
1 |
auto[0] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
234 |
1 |
|
|
T4 |
12 |
|
T156 |
15 |
|
T174 |
1 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
272 |
1 |
|
|
T5 |
13 |
|
T85 |
15 |
|
T162 |
13 |
auto[0] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
220 |
1 |
|
|
T7 |
1 |
|
T11 |
6 |
|
T154 |
1 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
117 |
1 |
|
|
T12 |
14 |
|
T42 |
1 |
|
T254 |
11 |
auto[0] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
273 |
1 |
|
|
T5 |
11 |
|
T11 |
10 |
|
T85 |
3 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
214 |
1 |
|
|
T4 |
13 |
|
T48 |
1 |
|
T60 |
23 |
auto[0] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
163 |
1 |
|
|
T261 |
1 |
|
T174 |
1 |
|
T271 |
1 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
248 |
1 |
|
|
T62 |
3 |
|
T159 |
1 |
|
T161 |
16 |
auto[0] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
229 |
1 |
|
|
T3 |
1 |
|
T154 |
1 |
|
T160 |
1 |
auto[0] |
minimum |
auto[ADC_CTRL_FILTER_COND_IN] |
17380 |
1 |
|
|
T2 |
18 |
|
T4 |
239 |
|
T6 |
163 |
auto[1] |
maximum |
auto[ADC_CTRL_FILTER_COND_IN] |
45 |
1 |
|
|
T59 |
5 |
|
T119 |
2 |
|
T296 |
1 |
auto[1] |
maximum |
auto[ADC_CTRL_FILTER_COND_OUT] |
91 |
1 |
|
|
T171 |
13 |
|
T216 |
10 |
|
T100 |
9 |
auto[1] |
values[0] |
auto[ADC_CTRL_FILTER_COND_IN] |
14 |
1 |
|
|
T277 |
14 |
|
- |
- |
|
- |
- |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_IN] |
190 |
1 |
|
|
T10 |
21 |
|
T151 |
7 |
|
T43 |
13 |
auto[1] |
values[1] |
auto[ADC_CTRL_FILTER_COND_OUT] |
171 |
1 |
|
|
T156 |
15 |
|
T219 |
14 |
|
T47 |
2 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_IN] |
192 |
1 |
|
|
T7 |
12 |
|
T249 |
17 |
|
T262 |
9 |
auto[1] |
values[2] |
auto[ADC_CTRL_FILTER_COND_OUT] |
220 |
1 |
|
|
T1 |
22 |
|
T161 |
8 |
|
T237 |
13 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_IN] |
122 |
1 |
|
|
T55 |
4 |
|
T157 |
2 |
|
T268 |
8 |
auto[1] |
values[3] |
auto[ADC_CTRL_FILTER_COND_OUT] |
210 |
1 |
|
|
T62 |
2 |
|
T220 |
10 |
|
T166 |
15 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_IN] |
174 |
1 |
|
|
T7 |
4 |
|
T10 |
2 |
|
T59 |
11 |
auto[1] |
values[4] |
auto[ADC_CTRL_FILTER_COND_OUT] |
86 |
1 |
|
|
T211 |
9 |
|
T26 |
2 |
|
T280 |
10 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_IN] |
1260 |
1 |
|
|
T5 |
10 |
|
T9 |
9 |
|
T153 |
4 |
auto[1] |
values[5] |
auto[ADC_CTRL_FILTER_COND_OUT] |
197 |
1 |
|
|
T4 |
11 |
|
T156 |
13 |
|
T174 |
12 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_IN] |
132 |
1 |
|
|
T5 |
4 |
|
T47 |
3 |
|
T240 |
7 |
auto[1] |
values[6] |
auto[ADC_CTRL_FILTER_COND_OUT] |
119 |
1 |
|
|
T7 |
3 |
|
T151 |
14 |
|
T160 |
5 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_IN] |
136 |
1 |
|
|
T12 |
9 |
|
T42 |
14 |
|
T254 |
13 |
auto[1] |
values[7] |
auto[ADC_CTRL_FILTER_COND_OUT] |
219 |
1 |
|
|
T5 |
9 |
|
T85 |
14 |
|
T171 |
2 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_IN] |
153 |
1 |
|
|
T4 |
2 |
|
T60 |
31 |
|
T156 |
2 |
auto[1] |
values[8] |
auto[ADC_CTRL_FILTER_COND_OUT] |
114 |
1 |
|
|
T174 |
12 |
|
T271 |
8 |
|
T242 |
11 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_IN] |
198 |
1 |
|
|
T62 |
13 |
|
T161 |
17 |
|
T238 |
10 |
auto[1] |
values[9] |
auto[ADC_CTRL_FILTER_COND_OUT] |
224 |
1 |
|
|
T160 |
12 |
|
T237 |
7 |
|
T164 |
11 |