Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26819

1

T1

24

T2

18

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22985

1

T2

18

T3

2

T4

239

auto[ADC_CTRL_FILTER_COND_OUT]

3834

1

T1

24

T3

1

T4

38

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20356

1

T1

11

T2

18

T3

1

auto[1]

6463

1

T1

13

T3

2

T4

38

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22590

1

T1

24

T2

18

T3

3

auto[1]

4229

1

T4

23

T5

30

T10

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	224	1			T62	3		T174	4		T239	15
values[0]	32	1			T269	14		T297	18		-	-
values[1]	688	1			T4	23		T11	27		T48	1
values[2]	721	1			T1	13		T220	22		T42	16
values[3]	881	1			T3	1		T4	15		T12	8
values[4]	3039	1			T5	19		T9	10		T12	23
values[5]	598	1			T10	5		T85	15		T46	11
values[6]	760	1			T5	17		T11	6		T48	1
values[7]	756	1			T1	11		T7	18		T60	33
values[8]	742	1			T5	20		T10	32		T59	12
values[9]	998	1			T3	2		T7	4		T10	2
minimum	17380	1			T2	18		T4	239		T6	163

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	542	1			T4	23		T11	27		T48	1
values[1]	914	1			T1	13		T3	1		T12	8
values[2]	758	1			T4	15		T55	12		T155	4
values[3]	2932	1			T5	19		T9	10		T12	23
values[4]	680	1			T10	5		T46	11		T174	13
values[5]	766	1			T5	17		T7	5		T11	6
values[6]	773	1			T1	11		T5	20		T7	13
values[7]	739	1			T3	1		T10	32		T60	23
values[8]	886	1			T3	1		T7	4		T10	2
values[9]	143	1			T159	1		T161	33		T33	29
minimum	17686	1			T2	18		T4	239		T6	163

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22552

1

T1

2

T2

18

T3

3

auto[1]

4267

1

T1

22

T4

13

T5

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	2		T160	13		T174	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T4	12		T48	1		T165	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T3	1		T220	11		T42	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T1	13		T12	4		T237	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T155	1		T166	1		T51	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T4	3		T55	5		T160	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1580	1			T9	10		T12	13		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	11		T85	1		T156	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T46	4		T164	1		T186	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T10	3		T174	13		T171	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	5		T11	1		T85	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T7	5		T48	1		T156	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T7	13		T154	1		T156	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T1	11		T5	10		T59	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T3	1		T10	22		T60	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T184	1		T154	2		T261	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T7	4		T62	17		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T3	1		T10	1		T62	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T101	12		T255	9		T298	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T159	1		T161	18		T33	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17308	1			T2	18		T4	239		T6	163
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T28	21		T110	11		T299	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T11	25		T49	1		T121	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T4	11		T165	17		T211	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T220	11		T268	4		T188	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T12	4		T237	9		T44	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T155	3		T166	8		T51	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T4	12		T55	7		T239	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	964	1			T12	10		T56	5		T59	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	8		T85	14		T156	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T46	7		T164	10		T186	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T10	2		T166	5		T251	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	12		T11	5		T85	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T156	12		T49	11		T262	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T156	14		T186	6		T286	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T5	10		T60	12		T162	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T10	10		T60	10		T151	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T161	8		T164	9		T47	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T62	2		T155	10		T238	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T10	1		T62	4		T151	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T101	16		T298	10		T300	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T161	15		T33	15		T14	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	2		T55	1		T85	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T28	14		T110	11		T295	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T62	3		T174	4		T101	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T239	8		T47	9		T186	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T269	14		T297	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T11	2		T160	13		T174	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T4	12		T48	1		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T220	11		T42	16		T268	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T1	13		T43	16		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T3	1		T155	1		T254	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T4	3		T12	4		T160	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1620	1			T9	10		T12	13		T56	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T5	11		T55	5		T156	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T46	4		T164	1		T50	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T10	3		T85	1		T174	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	5		T11	1		T85	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T48	1		T156	16		T43	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	13		T154	1		T156	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T1	11		T7	5		T60	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T10	22		T60	13		T98	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T5	10		T59	12		T184	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T3	1		T7	4		T62	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T3	1		T10	1		T62	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17230	1			T2	18		T4	239		T6	163
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T101	16		T301	9		T298	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T239	7		T47	2		T186	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T297	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T11	25		T49	1		T190	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T4	11		T165	17		T249	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T220	11		T268	4		T188	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T44	2		T211	1		T242	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T155	3		T254	10		T51	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T4	12		T12	4		T237	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T12	10		T56	5		T59	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T5	8		T55	7		T156	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T46	7		T164	10		T50	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T10	2		T85	14		T158	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	12		T11	5		T85	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T156	12		T49	11		T258	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T156	14		T251	12		T186	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T60	12		T162	12		T248	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T10	10		T60	10		T98	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T5	10		T161	8		T237	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T62	2		T151	7		T155	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T10	1		T62	4		T151	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	2		T55	1		T85	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T11	27		T160	1		T174	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T4	12		T48	1		T165	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T3	1		T220	12		T42	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T1	1		T12	8		T237	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T155	4		T166	9		T51	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T4	13		T55	8		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1303	1			T9	1		T12	14		T56	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T5	9		T85	15		T156	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T46	11		T164	11		T186	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T10	3		T174	1		T171	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	13		T11	6		T85	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T7	1		T48	1		T156	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	1		T154	1		T156	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T1	1		T5	11		T59	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	1		T10	11		T60	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T184	1		T154	2		T261	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T7	1		T62	4		T155	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T3	1		T10	2		T62	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T101	17		T255	1		T298	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T159	1		T161	16		T33	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17442	1			T2	18		T4	239		T6	163
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T28	15		T110	12		T299	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T160	12		T174	12		T100	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T4	11		T123	8		T249	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T220	10		T42	15		T268	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T1	12		T237	7		T43	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T51	5		T119	2		T279	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T4	2		T55	4		T160	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1241	1			T9	9		T12	9		T59	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T5	10		T156	2		T237	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T241	7		T54	1		T249	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T10	2		T174	12		T171	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T5	4		T85	14		T256	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T7	4		T156	15		T164	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T7	12		T156	13		T271	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T1	10		T5	9		T59	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T10	21		T60	12		T151	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T161	7		T164	4		T47	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	3		T62	15		T174	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T62	5		T151	14		T219	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T101	11		T255	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T161	17		T33	13		T208	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T43	9		T269	13		T207	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T28	20		T110	10		T295	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T62	1		T174	1		T101	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T239	8		T47	8		T186	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T269	1		T297	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	27		T160	1		T174	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T4	12		T48	1		T165	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T220	12		T42	1		T268	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T1	1		T43	1		T44	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T3	1		T155	4		T254	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T4	13		T12	8		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1339	1			T9	1		T12	14		T56	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T5	9		T55	8		T156	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T46	11		T164	11		T50	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T10	3		T85	15		T174	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T5	13		T11	6		T85	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T48	1		T156	13		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	1		T154	1		T156	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T1	1		T7	1		T60	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T10	11		T60	11		T98	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T5	11		T59	1		T184	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T3	1		T7	1		T62	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T3	1		T10	2		T62	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17380	1			T2	18		T4	239		T6	163
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T62	2		T174	3		T101	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T239	7		T47	3		T260	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T269	13		T297	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T160	12		T174	12		T43	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T4	11		T123	8		T249	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T220	10		T42	15		T268	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	12		T43	15		T270	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T254	13		T51	5		T119	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T4	2		T160	5		T237	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1271	1			T9	9		T12	9		T59	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	10		T55	4		T156	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T241	7		T249	7		T286	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T10	2		T174	12		T171	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T5	4		T85	14		T256	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T156	15		T43	13		T251	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T7	12		T156	13		T271	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T1	10		T7	4		T60	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T10	21		T60	12		T98	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T5	9		T59	11		T161	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T7	3		T62	13		T151	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T62	5		T151	14		T219	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22552

1

T1

2

T2

18

T3

3

auto[1]

auto[0]

4267

1

T1

22

T4

13

T5

23