Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26819

1

T1

24

T2

18

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20817

1

T1

13

T2

18

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

6002

1

T1

11

T4

15

T5

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20769

1

T2

18

T3

1

T4

277

auto[1]

6050

1

T1

24

T3

2

T5

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22590

1

T1

24

T2

18

T3

3

auto[1]

4229

1

T4

23

T5

30

T10

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	183	1			T3	1		T62	10		T156	28
values[0]	18	1			T257	15		T236	1		T19	1
values[1]	879	1			T3	1		T5	19		T12	23
values[2]	728	1			T60	2		T85	17		T155	11
values[3]	691	1			T11	6		T12	8		T155	4
values[4]	617	1			T1	11		T60	31		T151	46
values[5]	782	1			T1	13		T4	15		T5	17
values[6]	523	1			T48	1		T184	1		T154	2
values[7]	808	1			T3	1		T4	23		T10	32
values[8]	956	1			T5	20		T7	5		T55	12
values[9]	3254	1			T9	10		T11	10		T56	6
minimum	17380	1			T2	18		T4	239		T6	163

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	784	1			T3	1		T5	19		T12	23
values[1]	2946	1			T9	10		T12	8		T56	6
values[2]	721	1			T11	6		T151	31		T46	11
values[3]	637	1			T1	11		T4	15		T48	1
values[4]	759	1			T1	13		T5	17		T7	17
values[5]	444	1			T48	1		T154	1		T164	11
values[6]	1027	1			T3	1		T4	23		T7	5
values[7]	776	1			T59	12		T238	20		T47	11
values[8]	961	1			T5	20		T11	10		T60	23
values[9]	128	1			T3	1		T62	10		T174	4
minimum	17636	1			T2	18		T4	239		T6	163

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22552

1

T1

2

T2

18

T3

3

auto[1]

4267

1

T1

22

T4

13

T5

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	1		T5	11		T62	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T12	13		T154	1		T164	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T60	1		T85	15		T47	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1591	1			T9	10		T12	4		T56	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T151	15		T46	4		T237	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	1		T171	14		T188	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T60	20		T151	8		T160	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T1	11		T4	3		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	13		T5	5		T10	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T7	17		T156	3		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T154	1		T172	1		T44	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T48	1		T164	1		T32	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T3	1		T4	12		T10	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T7	5		T85	1		T161	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T238	11		T240	8		T268	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T59	6		T47	9		T242	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T62	3		T156	14		T172	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T5	10		T11	1		T60	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T3	1		T174	4		T49	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T62	6		T255	9		T246	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17343	1			T2	18		T4	239		T6	163
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T101	12		T303	12		T304	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T5	8		T62	2		T117	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	10		T164	9		T39	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T60	1		T85	2		T47	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	954	1			T12	4		T56	5		T61	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T151	16		T46	7		T237	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T11	5		T188	14		T186	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T60	11		T151	7		T220	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T4	12		T44	9		T169	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T5	12		T10	3		T238	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T156	6		T161	15		T237	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T44	2		T27	2		T110	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T164	10		T32	12		T251	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T4	11		T10	10		T11	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T85	14		T161	11		T158	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T238	9		T240	7		T268	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T59	6		T47	2		T242	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T156	14		T49	11		T118	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T5	10		T11	9		T60	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T49	1		T305	2		T200	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T62	4		T246	12		T209	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	2		T55	1		T85	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T101	16		T303	11		T304	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T3	1		T156	14		T174	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T62	6		T121	1		T54	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T257	15		T19	1		T247	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T236	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T3	1		T5	11		T62	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T12	13		T154	1		T39	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T60	1		T85	15		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T155	1		T164	5		T239	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T46	4		T237	3		T239	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	1		T12	4		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T60	20		T151	23		T220	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T1	11		T174	13		T163	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	13		T5	5		T10	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T4	3		T7	17		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T184	1		T154	2		T160	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T48	1		T161	18		T237	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T3	1		T4	12		T10	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T85	1		T158	1		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T55	5		T238	11		T166	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	10		T7	5		T59	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T62	3		T240	8		T172	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1703	1			T9	10		T11	1		T56	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17230	1			T2	18		T4	239		T6	163
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T156	14		T49	1		T63	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T62	4		T54	1		T246	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	8		T62	2		T161	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	10		T39	12		T169	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T60	1		T85	2		T165	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T155	10		T164	9		T239	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T46	7		T237	9		T239	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T11	5		T12	4		T155	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T60	11		T151	23		T220	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T169	8		T186	6		T249	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	12		T10	3		T237	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T4	12		T156	6		T44	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T238	4		T44	2		T27	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T161	15		T237	9		T164	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T4	11		T10	10		T11	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T85	14		T158	12		T162	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T55	7		T238	9		T166	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T5	10		T59	6		T161	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T240	7		T49	11		T118	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1118	1			T11	9		T56	5		T60	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	2		T55	1		T85	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	1		T5	9		T62	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T12	14		T154	1		T164	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T60	2		T85	3		T47	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1293	1			T9	1		T12	8		T56	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T151	17		T46	11		T237	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	6		T171	1		T188	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T60	12		T151	8		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T1	1		T4	13		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T1	1		T5	13		T10	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T7	2		T156	7		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T154	1		T172	1		T44	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T48	1		T164	11		T32	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T3	1		T4	12		T10	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T7	1		T85	15		T161	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T238	10		T240	8		T268	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T59	7		T47	8		T242	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T62	1		T156	15		T172	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T5	11		T11	10		T60	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T3	1		T174	1		T49	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T62	5		T255	1		T246	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17448	1			T2	18		T4	239		T6	163
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T101	17		T303	12		T304	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T5	10		T62	13		T43	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T12	9		T164	4		T39	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T85	14		T47	2		T256	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1252	1			T9	9		T153	4		T250	38
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T151	14		T237	2		T42	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T171	13		T188	14		T216	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T60	19		T151	7		T160	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T1	10		T4	2		T174	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T1	12		T5	4		T10	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T7	15		T156	2		T161	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T27	2		T252	14		T253	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T32	15		T251	3		T211	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T4	11		T10	21		T55	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T7	4		T161	8		T42	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T238	10		T240	7		T268	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T59	5		T47	3		T242	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T62	2		T156	13		T242	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	9		T60	12		T156	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T174	3		T305	13		T306	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T62	5		T255	8		T246	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T161	7		T251	15		T283	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T101	11		T303	11		T199	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T3	1		T156	15		T174	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T62	5		T121	1		T54	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T257	1		T19	1		T247	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T236	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T3	1		T5	9		T62	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T12	14		T154	1		T39	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T60	2		T85	3		T165	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T155	11		T164	10		T239	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T46	11		T237	10		T239	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	6		T12	8		T155	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T60	12		T151	25		T220	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T1	1		T174	1		T163	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	1		T5	13		T10	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T4	13		T7	2		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T184	1		T154	2		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T48	1		T161	16		T237	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	1		T4	12		T10	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T85	15		T158	13		T162	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T55	8		T238	10		T166	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T5	11		T7	1		T59	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T62	1		T240	8		T172	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1477	1			T9	1		T11	10		T56	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17380	1			T2	18		T4	239		T6	163
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T156	13		T174	3		T63	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T62	5		T54	1		T255	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T257	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T5	10		T62	13		T161	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T12	9		T39	10		T43	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T85	14		T256	12		T51	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T164	4		T239	7		T171	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T237	2		T47	2		T251	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T164	11		T171	13		T188	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T60	19		T151	21		T220	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T1	10		T174	12		T43	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T1	12		T5	4		T10	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T4	2		T7	15		T156	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T160	12		T238	4		T167	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T161	17		T237	7		T32	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T4	11		T10	21		T219	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T42	15		T254	13		T211	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T55	4		T238	10		T166	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	9		T7	4		T59	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T62	2		T240	7		T242	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1344	1			T9	9		T60	12		T153	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22552

1

T1

2

T2

18

T3

3

auto[1]

auto[0]

4267

1

T1

22

T4

13

T5

23