Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26819

1

T1

24

T2

18

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22801

1

T1

13

T2

18

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

4018

1

T1

11

T3

2

T4

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20569

1

T1

24

T2

18

T3

2

auto[1]

6250

1

T3

1

T4

15

T7

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22590

1

T1

24

T2

18

T3

3

auto[1]

4229

1

T4

23

T5

30

T10

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	68	1			T242	6		T249	15		T307	1
values[0]	67	1			T155	4		T118	16		T110	24
values[1]	761	1			T1	11		T4	38		T7	13
values[2]	2956	1			T9	10		T56	6		T61	19
values[3]	614	1			T5	19		T7	5		T48	1
values[4]	651	1			T12	23		T62	19		T154	1
values[5]	758	1			T3	1		T10	32		T12	8
values[6]	717	1			T3	1		T155	11		T156	28
values[7]	696	1			T5	17		T7	4		T10	2
values[8]	639	1			T1	13		T3	1		T11	10
values[9]	1512	1			T5	20		T10	5		T62	10
minimum	17380	1			T2	18		T4	239		T6	163

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	992	1			T1	11		T4	38		T7	13
values[1]	2917	1			T9	10		T56	6		T59	12
values[2]	631	1			T5	19		T7	5		T12	23
values[3]	709	1			T3	1		T10	32		T12	8
values[4]	695	1			T60	31		T160	6		T220	22
values[5]	851	1			T3	1		T5	17		T7	4
values[6]	591	1			T3	1		T10	2		T48	1
values[7]	741	1			T1	13		T10	5		T11	10
values[8]	1021	1			T5	20		T62	10		T154	1
values[9]	277	1			T85	17		T46	11		T174	4
minimum	17394	1			T2	18		T4	239		T6	163

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22552

1

T1

2

T2

18

T3

3

auto[1]

4267

1

T1

22

T4

13

T5

23

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T4	3		T155	1		T162	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T1	11		T4	12		T7	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1548	1			T9	10		T56	1		T59	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T261	1		T237	8		T39	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T7	5		T12	13		T160	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T5	11		T48	1		T154	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T3	1		T12	4		T151	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T10	22		T60	13		T62	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T160	6		T47	4		T43	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T60	20		T220	11		T166	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T7	4		T11	1		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T3	1		T5	5		T85	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T48	1		T59	6		T60	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	1		T10	1		T184	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	13		T55	5		T171	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T10	3		T11	1		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T5	10		T62	6		T156	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T154	1		T47	9		T240	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T46	4		T174	4		T32	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T85	15		T238	11		T15	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17230	1			T2	18		T4	239		T6	163
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T290	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T4	12		T155	3		T162	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T4	11		T11	16		T239	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	933	1			T56	5		T61	17		T182	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T237	9		T39	12		T44	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T12	10		T164	19		T239	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T5	8		T237	9		T166	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T12	4		T151	16		T156	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	10		T60	10		T62	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T47	2		T51	5		T242	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T60	11		T220	11		T166	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	5		T155	10		T156	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T5	12		T85	14		T170	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T59	6		T60	1		T188	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T10	1		T151	7		T237	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T55	7		T169	9		T186	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T10	2		T11	9		T163	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T5	10		T62	4		T156	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T47	2		T240	7		T32	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T46	7		T49	1		T251	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T85	2		T238	9		T15	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	2		T55	1		T85	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T290	5		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T307	1		T272	14		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T242	1		T249	8		T308	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T155	1		T110	11		T206	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T118	1		T110	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T4	3		T162	1		T171	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T1	11		T4	12		T7	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1526	1			T9	10		T56	1		T61	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T154	1		T261	1		T237	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	5		T59	12		T174	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T5	11		T48	1		T186	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	13		T156	14		T160	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T62	17		T154	1		T219	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T3	1		T12	4		T151	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T10	22		T60	33		T220	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T155	1		T156	16		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	1		T166	16		T172	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T7	4		T11	1		T59	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T5	5		T10	1		T85	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	13		T48	1		T55	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T3	1		T11	1		T171	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	426	1			T5	10		T62	6		T156	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T10	3		T85	15		T154	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17230	1			T2	18		T4	239		T6	163
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T242	5		T249	7		T308	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T155	3		T110	11		T206	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T118	15		T110	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T4	12		T162	12		T49	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T4	11		T11	16		T239	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	927	1			T56	5		T61	17		T182	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T237	9		T39	12		T44	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T164	19		T239	7		T166	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	8		T186	16		T211	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T12	10		T156	14		T169	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T62	2		T237	9		T166	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T12	4		T151	16		T47	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T10	10		T60	21		T220	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T155	10		T156	12		T158	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T166	11		T188	12		T245	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T11	5		T59	6		T60	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T5	12		T10	1		T85	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T55	7		T256	13		T186	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T11	9		T119	3		T101	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	452	1			T5	10		T62	4		T156	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T10	2		T85	2		T163	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	2		T55	1		T85	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T4	13		T155	4		T162	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	357	1			T1	1		T4	12		T7	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T9	1		T56	6		T59	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T261	1		T237	10		T39	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T7	1		T12	14		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T5	9		T48	1		T154	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T3	1		T12	8		T151	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T10	11		T60	11		T62	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T160	1		T47	4		T43	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T60	12		T220	12		T166	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T7	1		T11	6		T155	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T3	1		T5	13		T85	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T48	1		T59	7		T60	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	1		T10	2		T184	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	1		T55	8		T171	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T10	3		T11	10		T163	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	356	1			T5	11		T62	5		T156	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T154	1		T47	8		T240	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T46	11		T174	1		T32	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T85	3		T238	10		T15	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17380	1			T2	18		T4	239		T6	163
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T290	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T4	2		T171	13		T43	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T1	10		T4	11		T7	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1215	1			T9	9		T59	11		T153	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T237	7		T39	10		T119	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T7	4		T12	9		T160	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T5	10		T237	2		T189	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T151	14		T156	13		T157	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	21		T60	12		T62	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T160	5		T47	2		T43	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T60	19		T220	10		T166	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	3		T156	15		T42	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	4		T305	13		T176	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T59	5		T188	14		T256	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T151	7		T237	11		T188	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T1	12		T55	4		T171	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	2		T171	11		T119	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T5	9		T62	5		T156	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T47	3		T240	7		T32	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T174	3		T251	14		T221	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T85	14		T238	10		T15	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T290	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T307	1		T272	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T242	6		T249	8		T308	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T155	4		T110	12		T206	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T118	16		T110	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T4	13		T162	13		T171	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T1	1		T4	12		T7	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1257	1			T9	1		T56	6		T61	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T154	1		T261	1		T237	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T7	1		T59	1		T174	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T5	9		T48	1		T186	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T12	14		T156	15		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T62	4		T154	1		T219	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	1		T12	8		T151	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T10	11		T60	23		T220	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T155	11		T156	13		T158	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	1		T166	12		T172	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T7	1		T11	6		T59	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T5	13		T10	2		T85	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T1	1		T48	1		T55	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T3	1		T11	10		T171	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	537	1			T5	11		T62	5		T156	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T10	3		T85	3		T154	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17380	1			T2	18		T4	239		T6	163
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T272	13		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T249	7		T308	17		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T110	10		T206	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T4	2		T171	13		T43	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	10		T4	11		T7	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1196	1			T9	9		T153	4		T250	38
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T237	7		T39	10		T119	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	4		T59	11		T174	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T5	10		T309	2		T110	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T12	9		T156	13		T160	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T62	15		T219	14		T237	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T151	14		T160	5		T47	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	21		T60	31		T220	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T156	15		T42	14		T43	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T166	15		T188	11		T206	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T7	3		T59	5		T188	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T5	4		T151	7		T237	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T1	12		T55	4		T171	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T171	11		T119	3		T100	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	341	1			T5	9		T62	5		T156	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T10	2		T85	14		T238	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22552

1

T1

2

T2

18

T3

3

auto[1]

auto[0]

4267

1

T1

22

T4

13

T5

23