Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.75 99.07 96.62 100.00 100.00 98.83 98.33 91.42


Total test records in report: 920
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T76 /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.364775560 Jun 25 05:56:26 PM PDT 24 Jun 25 05:58:34 PM PDT 24 56699915270 ps
T332 /workspace/coverage/default/6.adc_ctrl_clock_gating.59646285 Jun 25 05:52:09 PM PDT 24 Jun 25 05:53:18 PM PDT 24 213724721566 ps
T272 /workspace/coverage/default/2.adc_ctrl_filters_wakeup.40799663 Jun 25 05:51:50 PM PDT 24 Jun 25 05:54:16 PM PDT 24 535206138300 ps
T288 /workspace/coverage/default/27.adc_ctrl_clock_gating.2110061817 Jun 25 05:53:56 PM PDT 24 Jun 25 06:00:18 PM PDT 24 367628322564 ps
T794 /workspace/coverage/default/19.adc_ctrl_filters_polled.577189814 Jun 25 05:52:48 PM PDT 24 Jun 25 06:11:58 PM PDT 24 487751412030 ps
T146 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2940277639 Jun 25 05:51:35 PM PDT 24 Jun 25 05:51:37 PM PDT 24 492857731 ps
T77 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2682546214 Jun 25 05:51:26 PM PDT 24 Jun 25 05:51:30 PM PDT 24 534634692 ps
T78 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.415263105 Jun 25 05:51:25 PM PDT 24 Jun 25 05:51:31 PM PDT 24 609236372 ps
T795 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.4204340114 Jun 25 05:51:38 PM PDT 24 Jun 25 05:51:40 PM PDT 24 450424671 ps
T796 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1852262545 Jun 25 05:51:41 PM PDT 24 Jun 25 05:51:44 PM PDT 24 355947331 ps
T88 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3691887257 Jun 25 05:51:42 PM PDT 24 Jun 25 05:51:45 PM PDT 24 323293055 ps
T84 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2942512266 Jun 25 05:51:27 PM PDT 24 Jun 25 05:51:31 PM PDT 24 443677839 ps
T130 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.770750041 Jun 25 05:51:26 PM PDT 24 Jun 25 05:51:33 PM PDT 24 1162745646 ps
T131 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.184767779 Jun 25 05:51:28 PM PDT 24 Jun 25 05:51:31 PM PDT 24 350937550 ps
T73 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.163713684 Jun 25 05:51:45 PM PDT 24 Jun 25 05:51:53 PM PDT 24 9183765632 ps
T797 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2670968644 Jun 25 05:51:42 PM PDT 24 Jun 25 05:51:44 PM PDT 24 448716394 ps
T798 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.247578343 Jun 25 05:51:37 PM PDT 24 Jun 25 05:51:40 PM PDT 24 561982868 ps
T92 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1243306479 Jun 25 05:51:42 PM PDT 24 Jun 25 05:51:44 PM PDT 24 495906322 ps
T74 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1062099117 Jun 25 05:51:24 PM PDT 24 Jun 25 05:51:48 PM PDT 24 8461645426 ps
T70 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2562129774 Jun 25 05:51:37 PM PDT 24 Jun 25 05:51:41 PM PDT 24 4585182922 ps
T71 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3480998011 Jun 25 05:51:23 PM PDT 24 Jun 25 05:51:35 PM PDT 24 27016414353 ps
T75 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2297224100 Jun 25 05:51:25 PM PDT 24 Jun 25 05:51:39 PM PDT 24 8174022241 ps
T91 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.4188928058 Jun 25 05:51:44 PM PDT 24 Jun 25 05:51:56 PM PDT 24 4171493028 ps
T72 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3679741634 Jun 25 05:51:34 PM PDT 24 Jun 25 05:51:52 PM PDT 24 4426729639 ps
T89 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2625990990 Jun 25 05:51:28 PM PDT 24 Jun 25 05:51:52 PM PDT 24 8338279873 ps
T132 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2626350214 Jun 25 05:51:28 PM PDT 24 Jun 25 05:51:32 PM PDT 24 1250580382 ps
T799 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1114369947 Jun 25 05:51:50 PM PDT 24 Jun 25 05:51:53 PM PDT 24 476046657 ps
T800 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3339908085 Jun 25 05:51:50 PM PDT 24 Jun 25 05:51:53 PM PDT 24 476656702 ps
T801 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.4200600237 Jun 25 05:51:25 PM PDT 24 Jun 25 05:51:27 PM PDT 24 437730273 ps
T133 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3746182863 Jun 25 05:51:19 PM PDT 24 Jun 25 05:53:01 PM PDT 24 25322987356 ps
T802 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1068971043 Jun 25 05:51:51 PM PDT 24 Jun 25 05:51:53 PM PDT 24 390357050 ps
T134 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.509521484 Jun 25 05:51:42 PM PDT 24 Jun 25 05:51:44 PM PDT 24 506092792 ps
T82 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1262913397 Jun 25 05:51:27 PM PDT 24 Jun 25 05:51:31 PM PDT 24 378218912 ps
T803 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.283025853 Jun 25 05:51:23 PM PDT 24 Jun 25 05:51:27 PM PDT 24 442437433 ps
T804 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2677511319 Jun 25 05:51:33 PM PDT 24 Jun 25 05:51:36 PM PDT 24 411680939 ps
T805 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2358165069 Jun 25 05:51:26 PM PDT 24 Jun 25 05:51:29 PM PDT 24 532419158 ps
T806 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2687180296 Jun 25 05:51:42 PM PDT 24 Jun 25 05:51:44 PM PDT 24 450271562 ps
T807 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1957036335 Jun 25 05:51:28 PM PDT 24 Jun 25 05:51:31 PM PDT 24 342734678 ps
T808 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.271074649 Jun 25 05:51:24 PM PDT 24 Jun 25 05:51:27 PM PDT 24 371972488 ps
T83 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3598061242 Jun 25 05:51:33 PM PDT 24 Jun 25 05:51:38 PM PDT 24 422479468 ps
T809 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1593745310 Jun 25 05:51:24 PM PDT 24 Jun 25 05:51:26 PM PDT 24 593995045 ps
T810 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3940140635 Jun 25 05:51:33 PM PDT 24 Jun 25 05:51:37 PM PDT 24 562246040 ps
T342 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1479334359 Jun 25 05:51:27 PM PDT 24 Jun 25 05:51:52 PM PDT 24 8533327999 ps
T811 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.572799840 Jun 25 05:51:24 PM PDT 24 Jun 25 05:51:27 PM PDT 24 344726077 ps
T90 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2750009619 Jun 25 05:51:27 PM PDT 24 Jun 25 05:51:32 PM PDT 24 620922742 ps
T812 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3286164699 Jun 25 05:51:46 PM PDT 24 Jun 25 05:51:49 PM PDT 24 290383323 ps
T135 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.67998375 Jun 25 05:51:42 PM PDT 24 Jun 25 05:51:45 PM PDT 24 428166153 ps
T813 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3238798625 Jun 25 05:51:53 PM PDT 24 Jun 25 05:51:57 PM PDT 24 505075511 ps
T814 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1978009341 Jun 25 05:51:24 PM PDT 24 Jun 25 05:51:27 PM PDT 24 404989167 ps
T815 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.83323621 Jun 25 05:51:17 PM PDT 24 Jun 25 05:51:19 PM PDT 24 386226410 ps
T816 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3134489666 Jun 25 05:51:19 PM PDT 24 Jun 25 05:51:26 PM PDT 24 1271598437 ps
T817 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2931778473 Jun 25 05:51:19 PM PDT 24 Jun 25 05:51:22 PM PDT 24 323901043 ps
T818 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1212784269 Jun 25 05:51:53 PM PDT 24 Jun 25 05:51:56 PM PDT 24 457571585 ps
T819 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1693954049 Jun 25 05:51:35 PM PDT 24 Jun 25 05:51:38 PM PDT 24 316637591 ps
T820 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.669753472 Jun 25 05:51:33 PM PDT 24 Jun 25 05:51:40 PM PDT 24 4132161332 ps
T821 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3835139670 Jun 25 05:51:40 PM PDT 24 Jun 25 05:51:47 PM PDT 24 4036051996 ps
T147 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1089234935 Jun 25 05:51:48 PM PDT 24 Jun 25 05:51:55 PM PDT 24 2464872066 ps
T822 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3204968042 Jun 25 05:51:20 PM PDT 24 Jun 25 05:51:23 PM PDT 24 607995116 ps
T823 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2179816577 Jun 25 05:51:25 PM PDT 24 Jun 25 05:51:28 PM PDT 24 388922824 ps
T824 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.4024258573 Jun 25 05:51:25 PM PDT 24 Jun 25 05:51:29 PM PDT 24 473855853 ps
T148 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1904833814 Jun 25 05:51:37 PM PDT 24 Jun 25 05:51:42 PM PDT 24 1878029322 ps
T825 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3928109657 Jun 25 05:51:34 PM PDT 24 Jun 25 05:51:38 PM PDT 24 456715741 ps
T136 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.4274701845 Jun 25 05:51:26 PM PDT 24 Jun 25 05:51:29 PM PDT 24 1059642221 ps
T826 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.673852667 Jun 25 05:51:40 PM PDT 24 Jun 25 05:51:43 PM PDT 24 659048611 ps
T149 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1142691708 Jun 25 05:51:26 PM PDT 24 Jun 25 05:51:31 PM PDT 24 2078610609 ps
T827 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1025052086 Jun 25 05:51:42 PM PDT 24 Jun 25 05:51:44 PM PDT 24 511690502 ps
T150 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.760734337 Jun 25 05:51:19 PM PDT 24 Jun 25 05:51:24 PM PDT 24 4795317442 ps
T137 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3697250770 Jun 25 05:51:31 PM PDT 24 Jun 25 05:51:33 PM PDT 24 539716398 ps
T828 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.4231080535 Jun 25 05:51:35 PM PDT 24 Jun 25 05:51:41 PM PDT 24 4456021770 ps
T138 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3069874355 Jun 25 05:51:24 PM PDT 24 Jun 25 05:51:26 PM PDT 24 533535854 ps
T829 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3104561598 Jun 25 05:51:41 PM PDT 24 Jun 25 05:51:44 PM PDT 24 378093829 ps
T830 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3747232506 Jun 25 05:51:19 PM PDT 24 Jun 25 05:51:28 PM PDT 24 8625558830 ps
T831 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3303865167 Jun 25 05:51:53 PM PDT 24 Jun 25 05:51:56 PM PDT 24 554975632 ps
T832 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1131599841 Jun 25 05:51:40 PM PDT 24 Jun 25 05:51:44 PM PDT 24 1242693081 ps
T833 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.196842146 Jun 25 05:51:24 PM PDT 24 Jun 25 05:51:29 PM PDT 24 640865505 ps
T834 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1177191717 Jun 25 05:51:28 PM PDT 24 Jun 25 05:51:31 PM PDT 24 333865177 ps
T139 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1483579993 Jun 25 05:51:23 PM PDT 24 Jun 25 05:51:30 PM PDT 24 1309460305 ps
T835 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.906242589 Jun 25 05:51:34 PM PDT 24 Jun 25 05:51:37 PM PDT 24 448845642 ps
T836 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1802279974 Jun 25 05:51:42 PM PDT 24 Jun 25 05:51:45 PM PDT 24 594887133 ps
T837 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1573104807 Jun 25 05:51:33 PM PDT 24 Jun 25 05:51:35 PM PDT 24 445590778 ps
T838 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1019050431 Jun 25 05:51:35 PM PDT 24 Jun 25 05:51:39 PM PDT 24 472955598 ps
T839 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3318217679 Jun 25 05:51:35 PM PDT 24 Jun 25 05:51:37 PM PDT 24 373019875 ps
T840 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3826812870 Jun 25 05:51:23 PM PDT 24 Jun 25 05:51:29 PM PDT 24 5396840188 ps
T841 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.879120636 Jun 25 05:51:42 PM PDT 24 Jun 25 05:51:49 PM PDT 24 4170831271 ps
T140 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3301329485 Jun 25 05:51:24 PM PDT 24 Jun 25 05:51:26 PM PDT 24 924293066 ps
T842 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1497591484 Jun 25 05:51:52 PM PDT 24 Jun 25 05:51:56 PM PDT 24 495969849 ps
T843 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1512541000 Jun 25 05:51:41 PM PDT 24 Jun 25 05:51:43 PM PDT 24 530731783 ps
T844 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2591150446 Jun 25 05:51:18 PM PDT 24 Jun 25 05:51:24 PM PDT 24 459590930 ps
T845 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3979626570 Jun 25 05:51:41 PM PDT 24 Jun 25 05:51:44 PM PDT 24 403967715 ps
T846 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1772201265 Jun 25 05:51:31 PM PDT 24 Jun 25 05:51:54 PM PDT 24 8621737273 ps
T847 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3688276647 Jun 25 05:51:36 PM PDT 24 Jun 25 05:51:45 PM PDT 24 8794245439 ps
T848 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.261893232 Jun 25 05:51:53 PM PDT 24 Jun 25 05:51:58 PM PDT 24 2854113547 ps
T849 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1295492087 Jun 25 05:51:19 PM PDT 24 Jun 25 05:51:22 PM PDT 24 735647589 ps
T850 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.165686768 Jun 25 05:51:45 PM PDT 24 Jun 25 05:51:46 PM PDT 24 442212168 ps
T143 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1517379290 Jun 25 05:51:27 PM PDT 24 Jun 25 05:51:29 PM PDT 24 412223629 ps
T851 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2076108542 Jun 25 05:51:40 PM PDT 24 Jun 25 05:51:43 PM PDT 24 348256599 ps
T852 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3180497733 Jun 25 05:51:36 PM PDT 24 Jun 25 05:51:39 PM PDT 24 514159835 ps
T853 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2549378540 Jun 25 05:51:52 PM PDT 24 Jun 25 05:51:56 PM PDT 24 451836065 ps
T854 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.145719418 Jun 25 05:51:41 PM PDT 24 Jun 25 05:51:43 PM PDT 24 443501862 ps
T855 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1780492100 Jun 25 05:51:35 PM PDT 24 Jun 25 05:51:38 PM PDT 24 614298558 ps
T141 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1203175661 Jun 25 05:51:26 PM PDT 24 Jun 25 05:51:29 PM PDT 24 852169714 ps
T856 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3301057278 Jun 25 05:51:36 PM PDT 24 Jun 25 05:51:42 PM PDT 24 2534677394 ps
T142 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1190495034 Jun 25 05:51:36 PM PDT 24 Jun 25 05:51:40 PM PDT 24 425295761 ps
T857 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1005398065 Jun 25 05:51:51 PM PDT 24 Jun 25 05:52:03 PM PDT 24 4159558335 ps
T858 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1513616809 Jun 25 05:51:46 PM PDT 24 Jun 25 05:51:48 PM PDT 24 349138896 ps
T859 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1242069376 Jun 25 05:51:35 PM PDT 24 Jun 25 05:51:38 PM PDT 24 594878770 ps
T860 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2785876884 Jun 25 05:51:50 PM PDT 24 Jun 25 05:51:53 PM PDT 24 316258347 ps
T861 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2347459357 Jun 25 05:51:33 PM PDT 24 Jun 25 05:51:35 PM PDT 24 524797380 ps
T862 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.4124369178 Jun 25 05:51:51 PM PDT 24 Jun 25 05:51:54 PM PDT 24 467305491 ps
T863 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3413682573 Jun 25 05:51:28 PM PDT 24 Jun 25 05:51:32 PM PDT 24 406614424 ps
T864 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1941928722 Jun 25 05:51:25 PM PDT 24 Jun 25 05:51:28 PM PDT 24 408857353 ps
T865 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.4279885004 Jun 25 05:51:46 PM PDT 24 Jun 25 05:51:54 PM PDT 24 8231165354 ps
T866 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2919738446 Jun 25 05:51:34 PM PDT 24 Jun 25 05:51:38 PM PDT 24 767326901 ps
T343 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.842835875 Jun 25 05:51:26 PM PDT 24 Jun 25 05:51:33 PM PDT 24 8788388965 ps
T867 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3821485327 Jun 25 05:51:51 PM PDT 24 Jun 25 05:51:55 PM PDT 24 396048448 ps
T868 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2041319680 Jun 25 05:51:36 PM PDT 24 Jun 25 05:51:39 PM PDT 24 393713176 ps
T144 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1148311618 Jun 25 05:51:24 PM PDT 24 Jun 25 05:51:28 PM PDT 24 1116568367 ps
T869 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.848728560 Jun 25 05:51:30 PM PDT 24 Jun 25 05:51:33 PM PDT 24 445323856 ps
T870 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2163220057 Jun 25 05:51:49 PM PDT 24 Jun 25 05:51:51 PM PDT 24 451023117 ps
T871 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2720055281 Jun 25 05:51:52 PM PDT 24 Jun 25 05:51:55 PM PDT 24 430643544 ps
T872 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3549760102 Jun 25 05:51:50 PM PDT 24 Jun 25 05:51:52 PM PDT 24 358906504 ps
T873 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.69508540 Jun 25 05:51:46 PM PDT 24 Jun 25 05:51:49 PM PDT 24 523390934 ps
T874 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.651916478 Jun 25 05:51:35 PM PDT 24 Jun 25 05:51:38 PM PDT 24 380432397 ps
T875 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3279517136 Jun 25 05:51:37 PM PDT 24 Jun 25 05:51:40 PM PDT 24 538235119 ps
T876 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3321129019 Jun 25 05:51:36 PM PDT 24 Jun 25 05:51:48 PM PDT 24 4490751351 ps
T877 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1645890022 Jun 25 05:51:38 PM PDT 24 Jun 25 05:52:01 PM PDT 24 8222699260 ps
T145 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1476484904 Jun 25 05:51:34 PM PDT 24 Jun 25 05:51:37 PM PDT 24 621801541 ps
T878 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2197021635 Jun 25 05:51:51 PM PDT 24 Jun 25 05:51:54 PM PDT 24 413228563 ps
T879 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2209959270 Jun 25 05:51:42 PM PDT 24 Jun 25 05:51:44 PM PDT 24 400329419 ps
T880 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3418744934 Jun 25 05:51:36 PM PDT 24 Jun 25 05:51:46 PM PDT 24 2397296727 ps
T881 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1967995432 Jun 25 05:51:35 PM PDT 24 Jun 25 05:51:39 PM PDT 24 617269763 ps
T882 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1583912003 Jun 25 05:51:34 PM PDT 24 Jun 25 05:51:37 PM PDT 24 297144748 ps
T883 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3519718371 Jun 25 05:51:28 PM PDT 24 Jun 25 05:51:34 PM PDT 24 4748628951 ps
T884 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3812229294 Jun 25 05:51:25 PM PDT 24 Jun 25 05:51:28 PM PDT 24 512157858 ps
T885 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2001449064 Jun 25 05:51:26 PM PDT 24 Jun 25 05:51:35 PM PDT 24 4375931674 ps
T886 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2711803320 Jun 25 05:51:54 PM PDT 24 Jun 25 05:51:57 PM PDT 24 465607357 ps
T887 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.337656050 Jun 25 05:51:34 PM PDT 24 Jun 25 05:51:37 PM PDT 24 443874479 ps
T888 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.495346487 Jun 25 05:51:40 PM PDT 24 Jun 25 05:51:42 PM PDT 24 459009734 ps
T889 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.606562125 Jun 25 05:51:37 PM PDT 24 Jun 25 05:51:47 PM PDT 24 4202663266 ps
T890 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1102703840 Jun 25 05:51:33 PM PDT 24 Jun 25 05:51:36 PM PDT 24 508009483 ps
T891 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1721045268 Jun 25 05:51:46 PM PDT 24 Jun 25 05:51:49 PM PDT 24 469556713 ps
T892 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.4261098126 Jun 25 05:51:52 PM PDT 24 Jun 25 05:51:55 PM PDT 24 363496553 ps
T893 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2336239479 Jun 25 05:51:33 PM PDT 24 Jun 25 05:51:35 PM PDT 24 465110945 ps
T894 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2643759435 Jun 25 05:51:23 PM PDT 24 Jun 25 05:51:28 PM PDT 24 481901757 ps
T895 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2115553263 Jun 25 05:51:49 PM PDT 24 Jun 25 05:51:51 PM PDT 24 454933445 ps
T896 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3258001369 Jun 25 05:51:26 PM PDT 24 Jun 25 05:51:39 PM PDT 24 4844953329 ps
T897 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3363318868 Jun 25 05:51:28 PM PDT 24 Jun 25 05:51:35 PM PDT 24 2407629516 ps
T898 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1455373487 Jun 25 05:51:37 PM PDT 24 Jun 25 05:51:41 PM PDT 24 594866337 ps
T899 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.14779873 Jun 25 05:51:42 PM PDT 24 Jun 25 05:51:45 PM PDT 24 455984105 ps
T900 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2421787477 Jun 25 05:51:33 PM PDT 24 Jun 25 05:51:35 PM PDT 24 558563331 ps
T901 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2497917455 Jun 25 05:51:24 PM PDT 24 Jun 25 05:51:27 PM PDT 24 335989914 ps
T902 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2471067003 Jun 25 05:51:31 PM PDT 24 Jun 25 05:51:36 PM PDT 24 2065669213 ps
T903 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2301316486 Jun 25 05:51:35 PM PDT 24 Jun 25 05:51:59 PM PDT 24 8631979466 ps
T904 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1524475085 Jun 25 05:51:27 PM PDT 24 Jun 25 05:51:49 PM PDT 24 5389751503 ps
T905 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1129843513 Jun 25 05:51:41 PM PDT 24 Jun 25 05:51:43 PM PDT 24 326842670 ps
T906 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1631506323 Jun 25 05:51:50 PM PDT 24 Jun 25 05:51:53 PM PDT 24 438204984 ps
T907 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3350549243 Jun 25 05:51:43 PM PDT 24 Jun 25 05:51:46 PM PDT 24 420366160 ps
T908 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1758699365 Jun 25 05:51:42 PM PDT 24 Jun 25 05:51:44 PM PDT 24 425885622 ps
T909 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.552958198 Jun 25 05:51:42 PM PDT 24 Jun 25 05:51:44 PM PDT 24 389777716 ps
T910 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.292716198 Jun 25 05:51:34 PM PDT 24 Jun 25 05:51:47 PM PDT 24 4448856868 ps
T911 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3765000122 Jun 25 05:51:25 PM PDT 24 Jun 25 05:53:00 PM PDT 24 23239731365 ps
T912 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.352349839 Jun 25 05:51:24 PM PDT 24 Jun 25 05:51:37 PM PDT 24 4275335959 ps
T913 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1469955312 Jun 25 05:51:18 PM PDT 24 Jun 25 05:51:21 PM PDT 24 543258607 ps
T914 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1828433817 Jun 25 05:51:24 PM PDT 24 Jun 25 05:51:31 PM PDT 24 1025664988 ps
T915 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3447182147 Jun 25 05:51:28 PM PDT 24 Jun 25 05:51:30 PM PDT 24 484567069 ps
T916 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3825038080 Jun 25 05:51:34 PM PDT 24 Jun 25 05:51:43 PM PDT 24 2645561335 ps
T917 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.984852813 Jun 25 05:51:21 PM PDT 24 Jun 25 05:51:25 PM PDT 24 1370244808 ps
T918 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2835475431 Jun 25 05:51:26 PM PDT 24 Jun 25 05:51:50 PM PDT 24 17349202503 ps
T919 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2852707799 Jun 25 05:51:38 PM PDT 24 Jun 25 05:51:40 PM PDT 24 419150877 ps
T920 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3466325534 Jun 25 05:51:40 PM PDT 24 Jun 25 05:51:59 PM PDT 24 4539366405 ps

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.1906600723
Short name T4
Test name
Test status
Simulation time 477389438476 ps
CPU time 890.82 seconds
Started Jun 25 05:52:01 PM PDT 24
Finished Jun 25 06:06:54 PM PDT 24
Peak memory 210368 kb
Host smart-4ad37ae0-6052-4712-b951-7266d1247fb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906600723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
1906600723
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2262131981
Short name T12
Test name
Test status
Simulation time 492709000580 ps
CPU time 706.14 seconds
Started Jun 25 05:52:17 PM PDT 24
Finished Jun 25 06:04:05 PM PDT 24
Peak memory 210488 kb
Host smart-eee938f8-72c0-4422-86c5-2e10ad705c75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262131981 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2262131981
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.2718915406
Short name T5
Test name
Test status
Simulation time 490162020246 ps
CPU time 306.31 seconds
Started Jun 25 05:54:34 PM PDT 24
Finished Jun 25 05:59:41 PM PDT 24
Peak memory 201884 kb
Host smart-1964714a-05ec-495a-8123-15fe6b4d4502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718915406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.2718915406
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.196288582
Short name T60
Test name
Test status
Simulation time 549012469304 ps
CPU time 228.97 seconds
Started Jun 25 05:56:44 PM PDT 24
Finished Jun 25 06:00:33 PM PDT 24
Peak memory 201852 kb
Host smart-fd7211d1-da3e-4fb8-9821-9b8d165f64e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196288582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gati
ng.196288582
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.717665719
Short name T51
Test name
Test status
Simulation time 312279825450 ps
CPU time 211.32 seconds
Started Jun 25 05:52:14 PM PDT 24
Finished Jun 25 05:55:46 PM PDT 24
Peak memory 210248 kb
Host smart-3c2a3d57-ee45-4a46-9e16-94b7a99bcd91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717665719 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.717665719
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.1228833058
Short name T7
Test name
Test status
Simulation time 510696058710 ps
CPU time 121.1 seconds
Started Jun 25 05:52:48 PM PDT 24
Finished Jun 25 05:54:50 PM PDT 24
Peak memory 201856 kb
Host smart-57cfbd9a-c8a4-4c97-86b8-efb80e77e1e5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228833058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.1228833058
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2250560222
Short name T15
Test name
Test status
Simulation time 193059171085 ps
CPU time 204.99 seconds
Started Jun 25 05:53:14 PM PDT 24
Finished Jun 25 05:56:40 PM PDT 24
Peak memory 210508 kb
Host smart-abe5964b-4f87-4f2d-b52d-08c731d1f31c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250560222 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2250560222
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.977908982
Short name T242
Test name
Test status
Simulation time 747698612452 ps
CPU time 1153.76 seconds
Started Jun 25 05:55:26 PM PDT 24
Finished Jun 25 06:14:41 PM PDT 24
Peak memory 210356 kb
Host smart-7c1f6f23-a4a9-4426-b999-ba9797ebec3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977908982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.
977908982
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.4160756846
Short name T237
Test name
Test status
Simulation time 517017548705 ps
CPU time 427.69 seconds
Started Jun 25 05:52:21 PM PDT 24
Finished Jun 25 05:59:30 PM PDT 24
Peak memory 201864 kb
Host smart-ed1eb360-9876-4795-992f-5a6c7ad2ee7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160756846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.4160756846
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.2065535374
Short name T171
Test name
Test status
Simulation time 529657161859 ps
CPU time 1120.28 seconds
Started Jun 25 05:52:11 PM PDT 24
Finished Jun 25 06:10:53 PM PDT 24
Peak memory 201860 kb
Host smart-82b85417-ad54-4a69-aaeb-4fa869cb6568
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065535374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.2065535374
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.3331456002
Short name T79
Test name
Test status
Simulation time 3881798292 ps
CPU time 8.4 seconds
Started Jun 25 05:51:51 PM PDT 24
Finished Jun 25 05:52:01 PM PDT 24
Peak memory 217176 kb
Host smart-84c9eb78-f26c-4f23-98bb-1604881a9c38
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331456002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.3331456002
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3161167366
Short name T238
Test name
Test status
Simulation time 363077153224 ps
CPU time 725.42 seconds
Started Jun 25 05:54:11 PM PDT 24
Finished Jun 25 06:06:17 PM PDT 24
Peak memory 201848 kb
Host smart-9590d52f-8937-4e41-ab37-5bdb0da6db7f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161167366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3161167366
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2857684147
Short name T186
Test name
Test status
Simulation time 493168085248 ps
CPU time 80.22 seconds
Started Jun 25 05:51:51 PM PDT 24
Finished Jun 25 05:53:14 PM PDT 24
Peak memory 201864 kb
Host smart-8d09daa0-429d-4aec-801a-90ebc7bcb483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857684147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2857684147
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.3583536441
Short name T62
Test name
Test status
Simulation time 490170058102 ps
CPU time 168.74 seconds
Started Jun 25 05:54:56 PM PDT 24
Finished Jun 25 05:57:46 PM PDT 24
Peak memory 201888 kb
Host smart-f3dc493c-c26f-429f-b902-59dd2a816a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583536441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3583536441
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2682546214
Short name T77
Test name
Test status
Simulation time 534634692 ps
CPU time 1.91 seconds
Started Jun 25 05:51:26 PM PDT 24
Finished Jun 25 05:51:30 PM PDT 24
Peak memory 201828 kb
Host smart-833be54b-8a1c-4e6f-a36b-647134ff05f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682546214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2682546214
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3746182863
Short name T133
Test name
Test status
Simulation time 25322987356 ps
CPU time 100.3 seconds
Started Jun 25 05:51:19 PM PDT 24
Finished Jun 25 05:53:01 PM PDT 24
Peak memory 201900 kb
Host smart-676b53f7-16ce-400a-bde3-d02d4e30c323
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746182863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.3746182863
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1789403231
Short name T156
Test name
Test status
Simulation time 485638600463 ps
CPU time 480.73 seconds
Started Jun 25 05:52:26 PM PDT 24
Finished Jun 25 06:00:28 PM PDT 24
Peak memory 201800 kb
Host smart-a285fdf0-385f-4024-ac28-f07120724c2e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789403231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1789403231
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.2020293911
Short name T239
Test name
Test status
Simulation time 329296302248 ps
CPU time 720.14 seconds
Started Jun 25 05:52:34 PM PDT 24
Finished Jun 25 06:04:36 PM PDT 24
Peak memory 201896 kb
Host smart-9c36db19-224a-4812-8104-18f0b698ce68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020293911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.2020293911
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.4284236737
Short name T221
Test name
Test status
Simulation time 489647650724 ps
CPU time 118.28 seconds
Started Jun 25 05:52:09 PM PDT 24
Finished Jun 25 05:54:09 PM PDT 24
Peak memory 201848 kb
Host smart-613e7299-13bd-4e59-a5fd-f0f4e6d51158
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284236737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.4284236737
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.1488769409
Short name T263
Test name
Test status
Simulation time 358949762571 ps
CPU time 870.56 seconds
Started Jun 25 05:53:56 PM PDT 24
Finished Jun 25 06:08:27 PM PDT 24
Peak memory 201844 kb
Host smart-508cc061-463b-436b-941d-08c74eab19c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488769409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.1488769409
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.4169433860
Short name T211
Test name
Test status
Simulation time 500877861378 ps
CPU time 94.4 seconds
Started Jun 25 05:56:03 PM PDT 24
Finished Jun 25 05:57:39 PM PDT 24
Peak memory 201916 kb
Host smart-7e7f3b34-be94-4636-ab55-743ed1257cf0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169433860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.4169433860
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3609466784
Short name T49
Test name
Test status
Simulation time 430078319090 ps
CPU time 231.85 seconds
Started Jun 25 05:52:42 PM PDT 24
Finished Jun 25 05:56:34 PM PDT 24
Peak memory 210544 kb
Host smart-953451dd-9959-4147-b666-16b5044894db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609466784 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.3609466784
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.2264197171
Short name T246
Test name
Test status
Simulation time 507357507102 ps
CPU time 558.18 seconds
Started Jun 25 05:55:15 PM PDT 24
Finished Jun 25 06:04:34 PM PDT 24
Peak memory 201868 kb
Host smart-ec4575d9-015f-4b93-9c5b-bfe5ce45aa99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264197171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.2264197171
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.3215838836
Short name T166
Test name
Test status
Simulation time 518752860327 ps
CPU time 649.87 seconds
Started Jun 25 05:54:11 PM PDT 24
Finished Jun 25 06:05:01 PM PDT 24
Peak memory 201912 kb
Host smart-d655e2e4-0906-4967-aaa5-5fb5c70c80dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215838836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.3215838836
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3599119025
Short name T264
Test name
Test status
Simulation time 502214034560 ps
CPU time 284.31 seconds
Started Jun 25 05:54:12 PM PDT 24
Finished Jun 25 05:58:56 PM PDT 24
Peak memory 201868 kb
Host smart-e5ce1cc8-5458-459d-bfb4-d7a9b58a58b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599119025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3599119025
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2285251897
Short name T110
Test name
Test status
Simulation time 500037905645 ps
CPU time 154.31 seconds
Started Jun 25 05:52:40 PM PDT 24
Finished Jun 25 05:55:14 PM PDT 24
Peak memory 201908 kb
Host smart-e6eb2a74-ac30-4f8f-b98a-6a08573991f8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285251897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2285251897
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2625990990
Short name T89
Test name
Test status
Simulation time 8338279873 ps
CPU time 21.9 seconds
Started Jun 25 05:51:28 PM PDT 24
Finished Jun 25 05:51:52 PM PDT 24
Peak memory 201900 kb
Host smart-cde3ca7f-9254-4b4c-87a5-129bd2cf9112
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625990990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2625990990
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.513311630
Short name T56
Test name
Test status
Simulation time 163106359702 ps
CPU time 91.98 seconds
Started Jun 25 05:55:47 PM PDT 24
Finished Jun 25 05:57:20 PM PDT 24
Peak memory 201840 kb
Host smart-74d40aac-5016-4180-9b3b-30925355d2ac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=513311630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrup
t_fixed.513311630
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1029640188
Short name T249
Test name
Test status
Simulation time 330020846054 ps
CPU time 703.73 seconds
Started Jun 25 05:55:34 PM PDT 24
Finished Jun 25 06:07:19 PM PDT 24
Peak memory 201876 kb
Host smart-b221c83d-c6b3-4af0-a3ff-18eb6de64c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029640188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1029640188
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2357675160
Short name T400
Test name
Test status
Simulation time 305498200 ps
CPU time 0.8 seconds
Started Jun 25 05:52:40 PM PDT 24
Finished Jun 25 05:52:42 PM PDT 24
Peak memory 201608 kb
Host smart-3e2a7b6b-10ab-4703-be1f-280459480275
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357675160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2357675160
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.4056293115
Short name T277
Test name
Test status
Simulation time 551448030277 ps
CPU time 553.35 seconds
Started Jun 25 05:52:11 PM PDT 24
Finished Jun 25 06:01:26 PM PDT 24
Peak memory 201848 kb
Host smart-52c4814c-492a-4dc4-8ff1-9d4d2e979a29
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056293115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.4056293115
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2638018722
Short name T269
Test name
Test status
Simulation time 320713282052 ps
CPU time 274.53 seconds
Started Jun 25 05:55:42 PM PDT 24
Finished Jun 25 06:00:17 PM PDT 24
Peak memory 201896 kb
Host smart-a7bbae32-3b85-46e8-8a18-2bd1fd4dfa7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638018722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2638018722
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.2930350484
Short name T241
Test name
Test status
Simulation time 656311034174 ps
CPU time 195.37 seconds
Started Jun 25 05:56:43 PM PDT 24
Finished Jun 25 05:59:59 PM PDT 24
Peak memory 201864 kb
Host smart-154f2e79-345e-4f6b-8c34-fa84cc8050c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930350484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.2930350484
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3598061242
Short name T83
Test name
Test status
Simulation time 422479468 ps
CPU time 3.06 seconds
Started Jun 25 05:51:33 PM PDT 24
Finished Jun 25 05:51:38 PM PDT 24
Peak memory 217852 kb
Host smart-f6873854-fe43-4e2e-8196-bea3522c1e5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598061242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.3598061242
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.3519428539
Short name T290
Test name
Test status
Simulation time 359711278429 ps
CPU time 775.77 seconds
Started Jun 25 05:51:49 PM PDT 24
Finished Jun 25 06:04:45 PM PDT 24
Peak memory 201892 kb
Host smart-ee97aa32-7d31-45d2-a025-c53c61d02362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519428539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.3519428539
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2227044187
Short name T206
Test name
Test status
Simulation time 331085314228 ps
CPU time 136.05 seconds
Started Jun 25 05:51:51 PM PDT 24
Finished Jun 25 05:54:09 PM PDT 24
Peak memory 201920 kb
Host smart-cb6df647-23b8-4c59-b5f5-3e3c730c4fcd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227044187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2227044187
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.2283467374
Short name T274
Test name
Test status
Simulation time 402149134240 ps
CPU time 487.4 seconds
Started Jun 25 05:52:16 PM PDT 24
Finished Jun 25 06:00:25 PM PDT 24
Peak memory 201888 kb
Host smart-8c9a6527-eaf6-46af-b3cf-86ad9c69df99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283467374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2283467374
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3672093982
Short name T53
Test name
Test status
Simulation time 211463872374 ps
CPU time 388.76 seconds
Started Jun 25 05:52:33 PM PDT 24
Finished Jun 25 05:59:02 PM PDT 24
Peak memory 210552 kb
Host smart-e1c31fc7-dd0f-4e3b-a25e-6d8836be05e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672093982 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.3672093982
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.930219
Short name T54
Test name
Test status
Simulation time 34174391635 ps
CPU time 81 seconds
Started Jun 25 05:55:33 PM PDT 24
Finished Jun 25 05:56:54 PM PDT 24
Peak memory 201996 kb
Host smart-7d967922-5174-4b0a-9153-56d9657dfe31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930219 -assert nopostp
roc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.930219
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1383686147
Short name T266
Test name
Test status
Simulation time 327803073333 ps
CPU time 205.83 seconds
Started Jun 25 05:57:31 PM PDT 24
Finished Jun 25 06:01:02 PM PDT 24
Peak memory 201848 kb
Host smart-50f9e9bc-b36b-4c7a-af82-9cf64e50ede5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383686147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1383686147
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2943591512
Short name T331
Test name
Test status
Simulation time 203661969700 ps
CPU time 385.01 seconds
Started Jun 25 05:55:41 PM PDT 24
Finished Jun 25 06:02:07 PM PDT 24
Peak memory 211520 kb
Host smart-ba22a95e-37f5-4544-8f5f-81a6c3cd70c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943591512 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2943591512
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.4239836703
Short name T318
Test name
Test status
Simulation time 163912301243 ps
CPU time 365.84 seconds
Started Jun 25 05:52:11 PM PDT 24
Finished Jun 25 05:58:18 PM PDT 24
Peak memory 210500 kb
Host smart-30cd9c25-df77-4084-b756-627dd6bcf459
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239836703 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.4239836703
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.978867684
Short name T175
Test name
Test status
Simulation time 485948048718 ps
CPU time 1127.01 seconds
Started Jun 25 05:52:35 PM PDT 24
Finished Jun 25 06:11:23 PM PDT 24
Peak memory 201900 kb
Host smart-42ea495e-eb5a-49de-98ea-641eab1b1b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978867684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.978867684
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.3700764117
Short name T303
Test name
Test status
Simulation time 1471435209526 ps
CPU time 1222.35 seconds
Started Jun 25 05:54:26 PM PDT 24
Finished Jun 25 06:14:49 PM PDT 24
Peak memory 210360 kb
Host smart-e2be8f1b-e3a2-4484-b38b-b6b743911126
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700764117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.3700764117
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1040810251
Short name T257
Test name
Test status
Simulation time 539506570369 ps
CPU time 1249.33 seconds
Started Jun 25 05:55:40 PM PDT 24
Finished Jun 25 06:16:30 PM PDT 24
Peak memory 201948 kb
Host smart-4c3befcf-8ffc-40f6-b399-772875816cbf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040810251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1040810251
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3819253331
Short name T289
Test name
Test status
Simulation time 216709653475 ps
CPU time 96.1 seconds
Started Jun 25 05:56:03 PM PDT 24
Finished Jun 25 05:57:41 PM PDT 24
Peak memory 201928 kb
Host smart-5dab7be1-a399-4763-b4cd-842e4951dfde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819253331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3819253331
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.760734337
Short name T150
Test name
Test status
Simulation time 4795317442 ps
CPU time 3.74 seconds
Started Jun 25 05:51:19 PM PDT 24
Finished Jun 25 05:51:24 PM PDT 24
Peak memory 201868 kb
Host smart-02a1bb80-3e80-4212-baee-72b99f53f2bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760734337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.760734337
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.3600779682
Short name T259
Test name
Test status
Simulation time 194088200948 ps
CPU time 410.19 seconds
Started Jun 25 05:53:05 PM PDT 24
Finished Jun 25 05:59:56 PM PDT 24
Peak memory 201844 kb
Host smart-99fad5c9-ae83-4a3e-afc7-f3c994d1f0ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600779682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.3600779682
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.2110061817
Short name T288
Test name
Test status
Simulation time 367628322564 ps
CPU time 381.36 seconds
Started Jun 25 05:53:56 PM PDT 24
Finished Jun 25 06:00:18 PM PDT 24
Peak memory 201844 kb
Host smart-1f360570-98ff-47af-86c7-5d6359d6481b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110061817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.2110061817
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.43597094
Short name T243
Test name
Test status
Simulation time 571805742373 ps
CPU time 1386.88 seconds
Started Jun 25 05:54:06 PM PDT 24
Finished Jun 25 06:17:14 PM PDT 24
Peak memory 201884 kb
Host smart-118a5aff-1745-4b08-a039-f026a7ed9645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43597094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.43597094
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.670813875
Short name T33
Test name
Test status
Simulation time 176581642137 ps
CPU time 373.89 seconds
Started Jun 25 05:53:02 PM PDT 24
Finished Jun 25 05:59:17 PM PDT 24
Peak memory 201860 kb
Host smart-da11093d-3c3e-421f-bae9-402cb250f6e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670813875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.
670813875
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.2224537022
Short name T316
Test name
Test status
Simulation time 342429199611 ps
CPU time 460.14 seconds
Started Jun 25 05:53:16 PM PDT 24
Finished Jun 25 06:00:57 PM PDT 24
Peak memory 201932 kb
Host smart-c5f2871c-0efe-4772-9b69-eac1652617bb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224537022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.2224537022
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.42871971
Short name T322
Test name
Test status
Simulation time 202348140523 ps
CPU time 466.9 seconds
Started Jun 25 05:52:54 PM PDT 24
Finished Jun 25 06:00:42 PM PDT 24
Peak memory 201884 kb
Host smart-ba89fe92-262c-4c69-bf50-8eca14af02ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42871971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_w
akeup.42871971
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.68116632
Short name T284
Test name
Test status
Simulation time 165736582656 ps
CPU time 191.41 seconds
Started Jun 25 05:53:15 PM PDT 24
Finished Jun 25 05:56:27 PM PDT 24
Peak memory 201892 kb
Host smart-90c057bd-0da3-48a0-9cc4-567f8bf75ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68116632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.68116632
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1522767808
Short name T193
Test name
Test status
Simulation time 329390905883 ps
CPU time 158.02 seconds
Started Jun 25 05:55:19 PM PDT 24
Finished Jun 25 05:57:58 PM PDT 24
Peak memory 201844 kb
Host smart-f42f84da-58c6-42a0-91d9-e438622ef5c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522767808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1522767808
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2258578202
Short name T236
Test name
Test status
Simulation time 164628513221 ps
CPU time 100.38 seconds
Started Jun 25 05:57:22 PM PDT 24
Finished Jun 25 05:59:04 PM PDT 24
Peak memory 201896 kb
Host smart-61502a46-d044-442a-aa09-ce45d899cd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258578202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2258578202
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.1082413168
Short name T118
Test name
Test status
Simulation time 343494852481 ps
CPU time 829.55 seconds
Started Jun 25 05:52:25 PM PDT 24
Finished Jun 25 06:06:16 PM PDT 24
Peak memory 201844 kb
Host smart-b26fbcff-7929-4d15-9c8a-4c01c51b0ac6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082413168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.1082413168
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.3846038635
Short name T325
Test name
Test status
Simulation time 432751292916 ps
CPU time 466.78 seconds
Started Jun 25 05:52:34 PM PDT 24
Finished Jun 25 06:00:23 PM PDT 24
Peak memory 201856 kb
Host smart-f7c25767-b8ed-404c-827b-077c1cf6077c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846038635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.3846038635
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.40799663
Short name T272
Test name
Test status
Simulation time 535206138300 ps
CPU time 143.84 seconds
Started Jun 25 05:51:50 PM PDT 24
Finished Jun 25 05:54:16 PM PDT 24
Peak memory 201844 kb
Host smart-601995a1-3143-452c-9eb1-a6aa5c97795e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40799663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_wa
keup.40799663
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.1453381410
Short name T225
Test name
Test status
Simulation time 127813855580 ps
CPU time 410.93 seconds
Started Jun 25 05:52:55 PM PDT 24
Finished Jun 25 05:59:46 PM PDT 24
Peak memory 202112 kb
Host smart-a579c411-f479-448b-b575-ac45c2e215e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453381410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1453381410
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.764232246
Short name T197
Test name
Test status
Simulation time 598770318518 ps
CPU time 156.74 seconds
Started Jun 25 05:53:15 PM PDT 24
Finished Jun 25 05:55:53 PM PDT 24
Peak memory 201916 kb
Host smart-92909947-33a3-4dab-b20d-eea23210c730
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764232246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_
wakeup.764232246
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2972988668
Short name T196
Test name
Test status
Simulation time 329776363020 ps
CPU time 89.06 seconds
Started Jun 25 05:53:24 PM PDT 24
Finished Jun 25 05:54:54 PM PDT 24
Peak memory 201872 kb
Host smart-7655379c-a959-4fe2-a696-c03adbec1797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972988668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2972988668
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1758092415
Short name T295
Test name
Test status
Simulation time 507271739712 ps
CPU time 199.27 seconds
Started Jun 25 05:55:26 PM PDT 24
Finished Jun 25 05:58:46 PM PDT 24
Peak memory 201884 kb
Host smart-99d6ca6e-4ae3-477e-aa14-ed51d5a6358a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758092415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1758092415
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3085920740
Short name T302
Test name
Test status
Simulation time 490536129538 ps
CPU time 249.66 seconds
Started Jun 25 05:57:32 PM PDT 24
Finished Jun 25 06:01:47 PM PDT 24
Peak memory 202044 kb
Host smart-ccaaefde-7e8d-470f-955a-cda24b31f44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085920740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3085920740
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1062099117
Short name T74
Test name
Test status
Simulation time 8461645426 ps
CPU time 22.24 seconds
Started Jun 25 05:51:24 PM PDT 24
Finished Jun 25 05:51:48 PM PDT 24
Peak memory 201844 kb
Host smart-26cacfa3-6738-4b07-b7da-57548d311d51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062099117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1062099117
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1468457626
Short name T310
Test name
Test status
Simulation time 165253566367 ps
CPU time 188.59 seconds
Started Jun 25 05:52:20 PM PDT 24
Finished Jun 25 05:55:30 PM PDT 24
Peak memory 201888 kb
Host smart-242bd90f-e793-4fed-9e82-3bb090f48a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468457626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1468457626
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.1053940292
Short name T348
Test name
Test status
Simulation time 72290771666 ps
CPU time 391.1 seconds
Started Jun 25 05:52:46 PM PDT 24
Finished Jun 25 05:59:17 PM PDT 24
Peak memory 202208 kb
Host smart-021ee36e-e96a-42a4-9878-c25a9abd5326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053940292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1053940292
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.138454563
Short name T347
Test name
Test status
Simulation time 40027045146 ps
CPU time 134.91 seconds
Started Jun 25 05:53:02 PM PDT 24
Finished Jun 25 05:55:17 PM PDT 24
Peak memory 210548 kb
Host smart-3aa44f66-88a1-4bb9-bd8e-814d9d3f7e9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138454563 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.138454563
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.2776220868
Short name T212
Test name
Test status
Simulation time 501965129006 ps
CPU time 271.41 seconds
Started Jun 25 05:54:03 PM PDT 24
Finished Jun 25 05:58:35 PM PDT 24
Peak memory 201872 kb
Host smart-7406a005-81b9-4131-9185-d205e1e85fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776220868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.2776220868
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1578381515
Short name T174
Test name
Test status
Simulation time 603543276911 ps
CPU time 1434.38 seconds
Started Jun 25 05:54:53 PM PDT 24
Finished Jun 25 06:18:49 PM PDT 24
Peak memory 201880 kb
Host smart-ee990ee3-a30d-4b8d-bf3d-7936076a8fc8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578381515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.1578381515
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1565400748
Short name T202
Test name
Test status
Simulation time 576644686369 ps
CPU time 338.26 seconds
Started Jun 25 05:51:51 PM PDT 24
Finished Jun 25 05:57:31 PM PDT 24
Peak memory 201880 kb
Host smart-f60cddb1-9b8b-4b01-bec5-5a754d4f36fe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565400748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1565400748
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1267743242
Short name T392
Test name
Test status
Simulation time 612316949840 ps
CPU time 390.56 seconds
Started Jun 25 05:52:16 PM PDT 24
Finished Jun 25 05:58:48 PM PDT 24
Peak memory 201856 kb
Host smart-eac55aad-6afe-445f-96df-8d2d2697dd23
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267743242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1267743242
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3202557676
Short name T582
Test name
Test status
Simulation time 164643090148 ps
CPU time 210.51 seconds
Started Jun 25 05:52:34 PM PDT 24
Finished Jun 25 05:56:06 PM PDT 24
Peak memory 201980 kb
Host smart-87a4a3c6-ad05-4247-a39c-0537ae75c6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202557676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3202557676
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2837621405
Short name T232
Test name
Test status
Simulation time 138180964206 ps
CPU time 371.68 seconds
Started Jun 25 05:53:16 PM PDT 24
Finished Jun 25 05:59:28 PM PDT 24
Peak memory 202164 kb
Host smart-bc5273fa-0356-420f-936e-5754d4bc7a7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837621405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2837621405
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.3496830748
Short name T151
Test name
Test status
Simulation time 357849386951 ps
CPU time 131.93 seconds
Started Jun 25 05:53:24 PM PDT 24
Finished Jun 25 05:55:37 PM PDT 24
Peak memory 201800 kb
Host smart-bc9fc853-c132-4d2d-9300-bf168c76120f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496830748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.3496830748
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.1697616791
Short name T344
Test name
Test status
Simulation time 119483380626 ps
CPU time 483.23 seconds
Started Jun 25 05:54:26 PM PDT 24
Finished Jun 25 06:02:30 PM PDT 24
Peak memory 202256 kb
Host smart-19b14978-2826-4b22-8fb6-c07296466b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697616791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.1697616791
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.2002233911
Short name T326
Test name
Test status
Simulation time 360632741411 ps
CPU time 101.45 seconds
Started Jun 25 05:52:01 PM PDT 24
Finished Jun 25 05:53:44 PM PDT 24
Peak memory 201864 kb
Host smart-53a90735-c759-4351-bea8-51f7ce355d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002233911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2002233911
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.228065316
Short name T209
Test name
Test status
Simulation time 336504133970 ps
CPU time 197.21 seconds
Started Jun 25 05:54:32 PM PDT 24
Finished Jun 25 05:57:50 PM PDT 24
Peak memory 201860 kb
Host smart-af4542d6-1b9d-43f5-8044-f6d36cc699dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228065316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gati
ng.228065316
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3169574399
Short name T255
Test name
Test status
Simulation time 193985077152 ps
CPU time 109.12 seconds
Started Jun 25 05:55:04 PM PDT 24
Finished Jun 25 05:56:54 PM PDT 24
Peak memory 201980 kb
Host smart-8f4df39a-9801-4603-a479-37097bdf27dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169574399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3169574399
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1520026619
Short name T230
Test name
Test status
Simulation time 97949724764 ps
CPU time 361.53 seconds
Started Jun 25 05:56:05 PM PDT 24
Finished Jun 25 06:02:07 PM PDT 24
Peak memory 202184 kb
Host smart-f412efad-e7a6-48d9-95cb-2b11cdff1845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520026619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1520026619
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.842445852
Short name T297
Test name
Test status
Simulation time 334381437339 ps
CPU time 722.49 seconds
Started Jun 25 05:56:20 PM PDT 24
Finished Jun 25 06:08:23 PM PDT 24
Peak memory 201860 kb
Host smart-ecde5241-3e48-4e2b-a36c-04409968ebcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842445852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.842445852
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.984852813
Short name T917
Test name
Test status
Simulation time 1370244808 ps
CPU time 3.14 seconds
Started Jun 25 05:51:21 PM PDT 24
Finished Jun 25 05:51:25 PM PDT 24
Peak memory 201724 kb
Host smart-bddeb4da-cb21-447a-9f83-5aefc55727b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984852813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alias
ing.984852813
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3480998011
Short name T71
Test name
Test status
Simulation time 27016414353 ps
CPU time 10.44 seconds
Started Jun 25 05:51:23 PM PDT 24
Finished Jun 25 05:51:35 PM PDT 24
Peak memory 201824 kb
Host smart-17dc1203-c86a-4f92-b90c-37a7c9fc5925
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480998011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.3480998011
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3301329485
Short name T140
Test name
Test status
Simulation time 924293066 ps
CPU time 0.84 seconds
Started Jun 25 05:51:24 PM PDT 24
Finished Jun 25 05:51:26 PM PDT 24
Peak memory 201488 kb
Host smart-82f85b45-0414-4b58-9d10-3d68a2ac2b6c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301329485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.3301329485
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.283025853
Short name T803
Test name
Test status
Simulation time 442437433 ps
CPU time 2.02 seconds
Started Jun 25 05:51:23 PM PDT 24
Finished Jun 25 05:51:27 PM PDT 24
Peak memory 201548 kb
Host smart-ebfbd724-b66e-4787-943a-69e1e0e645fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283025853 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.283025853
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2931778473
Short name T817
Test name
Test status
Simulation time 323901043 ps
CPU time 1.18 seconds
Started Jun 25 05:51:19 PM PDT 24
Finished Jun 25 05:51:22 PM PDT 24
Peak memory 201528 kb
Host smart-786b4338-411c-422b-a03a-9bbb91bac10b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931778473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2931778473
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.83323621
Short name T815
Test name
Test status
Simulation time 386226410 ps
CPU time 0.8 seconds
Started Jun 25 05:51:17 PM PDT 24
Finished Jun 25 05:51:19 PM PDT 24
Peak memory 201360 kb
Host smart-0cb3e8b2-8f0b-40c1-a820-b5bbab003eb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83323621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.83323621
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2591150446
Short name T844
Test name
Test status
Simulation time 459590930 ps
CPU time 3.71 seconds
Started Jun 25 05:51:18 PM PDT 24
Finished Jun 25 05:51:24 PM PDT 24
Peak memory 217720 kb
Host smart-415ab287-9b68-4cf3-9fe6-44110c26b50a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591150446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2591150446
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3747232506
Short name T830
Test name
Test status
Simulation time 8625558830 ps
CPU time 7.23 seconds
Started Jun 25 05:51:19 PM PDT 24
Finished Jun 25 05:51:28 PM PDT 24
Peak memory 201832 kb
Host smart-5198ad1b-9a5d-4d90-838e-00bfc8a1efbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747232506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3747232506
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3134489666
Short name T816
Test name
Test status
Simulation time 1271598437 ps
CPU time 5.19 seconds
Started Jun 25 05:51:19 PM PDT 24
Finished Jun 25 05:51:26 PM PDT 24
Peak memory 201744 kb
Host smart-aedf7d6d-4474-4b8f-9137-d7e27c4b7572
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134489666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3134489666
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1295492087
Short name T849
Test name
Test status
Simulation time 735647589 ps
CPU time 1.12 seconds
Started Jun 25 05:51:19 PM PDT 24
Finished Jun 25 05:51:22 PM PDT 24
Peak memory 201528 kb
Host smart-ec5dc7c7-5b25-498d-8176-4b597cf699ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295492087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.1295492087
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3204968042
Short name T822
Test name
Test status
Simulation time 607995116 ps
CPU time 1.36 seconds
Started Jun 25 05:51:20 PM PDT 24
Finished Jun 25 05:51:23 PM PDT 24
Peak memory 201568 kb
Host smart-1f73d8e2-968c-4aca-b5c6-28eddca2b315
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204968042 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3204968042
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3069874355
Short name T138
Test name
Test status
Simulation time 533535854 ps
CPU time 0.98 seconds
Started Jun 25 05:51:24 PM PDT 24
Finished Jun 25 05:51:26 PM PDT 24
Peak memory 201508 kb
Host smart-cf954ed7-6e4b-4f17-9d93-fcf6ea398631
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069874355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.3069874355
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.572799840
Short name T811
Test name
Test status
Simulation time 344726077 ps
CPU time 0.98 seconds
Started Jun 25 05:51:24 PM PDT 24
Finished Jun 25 05:51:27 PM PDT 24
Peak memory 201432 kb
Host smart-f5930441-5280-4ec2-aaa3-3dd28b03ce74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572799840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.572799840
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3826812870
Short name T840
Test name
Test status
Simulation time 5396840188 ps
CPU time 5.28 seconds
Started Jun 25 05:51:23 PM PDT 24
Finished Jun 25 05:51:29 PM PDT 24
Peak memory 201856 kb
Host smart-5230f14a-2fde-4fa5-99aa-91ba122bea3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826812870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3826812870
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1469955312
Short name T913
Test name
Test status
Simulation time 543258607 ps
CPU time 2.14 seconds
Started Jun 25 05:51:18 PM PDT 24
Finished Jun 25 05:51:21 PM PDT 24
Peak memory 201796 kb
Host smart-0d2b4a7e-c09e-4359-a9b5-f9fa16ec5e3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469955312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.1469955312
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3928109657
Short name T825
Test name
Test status
Simulation time 456715741 ps
CPU time 1.97 seconds
Started Jun 25 05:51:34 PM PDT 24
Finished Jun 25 05:51:38 PM PDT 24
Peak memory 201576 kb
Host smart-9f91dc87-f9da-49d5-aaf0-c1248a6ee227
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928109657 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3928109657
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1190495034
Short name T142
Test name
Test status
Simulation time 425295761 ps
CPU time 1.68 seconds
Started Jun 25 05:51:36 PM PDT 24
Finished Jun 25 05:51:40 PM PDT 24
Peak memory 201512 kb
Host smart-e6bf59d0-2654-43e7-ae10-58400b987054
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190495034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.1190495034
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1693954049
Short name T819
Test name
Test status
Simulation time 316637591 ps
CPU time 1.37 seconds
Started Jun 25 05:51:35 PM PDT 24
Finished Jun 25 05:51:38 PM PDT 24
Peak memory 201432 kb
Host smart-9a85b1bc-020d-4aa8-9ace-4d2042b05f4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693954049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.1693954049
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3301057278
Short name T856
Test name
Test status
Simulation time 2534677394 ps
CPU time 3.68 seconds
Started Jun 25 05:51:36 PM PDT 24
Finished Jun 25 05:51:42 PM PDT 24
Peak memory 201620 kb
Host smart-d4fd9cad-9bab-4dce-8bc7-c63641080376
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301057278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.3301057278
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2919738446
Short name T866
Test name
Test status
Simulation time 767326901 ps
CPU time 3.04 seconds
Started Jun 25 05:51:34 PM PDT 24
Finished Jun 25 05:51:38 PM PDT 24
Peak memory 217776 kb
Host smart-26b86d16-06f0-459b-9a7d-aa4a44cbb51f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919738446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2919738446
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.606562125
Short name T889
Test name
Test status
Simulation time 4202663266 ps
CPU time 8.03 seconds
Started Jun 25 05:51:37 PM PDT 24
Finished Jun 25 05:51:47 PM PDT 24
Peak memory 201768 kb
Host smart-aca04fa4-1a21-4f05-8ee4-963321055b6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606562125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.606562125
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2336239479
Short name T893
Test name
Test status
Simulation time 465110945 ps
CPU time 1.32 seconds
Started Jun 25 05:51:33 PM PDT 24
Finished Jun 25 05:51:35 PM PDT 24
Peak memory 201588 kb
Host smart-8e142e85-84dc-4136-9251-fa463a709a60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336239479 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2336239479
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3180497733
Short name T852
Test name
Test status
Simulation time 514159835 ps
CPU time 1.95 seconds
Started Jun 25 05:51:36 PM PDT 24
Finished Jun 25 05:51:39 PM PDT 24
Peak memory 201508 kb
Host smart-cb71f332-9b7e-4bb1-b91d-a21c17fee1b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180497733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3180497733
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2347459357
Short name T861
Test name
Test status
Simulation time 524797380 ps
CPU time 0.89 seconds
Started Jun 25 05:51:33 PM PDT 24
Finished Jun 25 05:51:35 PM PDT 24
Peak memory 201432 kb
Host smart-26095450-f9ff-4bcf-ab06-92ffb64b293a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347459357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2347459357
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3679741634
Short name T72
Test name
Test status
Simulation time 4426729639 ps
CPU time 17.16 seconds
Started Jun 25 05:51:34 PM PDT 24
Finished Jun 25 05:51:52 PM PDT 24
Peak memory 201828 kb
Host smart-6408e65e-2a50-4583-8737-ee3131991f76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679741634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.3679741634
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1967995432
Short name T881
Test name
Test status
Simulation time 617269763 ps
CPU time 3.11 seconds
Started Jun 25 05:51:35 PM PDT 24
Finished Jun 25 05:51:39 PM PDT 24
Peak memory 210008 kb
Host smart-1293d9eb-3fb2-4c48-a356-2ff0698d745e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967995432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.1967995432
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2301316486
Short name T903
Test name
Test status
Simulation time 8631979466 ps
CPU time 22.8 seconds
Started Jun 25 05:51:35 PM PDT 24
Finished Jun 25 05:51:59 PM PDT 24
Peak memory 201716 kb
Host smart-1b6cca26-7bb9-42c8-9908-dda3763902b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301316486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2301316486
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1242069376
Short name T859
Test name
Test status
Simulation time 594878770 ps
CPU time 1.56 seconds
Started Jun 25 05:51:35 PM PDT 24
Finished Jun 25 05:51:38 PM PDT 24
Peak memory 201576 kb
Host smart-318bb1c9-cafd-4a6c-8e7b-8ad2666782e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242069376 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.1242069376
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2421787477
Short name T900
Test name
Test status
Simulation time 558563331 ps
CPU time 1.57 seconds
Started Jun 25 05:51:33 PM PDT 24
Finished Jun 25 05:51:35 PM PDT 24
Peak memory 201516 kb
Host smart-5a9a41fa-2da5-4257-9667-a405ed874cd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421787477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.2421787477
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.651916478
Short name T874
Test name
Test status
Simulation time 380432397 ps
CPU time 1.52 seconds
Started Jun 25 05:51:35 PM PDT 24
Finished Jun 25 05:51:38 PM PDT 24
Peak memory 201456 kb
Host smart-25e4c517-f02e-46e9-bb28-026d77602aee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651916478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.651916478
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3418744934
Short name T880
Test name
Test status
Simulation time 2397296727 ps
CPU time 9.36 seconds
Started Jun 25 05:51:36 PM PDT 24
Finished Jun 25 05:51:46 PM PDT 24
Peak memory 201640 kb
Host smart-4fb995c8-c9eb-4ad4-a8cf-a5fe6f23c1c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418744934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.3418744934
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3688276647
Short name T847
Test name
Test status
Simulation time 8794245439 ps
CPU time 8.34 seconds
Started Jun 25 05:51:36 PM PDT 24
Finished Jun 25 05:51:45 PM PDT 24
Peak memory 201824 kb
Host smart-34958d35-f68f-46c7-96b0-6cf3a04af89a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688276647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3688276647
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3279517136
Short name T875
Test name
Test status
Simulation time 538235119 ps
CPU time 1.41 seconds
Started Jun 25 05:51:37 PM PDT 24
Finished Jun 25 05:51:40 PM PDT 24
Peak memory 201552 kb
Host smart-6f904949-f618-409d-9fd6-8053a2e78e1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279517136 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3279517136
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2852707799
Short name T919
Test name
Test status
Simulation time 419150877 ps
CPU time 1.26 seconds
Started Jun 25 05:51:38 PM PDT 24
Finished Jun 25 05:51:40 PM PDT 24
Peak memory 201476 kb
Host smart-f9b30708-396c-490b-9e54-65a3a24fb9b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852707799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.2852707799
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.337656050
Short name T887
Test name
Test status
Simulation time 443874479 ps
CPU time 1.58 seconds
Started Jun 25 05:51:34 PM PDT 24
Finished Jun 25 05:51:37 PM PDT 24
Peak memory 201440 kb
Host smart-9f890bf9-6bc6-429e-9e3f-1e38985016e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337656050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.337656050
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2562129774
Short name T70
Test name
Test status
Simulation time 4585182922 ps
CPU time 1.85 seconds
Started Jun 25 05:51:37 PM PDT 24
Finished Jun 25 05:51:41 PM PDT 24
Peak memory 201864 kb
Host smart-6f619099-21f3-40e4-8d26-1c73431bdd44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562129774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2562129774
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1455373487
Short name T898
Test name
Test status
Simulation time 594866337 ps
CPU time 2.32 seconds
Started Jun 25 05:51:37 PM PDT 24
Finished Jun 25 05:51:41 PM PDT 24
Peak memory 218144 kb
Host smart-ce00d605-97a3-4aa2-8b3d-3ebdbca57a19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455373487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1455373487
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3321129019
Short name T876
Test name
Test status
Simulation time 4490751351 ps
CPU time 10.98 seconds
Started Jun 25 05:51:36 PM PDT 24
Finished Jun 25 05:51:48 PM PDT 24
Peak memory 201756 kb
Host smart-f02f8b5a-75cd-432c-bd19-ab66b05b8c96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321129019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3321129019
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3940140635
Short name T810
Test name
Test status
Simulation time 562246040 ps
CPU time 2.26 seconds
Started Jun 25 05:51:33 PM PDT 24
Finished Jun 25 05:51:37 PM PDT 24
Peak memory 201600 kb
Host smart-a4d2d398-ef7a-4ce9-96c6-f7a499166d77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940140635 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3940140635
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1476484904
Short name T145
Test name
Test status
Simulation time 621801541 ps
CPU time 0.96 seconds
Started Jun 25 05:51:34 PM PDT 24
Finished Jun 25 05:51:37 PM PDT 24
Peak memory 201508 kb
Host smart-73a1be34-a4ee-498e-be82-58b8743b22ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476484904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1476484904
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1573104807
Short name T837
Test name
Test status
Simulation time 445590778 ps
CPU time 1.67 seconds
Started Jun 25 05:51:33 PM PDT 24
Finished Jun 25 05:51:35 PM PDT 24
Peak memory 201456 kb
Host smart-571984e0-b796-4c32-bea5-48d39d88f656
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573104807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.1573104807
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.4231080535
Short name T828
Test name
Test status
Simulation time 4456021770 ps
CPU time 3.76 seconds
Started Jun 25 05:51:35 PM PDT 24
Finished Jun 25 05:51:41 PM PDT 24
Peak memory 201828 kb
Host smart-1a2f0a3b-4fc4-4888-b8f7-1f693f84595c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231080535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.4231080535
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1019050431
Short name T838
Test name
Test status
Simulation time 472955598 ps
CPU time 2.65 seconds
Started Jun 25 05:51:35 PM PDT 24
Finished Jun 25 05:51:39 PM PDT 24
Peak memory 201812 kb
Host smart-4c272a20-7fdc-4821-8482-a5e0ae452c65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019050431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1019050431
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1645890022
Short name T877
Test name
Test status
Simulation time 8222699260 ps
CPU time 21.84 seconds
Started Jun 25 05:51:38 PM PDT 24
Finished Jun 25 05:52:01 PM PDT 24
Peak memory 201824 kb
Host smart-83bbea8c-ef4d-44f9-912a-f5a754572f96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645890022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.1645890022
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.673852667
Short name T826
Test name
Test status
Simulation time 659048611 ps
CPU time 2.36 seconds
Started Jun 25 05:51:40 PM PDT 24
Finished Jun 25 05:51:43 PM PDT 24
Peak memory 201576 kb
Host smart-16210194-a919-4129-ac6e-e42ac2d87e60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673852667 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.673852667
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2041319680
Short name T868
Test name
Test status
Simulation time 393713176 ps
CPU time 1.07 seconds
Started Jun 25 05:51:36 PM PDT 24
Finished Jun 25 05:51:39 PM PDT 24
Peak memory 201476 kb
Host smart-caa4f273-74f4-4bc9-be5d-6a47cf00f59d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041319680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2041319680
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.4204340114
Short name T795
Test name
Test status
Simulation time 450424671 ps
CPU time 0.87 seconds
Started Jun 25 05:51:38 PM PDT 24
Finished Jun 25 05:51:40 PM PDT 24
Peak memory 201432 kb
Host smart-ac39d381-dd88-418a-9618-4076fbc1141e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204340114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.4204340114
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1005398065
Short name T857
Test name
Test status
Simulation time 4159558335 ps
CPU time 10 seconds
Started Jun 25 05:51:51 PM PDT 24
Finished Jun 25 05:52:03 PM PDT 24
Peak memory 202064 kb
Host smart-db196075-204d-4c4f-aa00-1dd43fd0fce9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005398065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1005398065
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1780492100
Short name T855
Test name
Test status
Simulation time 614298558 ps
CPU time 1.87 seconds
Started Jun 25 05:51:35 PM PDT 24
Finished Jun 25 05:51:38 PM PDT 24
Peak memory 209988 kb
Host smart-7ee04f09-88f0-456b-8614-df762f44e122
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780492100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1780492100
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.292716198
Short name T910
Test name
Test status
Simulation time 4448856868 ps
CPU time 11.62 seconds
Started Jun 25 05:51:34 PM PDT 24
Finished Jun 25 05:51:47 PM PDT 24
Peak memory 201836 kb
Host smart-094fff99-ea97-4b81-aba0-3570eafb14e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292716198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_in
tg_err.292716198
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.495346487
Short name T888
Test name
Test status
Simulation time 459009734 ps
CPU time 1.7 seconds
Started Jun 25 05:51:40 PM PDT 24
Finished Jun 25 05:51:42 PM PDT 24
Peak memory 201596 kb
Host smart-dbb40936-9d55-4a0e-8fcb-6d2e2b76daf3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495346487 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.495346487
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1129843513
Short name T905
Test name
Test status
Simulation time 326842670 ps
CPU time 1.13 seconds
Started Jun 25 05:51:41 PM PDT 24
Finished Jun 25 05:51:43 PM PDT 24
Peak memory 201508 kb
Host smart-5be2b099-54de-4a68-bdca-05d549d51d72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129843513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.1129843513
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1852262545
Short name T796
Test name
Test status
Simulation time 355947331 ps
CPU time 1.43 seconds
Started Jun 25 05:51:41 PM PDT 24
Finished Jun 25 05:51:44 PM PDT 24
Peak memory 201448 kb
Host smart-7411e44e-0e9c-4bea-89e1-2040a2a339ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852262545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1852262545
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.879120636
Short name T841
Test name
Test status
Simulation time 4170831271 ps
CPU time 5.61 seconds
Started Jun 25 05:51:42 PM PDT 24
Finished Jun 25 05:51:49 PM PDT 24
Peak memory 201872 kb
Host smart-fc267f24-2063-44eb-9288-b7694e0af3a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879120636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c
trl_same_csr_outstanding.879120636
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3104561598
Short name T829
Test name
Test status
Simulation time 378093829 ps
CPU time 2.49 seconds
Started Jun 25 05:51:41 PM PDT 24
Finished Jun 25 05:51:44 PM PDT 24
Peak memory 201784 kb
Host smart-1b009cc1-8628-4e63-8fe7-1cf56fa2b149
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104561598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3104561598
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.4279885004
Short name T865
Test name
Test status
Simulation time 8231165354 ps
CPU time 6.68 seconds
Started Jun 25 05:51:46 PM PDT 24
Finished Jun 25 05:51:54 PM PDT 24
Peak memory 201828 kb
Host smart-9d31d5f5-4799-4897-b3ad-8b6fbb7fd678
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279885004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.4279885004
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1802279974
Short name T836
Test name
Test status
Simulation time 594887133 ps
CPU time 1.4 seconds
Started Jun 25 05:51:42 PM PDT 24
Finished Jun 25 05:51:45 PM PDT 24
Peak memory 201572 kb
Host smart-4ad653ca-face-4dfb-bd87-22b36aa8d9dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802279974 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.1802279974
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1512541000
Short name T843
Test name
Test status
Simulation time 530731783 ps
CPU time 0.88 seconds
Started Jun 25 05:51:41 PM PDT 24
Finished Jun 25 05:51:43 PM PDT 24
Peak memory 201504 kb
Host smart-7b8e4b7f-4886-4768-8068-3ed23f63e821
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512541000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1512541000
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.165686768
Short name T850
Test name
Test status
Simulation time 442212168 ps
CPU time 0.91 seconds
Started Jun 25 05:51:45 PM PDT 24
Finished Jun 25 05:51:46 PM PDT 24
Peak memory 201440 kb
Host smart-4f640a6b-a7a1-416f-9c0e-c62cfc8994c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165686768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.165686768
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3466325534
Short name T920
Test name
Test status
Simulation time 4539366405 ps
CPU time 17.47 seconds
Started Jun 25 05:51:40 PM PDT 24
Finished Jun 25 05:51:59 PM PDT 24
Peak memory 201844 kb
Host smart-95635cff-bc85-4ad0-ad83-8f2e8ea42891
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466325534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.3466325534
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1131599841
Short name T832
Test name
Test status
Simulation time 1242693081 ps
CPU time 2.84 seconds
Started Jun 25 05:51:40 PM PDT 24
Finished Jun 25 05:51:44 PM PDT 24
Peak memory 210016 kb
Host smart-ed66e3ba-05a6-48a1-8c52-8568b587bb07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131599841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1131599841
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.4188928058
Short name T91
Test name
Test status
Simulation time 4171493028 ps
CPU time 11.5 seconds
Started Jun 25 05:51:44 PM PDT 24
Finished Jun 25 05:51:56 PM PDT 24
Peak memory 201864 kb
Host smart-62fd1dd1-9c2b-466a-ba0f-d962420f374f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188928058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.4188928058
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.69508540
Short name T873
Test name
Test status
Simulation time 523390934 ps
CPU time 1.94 seconds
Started Jun 25 05:51:46 PM PDT 24
Finished Jun 25 05:51:49 PM PDT 24
Peak memory 201388 kb
Host smart-a032005c-c1cc-4004-b726-9a5a71eead26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69508540 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.69508540
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.67998375
Short name T135
Test name
Test status
Simulation time 428166153 ps
CPU time 1.23 seconds
Started Jun 25 05:51:42 PM PDT 24
Finished Jun 25 05:51:45 PM PDT 24
Peak memory 201540 kb
Host smart-a429a51c-4133-4a29-8091-5f021979e8f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67998375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.67998375
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2209959270
Short name T879
Test name
Test status
Simulation time 400329419 ps
CPU time 0.75 seconds
Started Jun 25 05:51:42 PM PDT 24
Finished Jun 25 05:51:44 PM PDT 24
Peak memory 201280 kb
Host smart-12cc7717-1bc9-417b-a89e-56987cfe8158
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209959270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2209959270
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1089234935
Short name T147
Test name
Test status
Simulation time 2464872066 ps
CPU time 6.29 seconds
Started Jun 25 05:51:48 PM PDT 24
Finished Jun 25 05:51:55 PM PDT 24
Peak memory 201880 kb
Host smart-1aff897a-557c-417d-ac9d-daa737757dbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089234935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.1089234935
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.145719418
Short name T854
Test name
Test status
Simulation time 443501862 ps
CPU time 1.71 seconds
Started Jun 25 05:51:41 PM PDT 24
Finished Jun 25 05:51:43 PM PDT 24
Peak memory 201820 kb
Host smart-8d8f3ec7-31c1-4b0c-a1c3-49d6c945ac3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145719418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.145719418
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3835139670
Short name T821
Test name
Test status
Simulation time 4036051996 ps
CPU time 6.32 seconds
Started Jun 25 05:51:40 PM PDT 24
Finished Jun 25 05:51:47 PM PDT 24
Peak memory 201832 kb
Host smart-5eff90e6-3f6c-43bc-a004-6a63a2ed3b45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835139670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.3835139670
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1243306479
Short name T92
Test name
Test status
Simulation time 495906322 ps
CPU time 1.35 seconds
Started Jun 25 05:51:42 PM PDT 24
Finished Jun 25 05:51:44 PM PDT 24
Peak memory 201520 kb
Host smart-c6e71456-60ea-4469-8297-c598ad024355
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243306479 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1243306479
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.509521484
Short name T134
Test name
Test status
Simulation time 506092792 ps
CPU time 0.87 seconds
Started Jun 25 05:51:42 PM PDT 24
Finished Jun 25 05:51:44 PM PDT 24
Peak memory 201496 kb
Host smart-cee991e0-de74-4704-a682-e54501bb6cfb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509521484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.509521484
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1025052086
Short name T827
Test name
Test status
Simulation time 511690502 ps
CPU time 0.92 seconds
Started Jun 25 05:51:42 PM PDT 24
Finished Jun 25 05:51:44 PM PDT 24
Peak memory 201236 kb
Host smart-9a68ef8c-1ce1-4d72-ae0c-4c5d0110d854
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025052086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1025052086
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.261893232
Short name T848
Test name
Test status
Simulation time 2854113547 ps
CPU time 2.24 seconds
Started Jun 25 05:51:53 PM PDT 24
Finished Jun 25 05:51:58 PM PDT 24
Peak memory 201636 kb
Host smart-30545f72-e5cf-496b-9591-bdb08b3e50e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261893232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.261893232
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3691887257
Short name T88
Test name
Test status
Simulation time 323293055 ps
CPU time 2.05 seconds
Started Jun 25 05:51:42 PM PDT 24
Finished Jun 25 05:51:45 PM PDT 24
Peak memory 201828 kb
Host smart-2cecda7f-111f-4841-ba71-8a3517133392
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691887257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3691887257
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.163713684
Short name T73
Test name
Test status
Simulation time 9183765632 ps
CPU time 7.86 seconds
Started Jun 25 05:51:45 PM PDT 24
Finished Jun 25 05:51:53 PM PDT 24
Peak memory 201848 kb
Host smart-d35f1021-22c4-4937-b052-ff10a8816515
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163713684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_in
tg_err.163713684
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1828433817
Short name T914
Test name
Test status
Simulation time 1025664988 ps
CPU time 4.93 seconds
Started Jun 25 05:51:24 PM PDT 24
Finished Jun 25 05:51:31 PM PDT 24
Peak memory 201724 kb
Host smart-1eaf5d30-2dc8-444f-a5ee-ee4027ffa7be
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828433817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.1828433817
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3765000122
Short name T911
Test name
Test status
Simulation time 23239731365 ps
CPU time 92.86 seconds
Started Jun 25 05:51:25 PM PDT 24
Finished Jun 25 05:53:00 PM PDT 24
Peak memory 201824 kb
Host smart-be0e1b92-27e6-4b67-94fe-360795106791
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765000122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.3765000122
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2626350214
Short name T132
Test name
Test status
Simulation time 1250580382 ps
CPU time 2.38 seconds
Started Jun 25 05:51:28 PM PDT 24
Finished Jun 25 05:51:32 PM PDT 24
Peak memory 201500 kb
Host smart-d9b2b4ce-5762-4667-980c-4cef79744b9f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626350214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.2626350214
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.4024258573
Short name T824
Test name
Test status
Simulation time 473855853 ps
CPU time 1.83 seconds
Started Jun 25 05:51:25 PM PDT 24
Finished Jun 25 05:51:29 PM PDT 24
Peak memory 201576 kb
Host smart-83ef0224-0f00-456d-8c35-7ecab0137c78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024258573 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.4024258573
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1177191717
Short name T834
Test name
Test status
Simulation time 333865177 ps
CPU time 1.65 seconds
Started Jun 25 05:51:28 PM PDT 24
Finished Jun 25 05:51:31 PM PDT 24
Peak memory 201512 kb
Host smart-dd9322aa-6083-479e-88cb-5180a7498743
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177191717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1177191717
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.4200600237
Short name T801
Test name
Test status
Simulation time 437730273 ps
CPU time 0.89 seconds
Started Jun 25 05:51:25 PM PDT 24
Finished Jun 25 05:51:27 PM PDT 24
Peak memory 201292 kb
Host smart-3e243df9-b350-4ee8-b3bd-6c6c6b006cd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200600237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.4200600237
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2471067003
Short name T902
Test name
Test status
Simulation time 2065669213 ps
CPU time 3.88 seconds
Started Jun 25 05:51:31 PM PDT 24
Finished Jun 25 05:51:36 PM PDT 24
Peak memory 201524 kb
Host smart-6dff8a64-e530-4dc0-9ef9-efd8b7c5f445
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471067003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.2471067003
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2643759435
Short name T894
Test name
Test status
Simulation time 481901757 ps
CPU time 3.63 seconds
Started Jun 25 05:51:23 PM PDT 24
Finished Jun 25 05:51:28 PM PDT 24
Peak memory 201816 kb
Host smart-4fccd9e8-b674-492a-8d1d-2fea7262da61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643759435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2643759435
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3519718371
Short name T883
Test name
Test status
Simulation time 4748628951 ps
CPU time 4.43 seconds
Started Jun 25 05:51:28 PM PDT 24
Finished Jun 25 05:51:34 PM PDT 24
Peak memory 201852 kb
Host smart-0d7660f2-8cf8-492b-92da-523541d1cd2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519718371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.3519718371
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.552958198
Short name T909
Test name
Test status
Simulation time 389777716 ps
CPU time 1.52 seconds
Started Jun 25 05:51:42 PM PDT 24
Finished Jun 25 05:51:44 PM PDT 24
Peak memory 201456 kb
Host smart-d36fe239-0578-41c9-b286-a85375ce51e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552958198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.552958198
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1513616809
Short name T858
Test name
Test status
Simulation time 349138896 ps
CPU time 0.84 seconds
Started Jun 25 05:51:46 PM PDT 24
Finished Jun 25 05:51:48 PM PDT 24
Peak memory 201360 kb
Host smart-7171a724-0fac-4f57-8af6-57507a6de8a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513616809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1513616809
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3303865167
Short name T831
Test name
Test status
Simulation time 554975632 ps
CPU time 0.92 seconds
Started Jun 25 05:51:53 PM PDT 24
Finished Jun 25 05:51:56 PM PDT 24
Peak memory 201436 kb
Host smart-a233086a-e495-4abf-bb62-1f883381885b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303865167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.3303865167
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2076108542
Short name T851
Test name
Test status
Simulation time 348256599 ps
CPU time 1.46 seconds
Started Jun 25 05:51:40 PM PDT 24
Finished Jun 25 05:51:43 PM PDT 24
Peak memory 201372 kb
Host smart-036c6664-eaab-4f5b-a7ac-92518ad77d19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076108542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.2076108542
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1721045268
Short name T891
Test name
Test status
Simulation time 469556713 ps
CPU time 1.66 seconds
Started Jun 25 05:51:46 PM PDT 24
Finished Jun 25 05:51:49 PM PDT 24
Peak memory 201436 kb
Host smart-7217eb9b-b30f-47dc-b523-87acdcb9a89e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721045268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.1721045268
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3286164699
Short name T812
Test name
Test status
Simulation time 290383323 ps
CPU time 1.22 seconds
Started Jun 25 05:51:46 PM PDT 24
Finished Jun 25 05:51:49 PM PDT 24
Peak memory 201300 kb
Host smart-e15695c7-580e-4676-9f67-f2aee0e3c042
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286164699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.3286164699
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2670968644
Short name T797
Test name
Test status
Simulation time 448716394 ps
CPU time 1.71 seconds
Started Jun 25 05:51:42 PM PDT 24
Finished Jun 25 05:51:44 PM PDT 24
Peak memory 201460 kb
Host smart-de0612b3-0618-4406-ac96-d292501d9bac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670968644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2670968644
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.14779873
Short name T899
Test name
Test status
Simulation time 455984105 ps
CPU time 1.62 seconds
Started Jun 25 05:51:42 PM PDT 24
Finished Jun 25 05:51:45 PM PDT 24
Peak memory 201424 kb
Host smart-41b7b11b-762b-40fa-87ba-90a6d14d2aa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14779873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.14779873
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2687180296
Short name T806
Test name
Test status
Simulation time 450271562 ps
CPU time 0.92 seconds
Started Jun 25 05:51:42 PM PDT 24
Finished Jun 25 05:51:44 PM PDT 24
Peak memory 201376 kb
Host smart-4a1b8a1b-e873-4394-b26b-2c5d0079ea4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687180296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2687180296
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1758699365
Short name T908
Test name
Test status
Simulation time 425885622 ps
CPU time 0.89 seconds
Started Jun 25 05:51:42 PM PDT 24
Finished Jun 25 05:51:44 PM PDT 24
Peak memory 201392 kb
Host smart-119c9c66-1fd3-4cfc-a15c-f2eb63fb678c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758699365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1758699365
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1203175661
Short name T141
Test name
Test status
Simulation time 852169714 ps
CPU time 1.67 seconds
Started Jun 25 05:51:26 PM PDT 24
Finished Jun 25 05:51:29 PM PDT 24
Peak memory 201752 kb
Host smart-fa1dfda3-f4fb-44ae-bd7f-38ca675f0c58
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203175661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.1203175661
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1483579993
Short name T139
Test name
Test status
Simulation time 1309460305 ps
CPU time 5.07 seconds
Started Jun 25 05:51:23 PM PDT 24
Finished Jun 25 05:51:30 PM PDT 24
Peak memory 201696 kb
Host smart-404693a6-930b-461e-83a0-06cda713dce1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483579993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.1483579993
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.4274701845
Short name T136
Test name
Test status
Simulation time 1059642221 ps
CPU time 0.86 seconds
Started Jun 25 05:51:26 PM PDT 24
Finished Jun 25 05:51:29 PM PDT 24
Peak memory 201460 kb
Host smart-63d675a4-49fd-4193-9043-7bac5b260903
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274701845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.4274701845
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2942512266
Short name T84
Test name
Test status
Simulation time 443677839 ps
CPU time 1.95 seconds
Started Jun 25 05:51:27 PM PDT 24
Finished Jun 25 05:51:31 PM PDT 24
Peak memory 201572 kb
Host smart-8a1c49dd-0f99-45fb-92c3-5fba90f6285d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942512266 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.2942512266
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.184767779
Short name T131
Test name
Test status
Simulation time 350937550 ps
CPU time 0.9 seconds
Started Jun 25 05:51:28 PM PDT 24
Finished Jun 25 05:51:31 PM PDT 24
Peak memory 201516 kb
Host smart-f84ad438-c1cb-430b-a070-379825860074
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184767779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.184767779
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2358165069
Short name T805
Test name
Test status
Simulation time 532419158 ps
CPU time 1.31 seconds
Started Jun 25 05:51:26 PM PDT 24
Finished Jun 25 05:51:29 PM PDT 24
Peak memory 201440 kb
Host smart-e22fa27b-2b69-46b2-8d03-ec9df0e67aae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358165069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2358165069
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2001449064
Short name T885
Test name
Test status
Simulation time 4375931674 ps
CPU time 7.17 seconds
Started Jun 25 05:51:26 PM PDT 24
Finished Jun 25 05:51:35 PM PDT 24
Peak memory 201812 kb
Host smart-3fe77111-a237-4330-92aa-e7e6dbf652a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001449064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2001449064
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.196842146
Short name T833
Test name
Test status
Simulation time 640865505 ps
CPU time 3.16 seconds
Started Jun 25 05:51:24 PM PDT 24
Finished Jun 25 05:51:29 PM PDT 24
Peak memory 218076 kb
Host smart-e193bb59-53f8-4d79-979b-3b7e738c5eed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196842146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.196842146
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.352349839
Short name T912
Test name
Test status
Simulation time 4275335959 ps
CPU time 11.15 seconds
Started Jun 25 05:51:24 PM PDT 24
Finished Jun 25 05:51:37 PM PDT 24
Peak memory 201888 kb
Host smart-3ee2cf4d-c7f9-4949-b2ce-c0ffead1e874
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352349839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_int
g_err.352349839
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3350549243
Short name T907
Test name
Test status
Simulation time 420366160 ps
CPU time 1.59 seconds
Started Jun 25 05:51:43 PM PDT 24
Finished Jun 25 05:51:46 PM PDT 24
Peak memory 201680 kb
Host smart-6f490136-c7b7-4a16-88b6-e12f86305868
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350549243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.3350549243
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3979626570
Short name T845
Test name
Test status
Simulation time 403967715 ps
CPU time 1.1 seconds
Started Jun 25 05:51:41 PM PDT 24
Finished Jun 25 05:51:44 PM PDT 24
Peak memory 201460 kb
Host smart-cf514808-50e3-4ff9-abb8-d18e9b7aafa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979626570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3979626570
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2163220057
Short name T870
Test name
Test status
Simulation time 451023117 ps
CPU time 1.08 seconds
Started Jun 25 05:51:49 PM PDT 24
Finished Jun 25 05:51:51 PM PDT 24
Peak memory 201436 kb
Host smart-cd19dd69-d4fa-40fe-80d9-37c90b87d20e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163220057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.2163220057
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3238798625
Short name T813
Test name
Test status
Simulation time 505075511 ps
CPU time 1.27 seconds
Started Jun 25 05:51:53 PM PDT 24
Finished Jun 25 05:51:57 PM PDT 24
Peak memory 201428 kb
Host smart-d15d8035-3573-4200-ac99-98c70e8b90f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238798625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3238798625
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1114369947
Short name T799
Test name
Test status
Simulation time 476046657 ps
CPU time 1.74 seconds
Started Jun 25 05:51:50 PM PDT 24
Finished Jun 25 05:51:53 PM PDT 24
Peak memory 201452 kb
Host smart-5e1bf0e6-bd52-4365-8f39-917260477163
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114369947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1114369947
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.4124369178
Short name T862
Test name
Test status
Simulation time 467305491 ps
CPU time 0.89 seconds
Started Jun 25 05:51:51 PM PDT 24
Finished Jun 25 05:51:54 PM PDT 24
Peak memory 201376 kb
Host smart-45c49a8f-456b-410e-8da1-29bae87972d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124369178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.4124369178
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3339908085
Short name T800
Test name
Test status
Simulation time 476656702 ps
CPU time 1.04 seconds
Started Jun 25 05:51:50 PM PDT 24
Finished Jun 25 05:51:53 PM PDT 24
Peak memory 201412 kb
Host smart-1e717fc8-bde8-468b-889a-95ed61cf65d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339908085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3339908085
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1631506323
Short name T906
Test name
Test status
Simulation time 438204984 ps
CPU time 1 seconds
Started Jun 25 05:51:50 PM PDT 24
Finished Jun 25 05:51:53 PM PDT 24
Peak memory 201292 kb
Host smart-07819065-2b14-451b-a9ef-6a9be55c1b69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631506323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.1631506323
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3549760102
Short name T872
Test name
Test status
Simulation time 358906504 ps
CPU time 0.83 seconds
Started Jun 25 05:51:50 PM PDT 24
Finished Jun 25 05:51:52 PM PDT 24
Peak memory 201432 kb
Host smart-19f60b90-1945-4dc8-b16e-17ab19898903
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549760102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3549760102
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1068971043
Short name T802
Test name
Test status
Simulation time 390357050 ps
CPU time 0.72 seconds
Started Jun 25 05:51:51 PM PDT 24
Finished Jun 25 05:51:53 PM PDT 24
Peak memory 201432 kb
Host smart-6d5a797a-43d4-4a10-a052-7f845752db91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068971043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.1068971043
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.770750041
Short name T130
Test name
Test status
Simulation time 1162745646 ps
CPU time 5.88 seconds
Started Jun 25 05:51:26 PM PDT 24
Finished Jun 25 05:51:33 PM PDT 24
Peak memory 201756 kb
Host smart-600b90ac-2862-46f2-bf78-5f706ddb5c26
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770750041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.770750041
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2835475431
Short name T918
Test name
Test status
Simulation time 17349202503 ps
CPU time 22.06 seconds
Started Jun 25 05:51:26 PM PDT 24
Finished Jun 25 05:51:50 PM PDT 24
Peak memory 201804 kb
Host smart-3331968a-e670-4ef9-874b-d272c7531aa1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835475431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2835475431
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1148311618
Short name T144
Test name
Test status
Simulation time 1116568367 ps
CPU time 2.02 seconds
Started Jun 25 05:51:24 PM PDT 24
Finished Jun 25 05:51:28 PM PDT 24
Peak memory 201516 kb
Host smart-2cdf6a59-6ba2-49a4-90b5-4e3d5c413ddc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148311618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.1148311618
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2179816577
Short name T823
Test name
Test status
Simulation time 388922824 ps
CPU time 1.66 seconds
Started Jun 25 05:51:25 PM PDT 24
Finished Jun 25 05:51:28 PM PDT 24
Peak memory 201568 kb
Host smart-0683cb1a-6f6a-4b0d-8f9f-53cc463dd375
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179816577 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2179816577
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3447182147
Short name T915
Test name
Test status
Simulation time 484567069 ps
CPU time 0.81 seconds
Started Jun 25 05:51:28 PM PDT 24
Finished Jun 25 05:51:30 PM PDT 24
Peak memory 201528 kb
Host smart-9ff1dc50-99e7-453f-8cbc-7767f32e7a1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447182147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3447182147
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.271074649
Short name T808
Test name
Test status
Simulation time 371972488 ps
CPU time 0.85 seconds
Started Jun 25 05:51:24 PM PDT 24
Finished Jun 25 05:51:27 PM PDT 24
Peak memory 201456 kb
Host smart-41e116aa-d38f-48d4-a149-851d4ff8e982
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271074649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.271074649
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3363318868
Short name T897
Test name
Test status
Simulation time 2407629516 ps
CPU time 5.63 seconds
Started Jun 25 05:51:28 PM PDT 24
Finished Jun 25 05:51:35 PM PDT 24
Peak memory 201640 kb
Host smart-9add6182-fb69-403d-b552-858c145273bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363318868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.3363318868
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3413682573
Short name T863
Test name
Test status
Simulation time 406614424 ps
CPU time 2 seconds
Started Jun 25 05:51:28 PM PDT 24
Finished Jun 25 05:51:32 PM PDT 24
Peak memory 201780 kb
Host smart-bdaf81aa-8b6a-4dba-b342-7cf190106a85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413682573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.3413682573
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1479334359
Short name T342
Test name
Test status
Simulation time 8533327999 ps
CPU time 23.09 seconds
Started Jun 25 05:51:27 PM PDT 24
Finished Jun 25 05:51:52 PM PDT 24
Peak memory 201812 kb
Host smart-dc77cc99-62d3-4ec0-8397-36605671ff43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479334359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.1479334359
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2549378540
Short name T853
Test name
Test status
Simulation time 451836065 ps
CPU time 1.7 seconds
Started Jun 25 05:51:52 PM PDT 24
Finished Jun 25 05:51:56 PM PDT 24
Peak memory 201456 kb
Host smart-5b4c7a51-bbe5-42fa-a381-9a27b4fddcb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549378540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.2549378540
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2711803320
Short name T886
Test name
Test status
Simulation time 465607357 ps
CPU time 1.74 seconds
Started Jun 25 05:51:54 PM PDT 24
Finished Jun 25 05:51:57 PM PDT 24
Peak memory 201360 kb
Host smart-b5b80b12-1f59-4ce0-946d-f6493180d525
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711803320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.2711803320
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3821485327
Short name T867
Test name
Test status
Simulation time 396048448 ps
CPU time 1.68 seconds
Started Jun 25 05:51:51 PM PDT 24
Finished Jun 25 05:51:55 PM PDT 24
Peak memory 201440 kb
Host smart-53d7643d-ff32-41d0-a359-299edbf87951
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821485327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.3821485327
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2720055281
Short name T871
Test name
Test status
Simulation time 430643544 ps
CPU time 0.88 seconds
Started Jun 25 05:51:52 PM PDT 24
Finished Jun 25 05:51:55 PM PDT 24
Peak memory 201448 kb
Host smart-3642f78a-cc49-4987-8af6-f6aa91a93e00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720055281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2720055281
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1497591484
Short name T842
Test name
Test status
Simulation time 495969849 ps
CPU time 0.87 seconds
Started Jun 25 05:51:52 PM PDT 24
Finished Jun 25 05:51:56 PM PDT 24
Peak memory 201424 kb
Host smart-1942f05f-6c02-4f73-9fc9-18130a4c0eb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497591484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1497591484
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2115553263
Short name T895
Test name
Test status
Simulation time 454933445 ps
CPU time 1.12 seconds
Started Jun 25 05:51:49 PM PDT 24
Finished Jun 25 05:51:51 PM PDT 24
Peak memory 201440 kb
Host smart-5afc4665-416b-4592-8be5-d24ddc651ad4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115553263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2115553263
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.4261098126
Short name T892
Test name
Test status
Simulation time 363496553 ps
CPU time 0.86 seconds
Started Jun 25 05:51:52 PM PDT 24
Finished Jun 25 05:51:55 PM PDT 24
Peak memory 201432 kb
Host smart-d5a9e328-b43e-445c-975d-42a2b1802556
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261098126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.4261098126
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1212784269
Short name T818
Test name
Test status
Simulation time 457571585 ps
CPU time 0.75 seconds
Started Jun 25 05:51:53 PM PDT 24
Finished Jun 25 05:51:56 PM PDT 24
Peak memory 201564 kb
Host smart-395a9443-9341-432f-a1ca-5aff348c036e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212784269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.1212784269
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2197021635
Short name T878
Test name
Test status
Simulation time 413228563 ps
CPU time 1.58 seconds
Started Jun 25 05:51:51 PM PDT 24
Finished Jun 25 05:51:54 PM PDT 24
Peak memory 201424 kb
Host smart-62fe231b-c926-4901-b63f-86288154fbf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197021635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2197021635
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2785876884
Short name T860
Test name
Test status
Simulation time 316258347 ps
CPU time 0.98 seconds
Started Jun 25 05:51:50 PM PDT 24
Finished Jun 25 05:51:53 PM PDT 24
Peak memory 201464 kb
Host smart-c6abbe9d-68e4-485c-a4a1-9a9949bfded2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785876884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2785876884
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1941928722
Short name T864
Test name
Test status
Simulation time 408857353 ps
CPU time 1.75 seconds
Started Jun 25 05:51:25 PM PDT 24
Finished Jun 25 05:51:28 PM PDT 24
Peak memory 201588 kb
Host smart-a6961352-d8c9-42b1-877b-865d17cefe16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941928722 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1941928722
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.848728560
Short name T869
Test name
Test status
Simulation time 445323856 ps
CPU time 1.72 seconds
Started Jun 25 05:51:30 PM PDT 24
Finished Jun 25 05:51:33 PM PDT 24
Peak memory 201524 kb
Host smart-7f068740-d1e5-4255-963d-fb7079fe1c64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848728560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.848728560
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1978009341
Short name T814
Test name
Test status
Simulation time 404989167 ps
CPU time 1.14 seconds
Started Jun 25 05:51:24 PM PDT 24
Finished Jun 25 05:51:27 PM PDT 24
Peak memory 201436 kb
Host smart-5704e2d7-7692-48dc-a128-fff234c844ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978009341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1978009341
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3258001369
Short name T896
Test name
Test status
Simulation time 4844953329 ps
CPU time 11.98 seconds
Started Jun 25 05:51:26 PM PDT 24
Finished Jun 25 05:51:39 PM PDT 24
Peak memory 201844 kb
Host smart-f8cc7815-5c62-40fb-bc7c-e25739916517
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258001369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3258001369
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.415263105
Short name T78
Test name
Test status
Simulation time 609236372 ps
CPU time 3.69 seconds
Started Jun 25 05:51:25 PM PDT 24
Finished Jun 25 05:51:31 PM PDT 24
Peak memory 209928 kb
Host smart-5700645a-3e2c-4458-86d1-65e19d39d82e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415263105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.415263105
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2297224100
Short name T75
Test name
Test status
Simulation time 8174022241 ps
CPU time 11.94 seconds
Started Jun 25 05:51:25 PM PDT 24
Finished Jun 25 05:51:39 PM PDT 24
Peak memory 201812 kb
Host smart-db649920-ef3a-4a60-8051-644a0678347b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297224100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.2297224100
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1593745310
Short name T809
Test name
Test status
Simulation time 593995045 ps
CPU time 1.16 seconds
Started Jun 25 05:51:24 PM PDT 24
Finished Jun 25 05:51:26 PM PDT 24
Peak memory 201568 kb
Host smart-5cd79d76-a554-4c17-a062-d375223726cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593745310 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1593745310
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3697250770
Short name T137
Test name
Test status
Simulation time 539716398 ps
CPU time 0.79 seconds
Started Jun 25 05:51:31 PM PDT 24
Finished Jun 25 05:51:33 PM PDT 24
Peak memory 201524 kb
Host smart-c1263c45-735e-479f-a8aa-195ad1258ae3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697250770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3697250770
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3812229294
Short name T884
Test name
Test status
Simulation time 512157858 ps
CPU time 0.91 seconds
Started Jun 25 05:51:25 PM PDT 24
Finished Jun 25 05:51:28 PM PDT 24
Peak memory 201440 kb
Host smart-37d800ee-5419-4b3e-87da-3866a2458b9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812229294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3812229294
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1142691708
Short name T149
Test name
Test status
Simulation time 2078610609 ps
CPU time 2.95 seconds
Started Jun 25 05:51:26 PM PDT 24
Finished Jun 25 05:51:31 PM PDT 24
Peak memory 201488 kb
Host smart-d1827c1f-c887-4cc0-8d72-1a6608f179c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142691708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.1142691708
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1262913397
Short name T82
Test name
Test status
Simulation time 378218912 ps
CPU time 3.05 seconds
Started Jun 25 05:51:27 PM PDT 24
Finished Jun 25 05:51:31 PM PDT 24
Peak memory 211040 kb
Host smart-2a4bc5f8-6ac8-46d9-8469-22471ba56d84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262913397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1262913397
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1772201265
Short name T846
Test name
Test status
Simulation time 8621737273 ps
CPU time 22.56 seconds
Started Jun 25 05:51:31 PM PDT 24
Finished Jun 25 05:51:54 PM PDT 24
Peak memory 201808 kb
Host smart-6f34f790-ab81-468f-9ffa-82ec51affe73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772201265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.1772201265
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2497917455
Short name T901
Test name
Test status
Simulation time 335989914 ps
CPU time 1.47 seconds
Started Jun 25 05:51:24 PM PDT 24
Finished Jun 25 05:51:27 PM PDT 24
Peak memory 201576 kb
Host smart-67551b50-bd40-436d-85af-1e7a36d74e61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497917455 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.2497917455
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1517379290
Short name T143
Test name
Test status
Simulation time 412223629 ps
CPU time 1.09 seconds
Started Jun 25 05:51:27 PM PDT 24
Finished Jun 25 05:51:29 PM PDT 24
Peak memory 201472 kb
Host smart-ea34e8f5-7bde-46ab-acc4-bddf01de202b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517379290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1517379290
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1957036335
Short name T807
Test name
Test status
Simulation time 342734678 ps
CPU time 0.84 seconds
Started Jun 25 05:51:28 PM PDT 24
Finished Jun 25 05:51:31 PM PDT 24
Peak memory 201428 kb
Host smart-95fcfb3a-b3de-40ac-8870-437d24ed54f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957036335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1957036335
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1524475085
Short name T904
Test name
Test status
Simulation time 5389751503 ps
CPU time 20.16 seconds
Started Jun 25 05:51:27 PM PDT 24
Finished Jun 25 05:51:49 PM PDT 24
Peak memory 201856 kb
Host smart-4c3d41fc-05ac-49d0-814b-4ac0fe1d34d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524475085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.1524475085
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2750009619
Short name T90
Test name
Test status
Simulation time 620922742 ps
CPU time 3.65 seconds
Started Jun 25 05:51:27 PM PDT 24
Finished Jun 25 05:51:32 PM PDT 24
Peak memory 209944 kb
Host smart-e37ac398-da79-42bc-b066-eaacd5de2486
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750009619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2750009619
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.906242589
Short name T835
Test name
Test status
Simulation time 448845642 ps
CPU time 1.35 seconds
Started Jun 25 05:51:34 PM PDT 24
Finished Jun 25 05:51:37 PM PDT 24
Peak memory 201424 kb
Host smart-41fe1979-24ea-43d9-9b4f-361d9d1386c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906242589 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.906242589
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2940277639
Short name T146
Test name
Test status
Simulation time 492857731 ps
CPU time 0.9 seconds
Started Jun 25 05:51:35 PM PDT 24
Finished Jun 25 05:51:37 PM PDT 24
Peak memory 201508 kb
Host smart-3ccb3e7a-a292-4be5-b7d5-82d4ac790d6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940277639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2940277639
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3318217679
Short name T839
Test name
Test status
Simulation time 373019875 ps
CPU time 0.97 seconds
Started Jun 25 05:51:35 PM PDT 24
Finished Jun 25 05:51:37 PM PDT 24
Peak memory 201436 kb
Host smart-ab84a799-a934-4ded-b651-86f800f5548d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318217679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3318217679
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3825038080
Short name T916
Test name
Test status
Simulation time 2645561335 ps
CPU time 8.04 seconds
Started Jun 25 05:51:34 PM PDT 24
Finished Jun 25 05:51:43 PM PDT 24
Peak memory 201620 kb
Host smart-46401815-693a-440a-851d-86bfc2fd771a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825038080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.3825038080
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.842835875
Short name T343
Test name
Test status
Simulation time 8788388965 ps
CPU time 4.99 seconds
Started Jun 25 05:51:26 PM PDT 24
Finished Jun 25 05:51:33 PM PDT 24
Peak memory 201848 kb
Host smart-3a97a37f-db29-46e8-9085-0ef65755ba25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842835875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_int
g_err.842835875
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2677511319
Short name T804
Test name
Test status
Simulation time 411680939 ps
CPU time 1.51 seconds
Started Jun 25 05:51:33 PM PDT 24
Finished Jun 25 05:51:36 PM PDT 24
Peak memory 201576 kb
Host smart-c627f240-d3d8-47ca-a50f-1154b60e468d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677511319 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.2677511319
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1102703840
Short name T890
Test name
Test status
Simulation time 508009483 ps
CPU time 2.04 seconds
Started Jun 25 05:51:33 PM PDT 24
Finished Jun 25 05:51:36 PM PDT 24
Peak memory 201524 kb
Host smart-ed0cb189-4516-4c3d-8348-e527f05bc6de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102703840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1102703840
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.247578343
Short name T798
Test name
Test status
Simulation time 561982868 ps
CPU time 1 seconds
Started Jun 25 05:51:37 PM PDT 24
Finished Jun 25 05:51:40 PM PDT 24
Peak memory 201416 kb
Host smart-8fd72084-8da5-448d-8341-42794a323f13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247578343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.247578343
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1904833814
Short name T148
Test name
Test status
Simulation time 1878029322 ps
CPU time 2.58 seconds
Started Jun 25 05:51:37 PM PDT 24
Finished Jun 25 05:51:42 PM PDT 24
Peak memory 201400 kb
Host smart-1831c05d-9dec-4639-a02e-b6400176018e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904833814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.1904833814
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1583912003
Short name T882
Test name
Test status
Simulation time 297144748 ps
CPU time 2.05 seconds
Started Jun 25 05:51:34 PM PDT 24
Finished Jun 25 05:51:37 PM PDT 24
Peak memory 201788 kb
Host smart-a456644e-733b-48a8-85b0-91f905217ad5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583912003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1583912003
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.669753472
Short name T820
Test name
Test status
Simulation time 4132161332 ps
CPU time 5.91 seconds
Started Jun 25 05:51:33 PM PDT 24
Finished Jun 25 05:51:40 PM PDT 24
Peak memory 201816 kb
Host smart-3e257a57-01eb-422a-977b-75a329a70149
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669753472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_int
g_err.669753472
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.709147156
Short name T530
Test name
Test status
Simulation time 339500438 ps
CPU time 1.01 seconds
Started Jun 25 05:51:50 PM PDT 24
Finished Jun 25 05:51:53 PM PDT 24
Peak memory 201624 kb
Host smart-8ad3a9ab-5f08-4cc7-becd-296deae47a98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709147156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.709147156
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.183620611
Short name T648
Test name
Test status
Simulation time 164556771653 ps
CPU time 5.08 seconds
Started Jun 25 05:51:51 PM PDT 24
Finished Jun 25 05:51:59 PM PDT 24
Peak memory 201852 kb
Host smart-366d8681-662a-4697-9bb4-004755f21aef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183620611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gatin
g.183620611
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3169804113
Short name T385
Test name
Test status
Simulation time 483794824522 ps
CPU time 598.33 seconds
Started Jun 25 05:51:55 PM PDT 24
Finished Jun 25 06:01:55 PM PDT 24
Peak memory 201836 kb
Host smart-7f00dbfd-c76c-487e-a831-7e2b84782624
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169804113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.3169804113
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.687199415
Short name T3
Test name
Test status
Simulation time 496210062804 ps
CPU time 294.26 seconds
Started Jun 25 05:51:51 PM PDT 24
Finished Jun 25 05:56:47 PM PDT 24
Peak memory 201944 kb
Host smart-d6612340-d328-442e-b719-8adc6cfa8420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687199415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.687199415
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2336626093
Short name T363
Test name
Test status
Simulation time 494628166665 ps
CPU time 244.54 seconds
Started Jun 25 05:51:54 PM PDT 24
Finished Jun 25 05:56:00 PM PDT 24
Peak memory 201872 kb
Host smart-92be5329-2cd8-4993-9ed9-5d28ad7f65ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336626093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2336626093
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1229554141
Short name T395
Test name
Test status
Simulation time 193446473044 ps
CPU time 441.88 seconds
Started Jun 25 05:51:54 PM PDT 24
Finished Jun 25 05:59:18 PM PDT 24
Peak memory 201860 kb
Host smart-d302dd21-1322-4a7a-9936-5ac77d28f0bb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229554141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.1229554141
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.2471786105
Short name T638
Test name
Test status
Simulation time 110522609515 ps
CPU time 373.3 seconds
Started Jun 25 05:51:52 PM PDT 24
Finished Jun 25 05:58:07 PM PDT 24
Peak memory 202244 kb
Host smart-99e1693a-db6d-4211-a924-6d4def8b7c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471786105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2471786105
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.1051197093
Short name T2
Test name
Test status
Simulation time 40677872789 ps
CPU time 77.08 seconds
Started Jun 25 05:51:51 PM PDT 24
Finished Jun 25 05:53:10 PM PDT 24
Peak memory 201652 kb
Host smart-31c9435f-9f05-480b-9d9c-463be7fbaa07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051197093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1051197093
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.2169642846
Short name T625
Test name
Test status
Simulation time 5242780498 ps
CPU time 15.18 seconds
Started Jun 25 05:51:50 PM PDT 24
Finished Jun 25 05:52:07 PM PDT 24
Peak memory 201664 kb
Host smart-f30bc9bf-1fcf-4bd4-abe9-ea382dbc8258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169642846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.2169642846
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1046547941
Short name T628
Test name
Test status
Simulation time 5605258617 ps
CPU time 14.88 seconds
Started Jun 25 05:51:51 PM PDT 24
Finished Jun 25 05:52:08 PM PDT 24
Peak memory 201652 kb
Host smart-a944f18d-2d93-4a3f-9f39-8ac8316882d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046547941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1046547941
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.4018571393
Short name T315
Test name
Test status
Simulation time 882814540825 ps
CPU time 766.41 seconds
Started Jun 25 05:51:51 PM PDT 24
Finished Jun 25 06:04:40 PM PDT 24
Peak memory 202088 kb
Host smart-2189806b-d809-4389-ab87-004cee4a5599
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018571393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
4018571393
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2553434919
Short name T17
Test name
Test status
Simulation time 312985747791 ps
CPU time 291.97 seconds
Started Jun 25 05:51:53 PM PDT 24
Finished Jun 25 05:56:48 PM PDT 24
Peak memory 210556 kb
Host smart-bd939148-2405-42df-a42b-54ac62409939
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553434919 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.2553434919
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.1862241823
Short name T700
Test name
Test status
Simulation time 506238319 ps
CPU time 1.11 seconds
Started Jun 25 05:51:54 PM PDT 24
Finished Jun 25 05:51:57 PM PDT 24
Peak memory 201616 kb
Host smart-8f148bb9-b316-43a9-b09d-fecf6a6f6ec1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862241823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.1862241823
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.2764479074
Short name T578
Test name
Test status
Simulation time 172529641501 ps
CPU time 102.96 seconds
Started Jun 25 05:51:51 PM PDT 24
Finished Jun 25 05:53:37 PM PDT 24
Peak memory 201876 kb
Host smart-35754f23-1243-4f7d-a5df-77b17b7771e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764479074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.2764479074
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1618470764
Short name T657
Test name
Test status
Simulation time 331217984833 ps
CPU time 737.01 seconds
Started Jun 25 05:51:55 PM PDT 24
Finished Jun 25 06:04:14 PM PDT 24
Peak memory 201836 kb
Host smart-6cf3e378-56cd-4f98-8e86-4b0fb2775149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618470764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1618470764
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1608494234
Short name T575
Test name
Test status
Simulation time 492039413075 ps
CPU time 176.36 seconds
Started Jun 25 05:51:51 PM PDT 24
Finished Jun 25 05:54:50 PM PDT 24
Peak memory 201860 kb
Host smart-aa085ab1-faff-4cab-904d-1cc7602bf062
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608494234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1608494234
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.891560153
Short name T30
Test name
Test status
Simulation time 328069864921 ps
CPU time 803.24 seconds
Started Jun 25 05:51:51 PM PDT 24
Finished Jun 25 06:05:16 PM PDT 24
Peak memory 201908 kb
Host smart-036fcd3f-6242-477f-b9a4-5db1486ae76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891560153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.891560153
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1897600750
Short name T436
Test name
Test status
Simulation time 166656024691 ps
CPU time 21.92 seconds
Started Jun 25 05:51:54 PM PDT 24
Finished Jun 25 05:52:18 PM PDT 24
Peak memory 201868 kb
Host smart-2b14623e-8f4f-439c-b38f-26dfd57fd0e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897600750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1897600750
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3337429917
Short name T543
Test name
Test status
Simulation time 183674342034 ps
CPU time 417.9 seconds
Started Jun 25 05:51:51 PM PDT 24
Finished Jun 25 05:58:51 PM PDT 24
Peak memory 201888 kb
Host smart-ebcffc38-a73d-42b3-a357-58a4ecfee408
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337429917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.3337429917
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1574535170
Short name T210
Test name
Test status
Simulation time 201740875044 ps
CPU time 222 seconds
Started Jun 25 05:51:50 PM PDT 24
Finished Jun 25 05:55:33 PM PDT 24
Peak memory 201772 kb
Host smart-dc59255a-1eca-43a0-bd3f-0f20c95e222d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574535170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1574535170
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2398741078
Short name T540
Test name
Test status
Simulation time 90325649391 ps
CPU time 335.89 seconds
Started Jun 25 05:51:50 PM PDT 24
Finished Jun 25 05:57:27 PM PDT 24
Peak memory 202184 kb
Host smart-b04b9aec-2994-48f1-b4de-543961a6cf3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398741078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2398741078
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.1465403040
Short name T534
Test name
Test status
Simulation time 43468760731 ps
CPU time 48.66 seconds
Started Jun 25 05:51:53 PM PDT 24
Finished Jun 25 05:52:44 PM PDT 24
Peak memory 201612 kb
Host smart-186e34c9-fa15-4f12-abf8-f8c17985171a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465403040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1465403040
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.3224807763
Short name T469
Test name
Test status
Simulation time 3732191766 ps
CPU time 5.08 seconds
Started Jun 25 05:51:51 PM PDT 24
Finished Jun 25 05:51:58 PM PDT 24
Peak memory 201672 kb
Host smart-01ffd7ef-6ea7-489c-90a3-9f416ef43214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224807763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3224807763
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.74648269
Short name T80
Test name
Test status
Simulation time 7574678338 ps
CPU time 3.19 seconds
Started Jun 25 05:51:51 PM PDT 24
Finished Jun 25 05:51:57 PM PDT 24
Peak memory 218252 kb
Host smart-977f0bb0-57c7-47ef-b575-1da63b4743b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74648269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.74648269
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.388670011
Short name T497
Test name
Test status
Simulation time 6058119479 ps
CPU time 14.6 seconds
Started Jun 25 05:51:55 PM PDT 24
Finished Jun 25 05:52:11 PM PDT 24
Peak memory 201440 kb
Host smart-515f9674-51b1-4e4d-8568-eae13ae5d16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388670011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.388670011
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.2511099632
Short name T29
Test name
Test status
Simulation time 173037644014 ps
CPU time 98.33 seconds
Started Jun 25 05:51:53 PM PDT 24
Finished Jun 25 05:53:34 PM PDT 24
Peak memory 201876 kb
Host smart-ed0d7289-877d-4132-a772-e90f1b77486f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511099632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
2511099632
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3577672494
Short name T177
Test name
Test status
Simulation time 325824547484 ps
CPU time 95.72 seconds
Started Jun 25 05:51:50 PM PDT 24
Finished Jun 25 05:53:28 PM PDT 24
Peak memory 201980 kb
Host smart-28b3be27-70e3-4312-b492-bdbbbad05744
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577672494 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3577672494
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.3971911266
Short name T771
Test name
Test status
Simulation time 398743630 ps
CPU time 0.86 seconds
Started Jun 25 05:52:17 PM PDT 24
Finished Jun 25 05:52:19 PM PDT 24
Peak memory 201616 kb
Host smart-fe48c79f-6f94-46a8-acf8-658399998620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971911266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3971911266
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.2191150056
Short name T59
Test name
Test status
Simulation time 351970791458 ps
CPU time 768.03 seconds
Started Jun 25 05:52:15 PM PDT 24
Finished Jun 25 06:05:04 PM PDT 24
Peak memory 201872 kb
Host smart-d013bb78-58e4-497a-b821-74245cf512c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191150056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.2191150056
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3872173357
Short name T44
Test name
Test status
Simulation time 327639168458 ps
CPU time 194.56 seconds
Started Jun 25 05:52:18 PM PDT 24
Finished Jun 25 05:55:35 PM PDT 24
Peak memory 201860 kb
Host smart-a867f849-524a-4090-98da-b1d1b908a30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872173357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3872173357
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.3733655223
Short name T464
Test name
Test status
Simulation time 165370892826 ps
CPU time 387.96 seconds
Started Jun 25 05:52:18 PM PDT 24
Finished Jun 25 05:58:48 PM PDT 24
Peak memory 201824 kb
Host smart-6eaeb79f-3c5f-483a-bef7-36e7596c36bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733655223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.3733655223
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.1896194493
Short name T154
Test name
Test status
Simulation time 484701976912 ps
CPU time 269.58 seconds
Started Jun 25 05:52:19 PM PDT 24
Finished Jun 25 05:56:51 PM PDT 24
Peak memory 201864 kb
Host smart-755184d6-ebe5-46e0-927a-5ecc9230cc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896194493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.1896194493
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3582221634
Short name T581
Test name
Test status
Simulation time 329856505278 ps
CPU time 747.74 seconds
Started Jun 25 05:52:17 PM PDT 24
Finished Jun 25 06:04:46 PM PDT 24
Peak memory 201876 kb
Host smart-0d654dce-ec09-4309-bc17-30edc1652470
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582221634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.3582221634
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1249978546
Short name T271
Test name
Test status
Simulation time 177226139155 ps
CPU time 209.84 seconds
Started Jun 25 05:52:17 PM PDT 24
Finished Jun 25 05:55:48 PM PDT 24
Peak memory 201928 kb
Host smart-62938d34-a026-42f8-a3fe-a4d13d21eba0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249978546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1249978546
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.683480944
Short name T354
Test name
Test status
Simulation time 83819170382 ps
CPU time 436.69 seconds
Started Jun 25 05:52:21 PM PDT 24
Finished Jun 25 05:59:39 PM PDT 24
Peak memory 202180 kb
Host smart-3d550680-10ff-491b-b422-e227099f95c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683480944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.683480944
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.3280200989
Short name T774
Test name
Test status
Simulation time 28524111587 ps
CPU time 13.47 seconds
Started Jun 25 05:52:18 PM PDT 24
Finished Jun 25 05:52:34 PM PDT 24
Peak memory 201660 kb
Host smart-df388f97-0fad-4878-9d10-6a324c3c096c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280200989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.3280200989
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.155217227
Short name T443
Test name
Test status
Simulation time 3301147953 ps
CPU time 2.83 seconds
Started Jun 25 05:52:19 PM PDT 24
Finished Jun 25 05:52:24 PM PDT 24
Peak memory 201680 kb
Host smart-f2eab783-3ab1-459f-8e1c-ae912b51fae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155217227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.155217227
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3097702178
Short name T516
Test name
Test status
Simulation time 5941551036 ps
CPU time 4.6 seconds
Started Jun 25 05:52:16 PM PDT 24
Finished Jun 25 05:52:21 PM PDT 24
Peak memory 201692 kb
Host smart-3c5afac6-6daa-43ca-849a-9de33b37d208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097702178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3097702178
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.2759321768
Short name T201
Test name
Test status
Simulation time 358425097582 ps
CPU time 743.37 seconds
Started Jun 25 05:52:17 PM PDT 24
Finished Jun 25 06:04:42 PM PDT 24
Peak memory 201912 kb
Host smart-82a57ae0-4065-4e55-af87-3e962428c733
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759321768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.2759321768
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2739760242
Short name T26
Test name
Test status
Simulation time 43587889266 ps
CPU time 92.42 seconds
Started Jun 25 05:52:18 PM PDT 24
Finished Jun 25 05:53:53 PM PDT 24
Peak memory 202236 kb
Host smart-f0ae2109-a5da-4324-89e6-d86092308150
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739760242 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.2739760242
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.2506649401
Short name T697
Test name
Test status
Simulation time 406860280 ps
CPU time 1.55 seconds
Started Jun 25 05:52:17 PM PDT 24
Finished Jun 25 05:52:21 PM PDT 24
Peak memory 201616 kb
Host smart-59bf19d1-b3f5-423c-b5bb-16501ce316a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506649401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.2506649401
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.1828647188
Short name T626
Test name
Test status
Simulation time 183178557829 ps
CPU time 32.54 seconds
Started Jun 25 05:52:18 PM PDT 24
Finished Jun 25 05:52:53 PM PDT 24
Peak memory 201928 kb
Host smart-033616a4-7712-4322-b2e5-c815f7f49dca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828647188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.1828647188
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.1560990317
Short name T195
Test name
Test status
Simulation time 355402243320 ps
CPU time 60.67 seconds
Started Jun 25 05:52:18 PM PDT 24
Finished Jun 25 05:53:21 PM PDT 24
Peak memory 201880 kb
Host smart-52bd30bd-1ea2-4395-8858-dbbf8c1c6bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560990317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.1560990317
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2960605551
Short name T162
Test name
Test status
Simulation time 164705392100 ps
CPU time 78.13 seconds
Started Jun 25 05:52:17 PM PDT 24
Finished Jun 25 05:53:37 PM PDT 24
Peak memory 201868 kb
Host smart-ddd5e5f0-7ac1-4337-9ce3-e0119bed4a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960605551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2960605551
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.798271188
Short name T488
Test name
Test status
Simulation time 482981351744 ps
CPU time 282.58 seconds
Started Jun 25 05:52:18 PM PDT 24
Finished Jun 25 05:57:03 PM PDT 24
Peak memory 201880 kb
Host smart-23b8e44d-f620-4f81-aad1-90721c956fc6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=798271188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrup
t_fixed.798271188
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.1591994718
Short name T299
Test name
Test status
Simulation time 328568592675 ps
CPU time 688.44 seconds
Started Jun 25 05:52:19 PM PDT 24
Finished Jun 25 06:03:50 PM PDT 24
Peak memory 201864 kb
Host smart-060c5a89-8836-4582-b400-9ad5918e080e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591994718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.1591994718
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.4123911915
Short name T779
Test name
Test status
Simulation time 166442861413 ps
CPU time 195.21 seconds
Started Jun 25 05:52:17 PM PDT 24
Finished Jun 25 05:55:34 PM PDT 24
Peak memory 201848 kb
Host smart-43062daf-c980-4eaf-b141-f7ed4c748a69
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123911915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.4123911915
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2497416258
Short name T502
Test name
Test status
Simulation time 464789153217 ps
CPU time 269.66 seconds
Started Jun 25 05:52:16 PM PDT 24
Finished Jun 25 05:56:46 PM PDT 24
Peak memory 201816 kb
Host smart-0f3c4b16-3f41-4734-8c17-073666566a85
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497416258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2497416258
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3139696312
Short name T699
Test name
Test status
Simulation time 588241441459 ps
CPU time 337.53 seconds
Started Jun 25 05:52:19 PM PDT 24
Finished Jun 25 05:57:58 PM PDT 24
Peak memory 201852 kb
Host smart-08eb29a5-2c83-4815-8a21-b266ba3301e8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139696312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.3139696312
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.2076613966
Short name T229
Test name
Test status
Simulation time 95146300253 ps
CPU time 508.97 seconds
Started Jun 25 05:52:16 PM PDT 24
Finished Jun 25 06:00:45 PM PDT 24
Peak memory 202172 kb
Host smart-bf806c1c-16b3-4c53-801a-92a50581dd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076613966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2076613966
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3656445038
Short name T748
Test name
Test status
Simulation time 21983845894 ps
CPU time 27.62 seconds
Started Jun 25 05:52:18 PM PDT 24
Finished Jun 25 05:52:48 PM PDT 24
Peak memory 201684 kb
Host smart-dba7cf39-4010-4ec1-8b6d-0300ffcac372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656445038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3656445038
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1151751041
Short name T485
Test name
Test status
Simulation time 3396291005 ps
CPU time 8.01 seconds
Started Jun 25 05:52:18 PM PDT 24
Finished Jun 25 05:52:29 PM PDT 24
Peak memory 201664 kb
Host smart-8a03b539-01f7-43cd-985e-ed5e63191863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151751041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1151751041
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.2773180611
Short name T416
Test name
Test status
Simulation time 5889950951 ps
CPU time 15.06 seconds
Started Jun 25 05:52:18 PM PDT 24
Finished Jun 25 05:52:35 PM PDT 24
Peak memory 201660 kb
Host smart-f9c185b6-8563-4e00-a733-4db769eedf7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773180611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2773180611
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.111298799
Short name T267
Test name
Test status
Simulation time 381135862750 ps
CPU time 891.16 seconds
Started Jun 25 05:52:18 PM PDT 24
Finished Jun 25 06:07:12 PM PDT 24
Peak memory 201904 kb
Host smart-d25de4bd-2bdd-4869-83e7-0156223be9a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111298799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.
111298799
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.2148163329
Short name T87
Test name
Test status
Simulation time 319877657 ps
CPU time 1.28 seconds
Started Jun 25 05:52:27 PM PDT 24
Finished Jun 25 05:52:30 PM PDT 24
Peak memory 201636 kb
Host smart-3c52e2e1-3db9-45c1-ba0a-4f5146ea57cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148163329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2148163329
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.232638227
Short name T717
Test name
Test status
Simulation time 339148744787 ps
CPU time 218.25 seconds
Started Jun 25 05:52:19 PM PDT 24
Finished Jun 25 05:56:00 PM PDT 24
Peak memory 201852 kb
Host smart-363cc77a-f559-452f-a9c4-e6ab4741d610
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232638227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gati
ng.232638227
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.2714488954
Short name T248
Test name
Test status
Simulation time 159493008328 ps
CPU time 183.49 seconds
Started Jun 25 05:52:19 PM PDT 24
Finished Jun 25 05:55:25 PM PDT 24
Peak memory 201924 kb
Host smart-8456c718-8e1b-4995-8cf8-93e538362d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714488954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.2714488954
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3934689332
Short name T369
Test name
Test status
Simulation time 487689849391 ps
CPU time 236.03 seconds
Started Jun 25 05:52:17 PM PDT 24
Finished Jun 25 05:56:14 PM PDT 24
Peak memory 201656 kb
Host smart-ea41d5ff-b352-424d-a3a2-9d23ddc9edc1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934689332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.3934689332
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2154322281
Short name T431
Test name
Test status
Simulation time 486291360937 ps
CPU time 127.24 seconds
Started Jun 25 05:52:19 PM PDT 24
Finished Jun 25 05:54:28 PM PDT 24
Peak memory 201848 kb
Host smart-a34358d8-e69b-4971-91cd-d580503ee80c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154322281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2154322281
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.2261095378
Short name T280
Test name
Test status
Simulation time 352432212598 ps
CPU time 793.12 seconds
Started Jun 25 05:52:21 PM PDT 24
Finished Jun 25 06:05:35 PM PDT 24
Peak memory 201904 kb
Host smart-0df99061-19c4-44a8-9317-17068187e3c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261095378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.2261095378
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.4162220853
Short name T783
Test name
Test status
Simulation time 201433145508 ps
CPU time 123.47 seconds
Started Jun 25 05:52:17 PM PDT 24
Finished Jun 25 05:54:23 PM PDT 24
Peak memory 201852 kb
Host smart-dd3c83b8-2b0f-4809-906e-1f9754eef24f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162220853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.4162220853
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.5283441
Short name T457
Test name
Test status
Simulation time 122702473513 ps
CPU time 411.71 seconds
Started Jun 25 05:52:25 PM PDT 24
Finished Jun 25 05:59:17 PM PDT 24
Peak memory 202116 kb
Host smart-405e28a0-c877-4d0f-8960-fe5371681e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5283441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.5283441
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.4095432692
Short name T454
Test name
Test status
Simulation time 25774123023 ps
CPU time 14.86 seconds
Started Jun 25 05:52:30 PM PDT 24
Finished Jun 25 05:52:46 PM PDT 24
Peak memory 201664 kb
Host smart-c0b25383-36df-4d15-8578-0318eb3c9fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095432692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.4095432692
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3936157405
Short name T415
Test name
Test status
Simulation time 5043409627 ps
CPU time 6.88 seconds
Started Jun 25 05:52:25 PM PDT 24
Finished Jun 25 05:52:32 PM PDT 24
Peak memory 201676 kb
Host smart-cd76336c-d00a-40dc-a426-b30b475558b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936157405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3936157405
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.3543786503
Short name T40
Test name
Test status
Simulation time 6132263276 ps
CPU time 15.36 seconds
Started Jun 25 05:52:17 PM PDT 24
Finished Jun 25 05:52:33 PM PDT 24
Peak memory 201680 kb
Host smart-2bcf3cad-6c5f-4b93-9c3d-2c28408d1aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543786503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3543786503
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1718776476
Short name T104
Test name
Test status
Simulation time 69528952298 ps
CPU time 165.04 seconds
Started Jun 25 05:52:27 PM PDT 24
Finished Jun 25 05:55:13 PM PDT 24
Peak memory 211528 kb
Host smart-972d404a-bd87-43ca-8d32-6201340b1def
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718776476 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1718776476
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1856014885
Short name T568
Test name
Test status
Simulation time 446841107 ps
CPU time 0.73 seconds
Started Jun 25 05:52:25 PM PDT 24
Finished Jun 25 05:52:27 PM PDT 24
Peak memory 201616 kb
Host smart-83462fdb-4856-4a40-8bff-acba4820a803
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856014885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1856014885
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.726669065
Short name T127
Test name
Test status
Simulation time 161472973195 ps
CPU time 79.55 seconds
Started Jun 25 05:52:25 PM PDT 24
Finished Jun 25 05:53:46 PM PDT 24
Peak memory 202104 kb
Host smart-dfe0d79c-8a14-4a88-a7a6-ff9971897098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726669065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.726669065
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.2231919317
Short name T170
Test name
Test status
Simulation time 330428931960 ps
CPU time 735.89 seconds
Started Jun 25 05:52:26 PM PDT 24
Finished Jun 25 06:04:43 PM PDT 24
Peak memory 201876 kb
Host smart-a0421560-16a7-426b-83e0-851cbc039763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231919317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.2231919317
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1789607842
Short name T359
Test name
Test status
Simulation time 485812303753 ps
CPU time 581.69 seconds
Started Jun 25 05:52:26 PM PDT 24
Finished Jun 25 06:02:10 PM PDT 24
Peak memory 201848 kb
Host smart-c4f7a90e-2391-433b-95ce-b24c6b5d436b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789607842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1789607842
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3984085210
Short name T112
Test name
Test status
Simulation time 164573970137 ps
CPU time 328.69 seconds
Started Jun 25 05:52:25 PM PDT 24
Finished Jun 25 05:57:55 PM PDT 24
Peak memory 201816 kb
Host smart-ddaa5105-3271-4448-ba8a-eaf2f780740c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984085210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3984085210
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.2731179392
Short name T669
Test name
Test status
Simulation time 492066077258 ps
CPU time 1185.26 seconds
Started Jun 25 05:52:25 PM PDT 24
Finished Jun 25 06:12:11 PM PDT 24
Peak memory 201868 kb
Host smart-d78ee41f-4bbd-46ae-b167-c8600e1c57ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731179392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.2731179392
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2717195580
Short name T337
Test name
Test status
Simulation time 195945754526 ps
CPU time 236.15 seconds
Started Jun 25 05:52:24 PM PDT 24
Finished Jun 25 05:56:21 PM PDT 24
Peak memory 201780 kb
Host smart-70193ab7-bf46-464f-a105-9054823ca091
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717195580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2717195580
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.822878350
Short name T583
Test name
Test status
Simulation time 412676491993 ps
CPU time 979.76 seconds
Started Jun 25 05:52:27 PM PDT 24
Finished Jun 25 06:08:48 PM PDT 24
Peak memory 201848 kb
Host smart-37992302-a4f2-4ea0-8556-9a13f454f286
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822878350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
adc_ctrl_filters_wakeup_fixed.822878350
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.789142361
Short name T660
Test name
Test status
Simulation time 103427029635 ps
CPU time 331.98 seconds
Started Jun 25 05:52:27 PM PDT 24
Finished Jun 25 05:58:01 PM PDT 24
Peak memory 202172 kb
Host smart-a16ff85a-98b6-47d3-80b9-f0a8ffc050c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789142361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.789142361
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2167011332
Short name T388
Test name
Test status
Simulation time 32978782227 ps
CPU time 76.06 seconds
Started Jun 25 05:52:23 PM PDT 24
Finished Jun 25 05:53:40 PM PDT 24
Peak memory 201700 kb
Host smart-7ccd5490-c5c2-4203-96d2-00a60fb08c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167011332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2167011332
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.178605094
Short name T69
Test name
Test status
Simulation time 4998707714 ps
CPU time 13.23 seconds
Started Jun 25 05:52:24 PM PDT 24
Finished Jun 25 05:52:38 PM PDT 24
Peak memory 201656 kb
Host smart-83fec48f-009b-4a0d-944e-6dfe87b210cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178605094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.178605094
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2021988866
Short name T787
Test name
Test status
Simulation time 5640708501 ps
CPU time 14.41 seconds
Started Jun 25 05:52:30 PM PDT 24
Finished Jun 25 05:52:45 PM PDT 24
Peak memory 201676 kb
Host smart-cf1f8e43-1830-4119-8214-4f0963223373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021988866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2021988866
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1208861328
Short name T301
Test name
Test status
Simulation time 374419743721 ps
CPU time 173.57 seconds
Started Jun 25 05:52:27 PM PDT 24
Finished Jun 25 05:55:22 PM PDT 24
Peak memory 201800 kb
Host smart-c54c861d-eac8-4aa2-8506-b22c175be81a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208861328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1208861328
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2637025145
Short name T282
Test name
Test status
Simulation time 265700348626 ps
CPU time 141.17 seconds
Started Jun 25 05:52:27 PM PDT 24
Finished Jun 25 05:54:50 PM PDT 24
Peak memory 210540 kb
Host smart-94e2278a-f2bd-492e-aaf7-49029925a771
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637025145 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.2637025145
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2171094309
Short name T668
Test name
Test status
Simulation time 334691682 ps
CPU time 1.44 seconds
Started Jun 25 05:52:25 PM PDT 24
Finished Jun 25 05:52:28 PM PDT 24
Peak memory 201616 kb
Host smart-e0b89f21-c7b5-4b66-b933-cb0c61430557
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171094309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2171094309
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.880928361
Short name T199
Test name
Test status
Simulation time 365621639670 ps
CPU time 212.25 seconds
Started Jun 25 05:52:25 PM PDT 24
Finished Jun 25 05:55:59 PM PDT 24
Peak memory 201812 kb
Host smart-6dc44230-bfd1-457f-8daf-08cf72bc4c25
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880928361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gati
ng.880928361
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.1269522633
Short name T579
Test name
Test status
Simulation time 484829088692 ps
CPU time 1122.78 seconds
Started Jun 25 05:52:25 PM PDT 24
Finished Jun 25 06:11:09 PM PDT 24
Peak memory 201892 kb
Host smart-888c996d-82da-460f-a80e-5d4e5e3fa4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269522633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1269522633
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.2980302234
Short name T328
Test name
Test status
Simulation time 493999838364 ps
CPU time 518.5 seconds
Started Jun 25 05:52:27 PM PDT 24
Finished Jun 25 06:01:07 PM PDT 24
Peak memory 201748 kb
Host smart-fabdab23-fb4f-4701-b677-00cff63a4d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980302234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2980302234
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3822994605
Short name T663
Test name
Test status
Simulation time 329242697507 ps
CPU time 380.56 seconds
Started Jun 25 05:52:24 PM PDT 24
Finished Jun 25 05:58:46 PM PDT 24
Peak memory 201880 kb
Host smart-03a36136-3d16-4182-a499-7a4aa47909aa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822994605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.3822994605
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3162445120
Short name T757
Test name
Test status
Simulation time 326149793001 ps
CPU time 693.47 seconds
Started Jun 25 05:52:27 PM PDT 24
Finished Jun 25 06:04:03 PM PDT 24
Peak memory 201932 kb
Host smart-8417e598-c1ce-4c88-8b87-283faec900f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162445120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3162445120
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.636598419
Short name T601
Test name
Test status
Simulation time 483299542586 ps
CPU time 142.11 seconds
Started Jun 25 05:52:30 PM PDT 24
Finished Jun 25 05:54:53 PM PDT 24
Peak memory 201864 kb
Host smart-02352ac9-fdcc-4ccf-af5d-987a6306d7e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=636598419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.636598419
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.1429267385
Short name T314
Test name
Test status
Simulation time 355457506579 ps
CPU time 49.93 seconds
Started Jun 25 05:52:26 PM PDT 24
Finished Jun 25 05:53:18 PM PDT 24
Peak memory 201852 kb
Host smart-1bac19bd-d7c6-4da9-940f-2da409c86f89
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429267385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.1429267385
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2102231047
Short name T522
Test name
Test status
Simulation time 609532675059 ps
CPU time 1235.15 seconds
Started Jun 25 05:52:26 PM PDT 24
Finished Jun 25 06:13:03 PM PDT 24
Peak memory 201848 kb
Host smart-6be26243-ea8c-4209-9022-8e26fcb8eb5e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102231047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.2102231047
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.3893381109
Short name T8
Test name
Test status
Simulation time 73822219116 ps
CPU time 230.63 seconds
Started Jun 25 05:52:25 PM PDT 24
Finished Jun 25 05:56:17 PM PDT 24
Peak memory 202256 kb
Host smart-fd818ead-aaa3-4a38-acd8-aa678ed2b5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893381109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.3893381109
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.2299915061
Short name T590
Test name
Test status
Simulation time 38055218036 ps
CPU time 42.48 seconds
Started Jun 25 05:52:27 PM PDT 24
Finished Jun 25 05:53:11 PM PDT 24
Peak memory 201580 kb
Host smart-580462a7-18aa-4a9f-bbc0-85107711a4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299915061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.2299915061
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.2421899092
Short name T405
Test name
Test status
Simulation time 3424327106 ps
CPU time 2.51 seconds
Started Jun 25 05:52:27 PM PDT 24
Finished Jun 25 05:52:31 PM PDT 24
Peak memory 201664 kb
Host smart-5fa844fc-092a-41f9-a2f6-24696036f1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421899092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2421899092
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.56129369
Short name T694
Test name
Test status
Simulation time 5895213283 ps
CPU time 2.26 seconds
Started Jun 25 05:52:26 PM PDT 24
Finished Jun 25 05:52:30 PM PDT 24
Peak memory 201648 kb
Host smart-77c44652-1df2-4d81-a1e6-9d825d144f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56129369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.56129369
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2986453383
Short name T305
Test name
Test status
Simulation time 224881503358 ps
CPU time 129.97 seconds
Started Jun 25 05:52:24 PM PDT 24
Finished Jun 25 05:54:35 PM PDT 24
Peak memory 201796 kb
Host smart-5decc419-ad94-4af9-b7e1-b1054880cc47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986453383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2986453383
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.424228769
Short name T22
Test name
Test status
Simulation time 402178158767 ps
CPU time 259.48 seconds
Started Jun 25 05:52:27 PM PDT 24
Finished Jun 25 05:56:48 PM PDT 24
Peak memory 210364 kb
Host smart-b1054e43-9323-47f2-8ded-976dac81cbba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424228769 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.424228769
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2482439721
Short name T31
Test name
Test status
Simulation time 426066463 ps
CPU time 0.87 seconds
Started Jun 25 05:52:34 PM PDT 24
Finished Jun 25 05:52:37 PM PDT 24
Peak memory 201620 kb
Host smart-9013a9cd-6132-46cf-bf5a-ef5e96f7b327
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482439721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2482439721
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3427926191
Short name T98
Test name
Test status
Simulation time 165781674731 ps
CPU time 199.25 seconds
Started Jun 25 05:52:26 PM PDT 24
Finished Jun 25 05:55:47 PM PDT 24
Peak memory 201848 kb
Host smart-9a0ecb6d-08ad-4069-8dc6-30494dfa7702
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427926191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3427926191
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.516340719
Short name T650
Test name
Test status
Simulation time 522295861005 ps
CPU time 1028.68 seconds
Started Jun 25 05:52:26 PM PDT 24
Finished Jun 25 06:09:36 PM PDT 24
Peak memory 201860 kb
Host smart-7c368073-4436-4ad4-a64b-93305a476827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516340719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.516340719
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.2517046128
Short name T329
Test name
Test status
Simulation time 164130010734 ps
CPU time 99.79 seconds
Started Jun 25 05:52:25 PM PDT 24
Finished Jun 25 05:54:06 PM PDT 24
Peak memory 201920 kb
Host smart-95bd8795-368b-4fb1-97fe-a7afda01693b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517046128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.2517046128
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3491909504
Short name T377
Test name
Test status
Simulation time 489069881410 ps
CPU time 1112.44 seconds
Started Jun 25 05:52:27 PM PDT 24
Finished Jun 25 06:11:01 PM PDT 24
Peak memory 201840 kb
Host smart-a719c59e-5486-45cb-8ddd-4f01082202fb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491909504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.3491909504
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.1746349715
Short name T307
Test name
Test status
Simulation time 326333150869 ps
CPU time 200.27 seconds
Started Jun 25 05:52:25 PM PDT 24
Finished Jun 25 05:55:47 PM PDT 24
Peak memory 201864 kb
Host smart-ae2b3269-a9c2-4775-b892-8f00c1e622c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746349715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.1746349715
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.2082936443
Short name T406
Test name
Test status
Simulation time 494000677802 ps
CPU time 1041.07 seconds
Started Jun 25 05:52:23 PM PDT 24
Finished Jun 25 06:09:45 PM PDT 24
Peak memory 201848 kb
Host smart-fde8314e-3f04-4542-a27c-1cbbe450e8ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082936443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.2082936443
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3082088327
Short name T584
Test name
Test status
Simulation time 527390512013 ps
CPU time 1280.53 seconds
Started Jun 25 05:52:25 PM PDT 24
Finished Jun 25 06:13:47 PM PDT 24
Peak memory 201892 kb
Host smart-ce439428-0b2b-447f-8f94-0cea35fdcc07
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082088327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3082088327
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1197867734
Short name T593
Test name
Test status
Simulation time 612140896442 ps
CPU time 1484.17 seconds
Started Jun 25 05:52:27 PM PDT 24
Finished Jun 25 06:17:13 PM PDT 24
Peak memory 201824 kb
Host smart-96fe7ae6-2ddb-484a-8f8b-0e96e903404c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197867734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1197867734
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.1876715007
Short name T233
Test name
Test status
Simulation time 90356262208 ps
CPU time 273.78 seconds
Started Jun 25 05:52:31 PM PDT 24
Finished Jun 25 05:57:06 PM PDT 24
Peak memory 202024 kb
Host smart-dbb405b7-9a9d-4bac-a80e-1f0828797300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876715007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1876715007
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1425674012
Short name T784
Test name
Test status
Simulation time 43806003317 ps
CPU time 100.78 seconds
Started Jun 25 05:52:34 PM PDT 24
Finished Jun 25 05:54:17 PM PDT 24
Peak memory 201608 kb
Host smart-c1998f90-d73e-40b2-a6ba-20f18ef3b3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425674012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1425674012
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.410495180
Short name T659
Test name
Test status
Simulation time 4145842973 ps
CPU time 3.17 seconds
Started Jun 25 05:52:33 PM PDT 24
Finished Jun 25 05:52:37 PM PDT 24
Peak memory 201656 kb
Host smart-4c33c6b3-6224-4979-a3ab-58274db35ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410495180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.410495180
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.1934072890
Short name T152
Test name
Test status
Simulation time 5808319190 ps
CPU time 14.41 seconds
Started Jun 25 05:52:24 PM PDT 24
Finished Jun 25 05:52:39 PM PDT 24
Peak memory 201652 kb
Host smart-23d9d60c-57f4-486d-912a-fbda175d66b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934072890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.1934072890
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.2532880793
Short name T749
Test name
Test status
Simulation time 15229824703 ps
CPU time 9.35 seconds
Started Jun 25 05:52:36 PM PDT 24
Finished Jun 25 05:52:46 PM PDT 24
Peak memory 210188 kb
Host smart-8b60bf08-a38a-46c9-a145-63469e6b6fb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532880793 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.2532880793
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.3283272491
Short name T528
Test name
Test status
Simulation time 430798623 ps
CPU time 0.88 seconds
Started Jun 25 05:52:32 PM PDT 24
Finished Jun 25 05:52:33 PM PDT 24
Peak memory 201636 kb
Host smart-d591fc69-54f8-4b1e-b00e-bb7dd3788ea4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283272491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3283272491
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.3972605646
Short name T667
Test name
Test status
Simulation time 174182715025 ps
CPU time 207.93 seconds
Started Jun 25 05:52:33 PM PDT 24
Finished Jun 25 05:56:02 PM PDT 24
Peak memory 201848 kb
Host smart-f433e73c-2262-46f8-8943-72c178a73d7a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972605646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.3972605646
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.471884294
Short name T245
Test name
Test status
Simulation time 490013288305 ps
CPU time 302.55 seconds
Started Jun 25 05:52:33 PM PDT 24
Finished Jun 25 05:57:36 PM PDT 24
Peak memory 201868 kb
Host smart-5545f326-d8d9-43ba-826f-20c1523dec0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471884294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.471884294
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.262784716
Short name T173
Test name
Test status
Simulation time 160918497052 ps
CPU time 80.29 seconds
Started Jun 25 05:52:36 PM PDT 24
Finished Jun 25 05:53:57 PM PDT 24
Peak memory 201852 kb
Host smart-c214f41f-c871-4e97-a23f-41e9c4bff994
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=262784716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrup
t_fixed.262784716
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.810329906
Short name T603
Test name
Test status
Simulation time 325196674359 ps
CPU time 730.7 seconds
Started Jun 25 05:52:36 PM PDT 24
Finished Jun 25 06:04:48 PM PDT 24
Peak memory 201868 kb
Host smart-b3f2e85b-cf12-46b7-bf94-3faa18a0dc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810329906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.810329906
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.489396623
Short name T552
Test name
Test status
Simulation time 490926979883 ps
CPU time 295.5 seconds
Started Jun 25 05:52:34 PM PDT 24
Finished Jun 25 05:57:30 PM PDT 24
Peak memory 202084 kb
Host smart-c9c9d38c-150d-4414-96a0-4f435971e137
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=489396623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixe
d.489396623
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.3182620240
Short name T560
Test name
Test status
Simulation time 233575146093 ps
CPU time 147.71 seconds
Started Jun 25 05:52:34 PM PDT 24
Finished Jun 25 05:55:04 PM PDT 24
Peak memory 201892 kb
Host smart-88d142b9-80ff-4a51-86a6-12a3aedcd796
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182620240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.3182620240
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.713992394
Short name T676
Test name
Test status
Simulation time 400315436376 ps
CPU time 674.94 seconds
Started Jun 25 05:52:33 PM PDT 24
Finished Jun 25 06:03:49 PM PDT 24
Peak memory 201800 kb
Host smart-5eb0a36e-721e-4a8d-8a29-73f5d64bcbde
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713992394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
adc_ctrl_filters_wakeup_fixed.713992394
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.696754037
Short name T533
Test name
Test status
Simulation time 81542849728 ps
CPU time 284.59 seconds
Started Jun 25 05:52:32 PM PDT 24
Finished Jun 25 05:57:17 PM PDT 24
Peak memory 202176 kb
Host smart-dba38849-022e-492d-9cf3-e58a33cb26e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696754037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.696754037
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1365114553
Short name T500
Test name
Test status
Simulation time 35593729574 ps
CPU time 22.7 seconds
Started Jun 25 05:52:35 PM PDT 24
Finished Jun 25 05:52:59 PM PDT 24
Peak memory 201680 kb
Host smart-eb042ad6-490e-45ff-b2de-8b445eeb1d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365114553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1365114553
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.3682580265
Short name T447
Test name
Test status
Simulation time 4662756616 ps
CPU time 2.26 seconds
Started Jun 25 05:52:34 PM PDT 24
Finished Jun 25 05:52:37 PM PDT 24
Peak memory 201676 kb
Host smart-cf15be5e-a5c3-4c4b-a6de-4043583b27ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682580265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.3682580265
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.2000163794
Short name T569
Test name
Test status
Simulation time 5878471568 ps
CPU time 13.7 seconds
Started Jun 25 05:52:35 PM PDT 24
Finished Jun 25 05:52:50 PM PDT 24
Peak memory 201644 kb
Host smart-b62b6cfa-a40e-4375-9b9b-b123269d90ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000163794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.2000163794
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.2431544441
Short name T446
Test name
Test status
Simulation time 1264824686 ps
CPU time 3.33 seconds
Started Jun 25 05:52:33 PM PDT 24
Finished Jun 25 05:52:38 PM PDT 24
Peak memory 201596 kb
Host smart-289b2186-6b68-4aac-b42e-ee2a1b6b65d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431544441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.2431544441
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1858341890
Short name T595
Test name
Test status
Simulation time 373884298065 ps
CPU time 115.87 seconds
Started Jun 25 05:52:33 PM PDT 24
Finished Jun 25 05:54:30 PM PDT 24
Peak memory 201780 kb
Host smart-aa6bdd0e-6a75-4265-b07b-7802049a02ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858341890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1858341890
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.1720817423
Short name T158
Test name
Test status
Simulation time 160735466517 ps
CPU time 105.25 seconds
Started Jun 25 05:52:35 PM PDT 24
Finished Jun 25 05:54:22 PM PDT 24
Peak memory 201940 kb
Host smart-662df276-f152-4bd6-8620-616278ef32c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720817423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1720817423
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.3995611892
Short name T187
Test name
Test status
Simulation time 322505478423 ps
CPU time 142.52 seconds
Started Jun 25 05:52:35 PM PDT 24
Finished Jun 25 05:54:59 PM PDT 24
Peak memory 201840 kb
Host smart-ae423c73-8ece-460c-9a1a-52af06c8b103
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995611892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.3995611892
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.210144538
Short name T408
Test name
Test status
Simulation time 162499169570 ps
CPU time 362.16 seconds
Started Jun 25 05:52:34 PM PDT 24
Finished Jun 25 05:58:38 PM PDT 24
Peak memory 201828 kb
Host smart-53f2b4f9-a2e5-48bf-9fff-7687d8ab79b3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=210144538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.210144538
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.1531973205
Short name T320
Test name
Test status
Simulation time 542379887801 ps
CPU time 1174.91 seconds
Started Jun 25 05:52:34 PM PDT 24
Finished Jun 25 06:12:10 PM PDT 24
Peak memory 201860 kb
Host smart-6faaa3bc-0ae0-4e98-97be-a1b8ec6b8fc9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531973205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.1531973205
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3552699898
Short name T547
Test name
Test status
Simulation time 621610741407 ps
CPU time 1405.95 seconds
Started Jun 25 05:52:34 PM PDT 24
Finished Jun 25 06:16:01 PM PDT 24
Peak memory 201920 kb
Host smart-4417d835-54fe-4ed4-b3ab-c360f856b501
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552699898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3552699898
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.394872271
Short name T703
Test name
Test status
Simulation time 65076050399 ps
CPU time 290.22 seconds
Started Jun 25 05:52:36 PM PDT 24
Finished Jun 25 05:57:27 PM PDT 24
Peak memory 202176 kb
Host smart-b080b753-8f6c-4bc9-8cb7-bd373eda824e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394872271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.394872271
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.4233178478
Short name T793
Test name
Test status
Simulation time 32512165644 ps
CPU time 19.75 seconds
Started Jun 25 05:52:34 PM PDT 24
Finished Jun 25 05:52:56 PM PDT 24
Peak memory 201680 kb
Host smart-041f933a-280e-4500-ba63-85287436f705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233178478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.4233178478
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1876314434
Short name T462
Test name
Test status
Simulation time 4069705106 ps
CPU time 3.13 seconds
Started Jun 25 05:52:34 PM PDT 24
Finished Jun 25 05:52:39 PM PDT 24
Peak memory 201676 kb
Host smart-9fbc0583-ab5c-4337-b7fd-b2d15b9398c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876314434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1876314434
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3936516029
Short name T375
Test name
Test status
Simulation time 6019418362 ps
CPU time 14.77 seconds
Started Jun 25 05:52:33 PM PDT 24
Finished Jun 25 05:52:49 PM PDT 24
Peak memory 201664 kb
Host smart-d08768ff-be7d-45d3-9c6e-c3781cd5fe1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936516029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3936516029
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.1945355572
Short name T217
Test name
Test status
Simulation time 210339518980 ps
CPU time 116.66 seconds
Started Jun 25 05:52:34 PM PDT 24
Finished Jun 25 05:54:31 PM PDT 24
Peak memory 201864 kb
Host smart-d46aa4b3-2f08-423e-b220-a9df1214980e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945355572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.1945355572
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.4282933772
Short name T50
Test name
Test status
Simulation time 60926616008 ps
CPU time 94.21 seconds
Started Jun 25 05:52:34 PM PDT 24
Finished Jun 25 05:54:09 PM PDT 24
Peak memory 210492 kb
Host smart-04f9d053-baa6-4056-998f-5284bbbdc637
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282933772 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.4282933772
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.3314643710
Short name T477
Test name
Test status
Simulation time 515127417 ps
CPU time 0.91 seconds
Started Jun 25 05:52:44 PM PDT 24
Finished Jun 25 05:52:46 PM PDT 24
Peak memory 201612 kb
Host smart-8ec89bb1-432c-46d3-a64d-fda0b562f1ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314643710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3314643710
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.3452492446
Short name T753
Test name
Test status
Simulation time 161476200485 ps
CPU time 370.46 seconds
Started Jun 25 05:52:43 PM PDT 24
Finished Jun 25 05:58:54 PM PDT 24
Peak memory 201872 kb
Host smart-8287996a-d3c1-4ff5-a034-2b5609838845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452492446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.3452492446
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1814829434
Short name T244
Test name
Test status
Simulation time 481869096653 ps
CPU time 121.34 seconds
Started Jun 25 05:52:42 PM PDT 24
Finished Jun 25 05:54:44 PM PDT 24
Peak memory 201868 kb
Host smart-95a4b924-defe-4cca-ad0d-3babe5ff25b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814829434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1814829434
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1440326510
Short name T758
Test name
Test status
Simulation time 162554426316 ps
CPU time 96.79 seconds
Started Jun 25 05:52:40 PM PDT 24
Finished Jun 25 05:54:18 PM PDT 24
Peak memory 201860 kb
Host smart-b8b11c5a-07c7-4f6b-8891-1794caeda03e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440326510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1440326510
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.2381557814
Short name T159
Test name
Test status
Simulation time 160104814788 ps
CPU time 99.25 seconds
Started Jun 25 05:52:39 PM PDT 24
Finished Jun 25 05:54:19 PM PDT 24
Peak memory 201864 kb
Host smart-06f33f1d-afcd-4ee3-81f2-5f39cfedb760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381557814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.2381557814
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2111141545
Short name T576
Test name
Test status
Simulation time 159291173998 ps
CPU time 87.45 seconds
Started Jun 25 05:52:42 PM PDT 24
Finished Jun 25 05:54:10 PM PDT 24
Peak memory 201824 kb
Host smart-160cc79b-bff1-4572-98be-b624a06a88ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111141545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2111141545
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1175724769
Short name T204
Test name
Test status
Simulation time 552313155999 ps
CPU time 158.72 seconds
Started Jun 25 05:52:40 PM PDT 24
Finished Jun 25 05:55:20 PM PDT 24
Peak memory 201936 kb
Host smart-ead0c1fa-fd48-4b86-8269-4d9f1f2b1a6e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175724769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.1175724769
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2951730338
Short name T185
Test name
Test status
Simulation time 396040882086 ps
CPU time 159.21 seconds
Started Jun 25 05:52:39 PM PDT 24
Finished Jun 25 05:55:19 PM PDT 24
Peak memory 201840 kb
Host smart-ddd6930f-fd24-4220-8f99-3eed19b7d622
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951730338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2951730338
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2096245133
Short name T234
Test name
Test status
Simulation time 99773558842 ps
CPU time 478.18 seconds
Started Jun 25 05:52:48 PM PDT 24
Finished Jun 25 06:00:47 PM PDT 24
Peak memory 202200 kb
Host smart-b4315987-4201-42e3-91eb-ed11d084ad09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096245133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2096245133
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3735087264
Short name T541
Test name
Test status
Simulation time 42262190350 ps
CPU time 75.14 seconds
Started Jun 25 05:52:40 PM PDT 24
Finished Jun 25 05:53:56 PM PDT 24
Peak memory 201680 kb
Host smart-06dc2539-c545-4858-90fb-634fb29591be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735087264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3735087264
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.3664332004
Short name T651
Test name
Test status
Simulation time 3806418518 ps
CPU time 5.11 seconds
Started Jun 25 05:52:41 PM PDT 24
Finished Jun 25 05:52:47 PM PDT 24
Peak memory 201916 kb
Host smart-f8fc4605-b741-42e1-a6bf-46c98ea23ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664332004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3664332004
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.2197455793
Short name T580
Test name
Test status
Simulation time 6147271000 ps
CPU time 4.26 seconds
Started Jun 25 05:52:40 PM PDT 24
Finished Jun 25 05:52:46 PM PDT 24
Peak memory 201596 kb
Host smart-60528e14-7b22-4813-aee1-fb34015defc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197455793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2197455793
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1506289808
Short name T32
Test name
Test status
Simulation time 336967542430 ps
CPU time 370.63 seconds
Started Jun 25 05:52:40 PM PDT 24
Finished Jun 25 05:58:51 PM PDT 24
Peak memory 201936 kb
Host smart-a1600b09-a2e8-4edb-aaa6-cb1575bb5912
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506289808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1506289808
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.1214710480
Short name T450
Test name
Test status
Simulation time 380297013 ps
CPU time 1.63 seconds
Started Jun 25 05:52:47 PM PDT 24
Finished Jun 25 05:52:50 PM PDT 24
Peak memory 201608 kb
Host smart-269913d5-91fa-4058-a415-11d66d79e363
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214710480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1214710480
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.240550747
Short name T609
Test name
Test status
Simulation time 335680560465 ps
CPU time 211.93 seconds
Started Jun 25 05:52:48 PM PDT 24
Finished Jun 25 05:56:20 PM PDT 24
Peak memory 201852 kb
Host smart-81f53114-a456-4bd0-ac41-938eeb65c171
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240550747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gati
ng.240550747
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.3711099896
Short name T714
Test name
Test status
Simulation time 170651851875 ps
CPU time 191.9 seconds
Started Jun 25 05:52:47 PM PDT 24
Finished Jun 25 05:55:59 PM PDT 24
Peak memory 201944 kb
Host smart-d9ec479c-627f-404f-9951-456b9548e58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711099896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.3711099896
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2651835438
Short name T662
Test name
Test status
Simulation time 166149268557 ps
CPU time 90.91 seconds
Started Jun 25 05:52:41 PM PDT 24
Finished Jun 25 05:54:13 PM PDT 24
Peak memory 201940 kb
Host smart-e36afe73-55c7-4b7f-b278-609df8065230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651835438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2651835438
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.971713592
Short name T37
Test name
Test status
Simulation time 332555515900 ps
CPU time 165.35 seconds
Started Jun 25 05:52:48 PM PDT 24
Finished Jun 25 05:55:34 PM PDT 24
Peak memory 201844 kb
Host smart-3c4d1944-173a-42ae-8f69-0ef4a9891226
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=971713592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrup
t_fixed.971713592
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.577189814
Short name T794
Test name
Test status
Simulation time 487751412030 ps
CPU time 1149.7 seconds
Started Jun 25 05:52:48 PM PDT 24
Finished Jun 25 06:11:58 PM PDT 24
Peak memory 201888 kb
Host smart-51937066-d8f3-4a9b-9704-d1b799840b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577189814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.577189814
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3962991186
Short name T728
Test name
Test status
Simulation time 336498356648 ps
CPU time 291.42 seconds
Started Jun 25 05:52:43 PM PDT 24
Finished Jun 25 05:57:35 PM PDT 24
Peak memory 201832 kb
Host smart-d0dd5671-74d9-48fe-88e1-8553e511c3b6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962991186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.3962991186
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1486575813
Short name T23
Test name
Test status
Simulation time 205104499339 ps
CPU time 200.47 seconds
Started Jun 25 05:52:49 PM PDT 24
Finished Jun 25 05:56:11 PM PDT 24
Peak memory 201856 kb
Host smart-53d99dd2-d1a0-4752-9f65-571c19763584
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486575813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.1486575813
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.3636385113
Short name T365
Test name
Test status
Simulation time 26250718867 ps
CPU time 62.65 seconds
Started Jun 25 05:52:49 PM PDT 24
Finished Jun 25 05:53:52 PM PDT 24
Peak memory 201664 kb
Host smart-37368b29-fc50-485f-9ae0-7db29abdc1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636385113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.3636385113
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.2026058111
Short name T475
Test name
Test status
Simulation time 2939488063 ps
CPU time 2.38 seconds
Started Jun 25 05:52:46 PM PDT 24
Finished Jun 25 05:52:49 PM PDT 24
Peak memory 201688 kb
Host smart-02d6b222-80e7-4baa-98ff-065da2546c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026058111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2026058111
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.329505730
Short name T709
Test name
Test status
Simulation time 5723778407 ps
CPU time 7.19 seconds
Started Jun 25 05:52:40 PM PDT 24
Finished Jun 25 05:52:48 PM PDT 24
Peak memory 201660 kb
Host smart-25f7818f-7ca5-4f98-a6d1-46db7605dd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329505730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.329505730
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.1393505910
Short name T467
Test name
Test status
Simulation time 244597817261 ps
CPU time 412.12 seconds
Started Jun 25 05:52:46 PM PDT 24
Finished Jun 25 05:59:38 PM PDT 24
Peak memory 210356 kb
Host smart-a5e696e0-0d8c-446b-87a5-bb3154f35a24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393505910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.1393505910
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.15914236
Short name T726
Test name
Test status
Simulation time 168964866443 ps
CPU time 101.64 seconds
Started Jun 25 05:52:48 PM PDT 24
Finished Jun 25 05:54:30 PM PDT 24
Peak memory 210180 kb
Host smart-fad45900-08b4-42cc-8d25-98b672b14d4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15914236 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.15914236
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.110520554
Short name T64
Test name
Test status
Simulation time 376424766 ps
CPU time 1.52 seconds
Started Jun 25 05:52:01 PM PDT 24
Finished Jun 25 05:52:04 PM PDT 24
Peak memory 201604 kb
Host smart-5927c8c3-0803-42ec-9226-4e16d5078f90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110520554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.110520554
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.2484890015
Short name T176
Test name
Test status
Simulation time 161000236724 ps
CPU time 326.73 seconds
Started Jun 25 05:52:05 PM PDT 24
Finished Jun 25 05:57:34 PM PDT 24
Peak memory 201908 kb
Host smart-9f06a511-e758-4d38-a88b-d1c5a9ebb950
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484890015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.2484890015
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3517049293
Short name T268
Test name
Test status
Simulation time 408442553700 ps
CPU time 255.37 seconds
Started Jun 25 05:51:59 PM PDT 24
Finished Jun 25 05:56:16 PM PDT 24
Peak memory 201876 kb
Host smart-65f40ad4-55d2-4b5c-a09e-3b5058609da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517049293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3517049293
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3831759852
Short name T291
Test name
Test status
Simulation time 161958299264 ps
CPU time 373.85 seconds
Started Jun 25 05:51:54 PM PDT 24
Finished Jun 25 05:58:10 PM PDT 24
Peak memory 201852 kb
Host smart-eaf03757-7130-4a08-ac89-1b6ff92daf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831759852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3831759852
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.926471965
Short name T390
Test name
Test status
Simulation time 164436031661 ps
CPU time 102.25 seconds
Started Jun 25 05:51:56 PM PDT 24
Finished Jun 25 05:53:39 PM PDT 24
Peak memory 201836 kb
Host smart-949c0a7f-2870-4ad3-8aed-da41bbfae688
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=926471965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt
_fixed.926471965
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.2812659238
Short name T323
Test name
Test status
Simulation time 319587747648 ps
CPU time 734.51 seconds
Started Jun 25 05:51:54 PM PDT 24
Finished Jun 25 06:04:11 PM PDT 24
Peak memory 201868 kb
Host smart-fcbd93eb-2516-4f5e-ae03-4a4a8b12fac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812659238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.2812659238
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.3383688242
Short name T215
Test name
Test status
Simulation time 487612871782 ps
CPU time 1054.79 seconds
Started Jun 25 05:51:52 PM PDT 24
Finished Jun 25 06:09:29 PM PDT 24
Peak memory 201844 kb
Host smart-389d49dc-455d-4087-95cd-833fc8900dfd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383688242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.3383688242
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2809917610
Short name T687
Test name
Test status
Simulation time 392279495566 ps
CPU time 938.52 seconds
Started Jun 25 05:51:55 PM PDT 24
Finished Jun 25 06:07:35 PM PDT 24
Peak memory 201700 kb
Host smart-c06d1b71-13cd-43a3-bb1f-ea1e56bba780
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809917610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2809917610
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.2688261418
Short name T768
Test name
Test status
Simulation time 107710058226 ps
CPU time 471.21 seconds
Started Jun 25 05:51:59 PM PDT 24
Finished Jun 25 05:59:52 PM PDT 24
Peak memory 202108 kb
Host smart-c8b19337-7dcb-4d77-bc56-c10ca30c66e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688261418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.2688261418
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.1026721038
Short name T410
Test name
Test status
Simulation time 35039909816 ps
CPU time 12.2 seconds
Started Jun 25 05:52:01 PM PDT 24
Finished Jun 25 05:52:15 PM PDT 24
Peak memory 201660 kb
Host smart-0f59dded-4fe1-4eb0-886d-ed05aac4870a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026721038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.1026721038
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2818775377
Short name T460
Test name
Test status
Simulation time 2881665657 ps
CPU time 2.24 seconds
Started Jun 25 05:52:03 PM PDT 24
Finished Jun 25 05:52:07 PM PDT 24
Peak memory 201664 kb
Host smart-9ad44ab3-9636-42bb-94cd-ec5a544b0375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818775377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2818775377
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.17834574
Short name T81
Test name
Test status
Simulation time 3892629447 ps
CPU time 9.37 seconds
Started Jun 25 05:52:04 PM PDT 24
Finished Jun 25 05:52:15 PM PDT 24
Peak memory 217252 kb
Host smart-0ddea066-cd33-46f0-994f-afcf3140a49c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17834574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.17834574
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.22896185
Short name T495
Test name
Test status
Simulation time 5744504758 ps
CPU time 7.03 seconds
Started Jun 25 05:51:56 PM PDT 24
Finished Jun 25 05:52:04 PM PDT 24
Peak memory 201660 kb
Host smart-b37e3409-1898-4cf7-b2cf-95554c8dfea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22896185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.22896185
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.863418183
Short name T34
Test name
Test status
Simulation time 129285198469 ps
CPU time 535.51 seconds
Started Jun 25 05:52:03 PM PDT 24
Finished Jun 25 06:01:00 PM PDT 24
Peak memory 202172 kb
Host smart-0b104b05-ef92-4ab6-a270-8113bba6823b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863418183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.863418183
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1917344582
Short name T319
Test name
Test status
Simulation time 131002141163 ps
CPU time 86.69 seconds
Started Jun 25 05:51:59 PM PDT 24
Finished Jun 25 05:53:27 PM PDT 24
Peak memory 210184 kb
Host smart-e2fa5477-6f41-4835-9673-a50605c1718c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917344582 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1917344582
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.641167382
Short name T723
Test name
Test status
Simulation time 318100101 ps
CPU time 1.34 seconds
Started Jun 25 05:52:56 PM PDT 24
Finished Jun 25 05:52:58 PM PDT 24
Peak memory 201624 kb
Host smart-b162a2cc-18b1-4b65-aaba-d2eb20eba38f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641167382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.641167382
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3632925008
Short name T587
Test name
Test status
Simulation time 350490212849 ps
CPU time 209.03 seconds
Started Jun 25 05:52:57 PM PDT 24
Finished Jun 25 05:56:27 PM PDT 24
Peak memory 201852 kb
Host smart-5968aa65-4d8d-45f5-b528-e9a2ad2a066e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632925008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3632925008
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.208628851
Short name T270
Test name
Test status
Simulation time 522163232825 ps
CPU time 977.62 seconds
Started Jun 25 05:52:55 PM PDT 24
Finished Jun 25 06:09:13 PM PDT 24
Peak memory 201876 kb
Host smart-7831dae6-03c1-4862-9c36-8b322d274684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208628851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.208628851
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1715952655
Short name T192
Test name
Test status
Simulation time 488740675478 ps
CPU time 260.83 seconds
Started Jun 25 05:52:55 PM PDT 24
Finished Jun 25 05:57:16 PM PDT 24
Peak memory 201872 kb
Host smart-ef2ef3ef-c9e6-4ef0-a68d-fde064054c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715952655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1715952655
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.196134884
Short name T613
Test name
Test status
Simulation time 164647254133 ps
CPU time 39.98 seconds
Started Jun 25 05:52:54 PM PDT 24
Finished Jun 25 05:53:35 PM PDT 24
Peak memory 201864 kb
Host smart-c0871f9c-74f8-49ee-a58d-d5a56f5f89f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=196134884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrup
t_fixed.196134884
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3825652160
Short name T658
Test name
Test status
Simulation time 164686336007 ps
CPU time 100.42 seconds
Started Jun 25 05:52:46 PM PDT 24
Finished Jun 25 05:54:27 PM PDT 24
Peak memory 201864 kb
Host smart-ecbcc2c2-e1e4-4c64-96c2-cb5b887ed852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825652160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3825652160
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1526396308
Short name T368
Test name
Test status
Simulation time 482723118024 ps
CPU time 525.8 seconds
Started Jun 25 05:52:47 PM PDT 24
Finished Jun 25 06:01:34 PM PDT 24
Peak memory 201924 kb
Host smart-0c0f694b-ebdc-4b00-bd4e-bd3dde3f4373
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526396308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1526396308
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1017367141
Short name T452
Test name
Test status
Simulation time 393288844335 ps
CPU time 217.83 seconds
Started Jun 25 05:52:57 PM PDT 24
Finished Jun 25 05:56:36 PM PDT 24
Peak memory 201828 kb
Host smart-4ecfa971-c530-4230-9873-d8d312ff3bae
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017367141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.1017367141
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.404506357
Short name T103
Test name
Test status
Simulation time 24138774649 ps
CPU time 59.1 seconds
Started Jun 25 05:52:56 PM PDT 24
Finished Jun 25 05:53:56 PM PDT 24
Peak memory 201788 kb
Host smart-600edc1f-dcb6-4349-855d-bb8a38fae0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404506357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.404506357
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2192991128
Short name T412
Test name
Test status
Simulation time 3168546644 ps
CPU time 2.62 seconds
Started Jun 25 05:52:55 PM PDT 24
Finished Jun 25 05:52:59 PM PDT 24
Peak memory 201676 kb
Host smart-feef5b52-e0aa-4a27-9852-da41eb873a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192991128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2192991128
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.2554417974
Short name T360
Test name
Test status
Simulation time 5887628686 ps
CPU time 4.05 seconds
Started Jun 25 05:52:47 PM PDT 24
Finished Jun 25 05:52:51 PM PDT 24
Peak memory 201572 kb
Host smart-62fbd544-57b8-40cf-a69b-11b50321ad23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554417974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.2554417974
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.4003855990
Short name T273
Test name
Test status
Simulation time 259671204951 ps
CPU time 345.03 seconds
Started Jun 25 05:52:56 PM PDT 24
Finished Jun 25 05:58:42 PM PDT 24
Peak memory 218512 kb
Host smart-27aab802-37bb-4026-8a77-133d6a6cd46d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003855990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.4003855990
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.746960732
Short name T740
Test name
Test status
Simulation time 18330356878 ps
CPU time 41.57 seconds
Started Jun 25 05:52:56 PM PDT 24
Finished Jun 25 05:53:38 PM PDT 24
Peak memory 202000 kb
Host smart-81a70f55-7e46-44af-9b2c-14c90c4853ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746960732 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.746960732
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1078402622
Short name T504
Test name
Test status
Simulation time 293129392 ps
CPU time 1.21 seconds
Started Jun 25 05:53:04 PM PDT 24
Finished Jun 25 05:53:06 PM PDT 24
Peak memory 201624 kb
Host smart-4b2e3fb2-aa2f-4138-9add-9fe4cf251e64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078402622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1078402622
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.691110373
Short name T119
Test name
Test status
Simulation time 528215285340 ps
CPU time 1248.72 seconds
Started Jun 25 05:53:05 PM PDT 24
Finished Jun 25 06:13:54 PM PDT 24
Peak memory 201876 kb
Host smart-181c9b01-d0b2-407c-94fb-fc4334231b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691110373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.691110373
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.764471708
Short name T165
Test name
Test status
Simulation time 159980444200 ps
CPU time 89.88 seconds
Started Jun 25 05:53:01 PM PDT 24
Finished Jun 25 05:54:32 PM PDT 24
Peak memory 201860 kb
Host smart-9eea1d4a-d021-4eba-a926-711092fafb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764471708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.764471708
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3746595854
Short name T417
Test name
Test status
Simulation time 167987174324 ps
CPU time 403.69 seconds
Started Jun 25 05:53:02 PM PDT 24
Finished Jun 25 05:59:46 PM PDT 24
Peak memory 201812 kb
Host smart-19bfe0f8-9dfc-4fd0-b88f-54b020775982
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746595854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.3746595854
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.342776317
Short name T235
Test name
Test status
Simulation time 164861834288 ps
CPU time 186.8 seconds
Started Jun 25 05:53:02 PM PDT 24
Finished Jun 25 05:56:10 PM PDT 24
Peak memory 201872 kb
Host smart-14e7edfa-bac5-4c92-b536-1a62784868eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342776317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.342776317
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2357424975
Short name T654
Test name
Test status
Simulation time 330345830527 ps
CPU time 197.32 seconds
Started Jun 25 05:53:06 PM PDT 24
Finished Jun 25 05:56:24 PM PDT 24
Peak memory 201824 kb
Host smart-aa21d9ad-60de-49d0-8b8d-ea241f2ad137
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357424975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2357424975
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.66788109
Short name T306
Test name
Test status
Simulation time 361934106143 ps
CPU time 202.92 seconds
Started Jun 25 05:53:00 PM PDT 24
Finished Jun 25 05:56:24 PM PDT 24
Peak memory 201872 kb
Host smart-64221fc1-55a3-44da-93e8-58fbb0d5a92a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66788109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_w
akeup.66788109
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.775361123
Short name T644
Test name
Test status
Simulation time 583172702648 ps
CPU time 1313.83 seconds
Started Jun 25 05:53:01 PM PDT 24
Finished Jun 25 06:14:55 PM PDT 24
Peak memory 201872 kb
Host smart-853342b4-9db6-40db-8c2f-df53636666bf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775361123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.775361123
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.2523683599
Short name T438
Test name
Test status
Simulation time 113952578893 ps
CPU time 487.64 seconds
Started Jun 25 05:53:02 PM PDT 24
Finished Jun 25 06:01:10 PM PDT 24
Peak memory 202188 kb
Host smart-cb9354ac-ac1e-470c-9d5f-e866c0372c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523683599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2523683599
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.2290055960
Short name T181
Test name
Test status
Simulation time 35526809978 ps
CPU time 22.37 seconds
Started Jun 25 05:53:01 PM PDT 24
Finished Jun 25 05:53:24 PM PDT 24
Peak memory 201648 kb
Host smart-017300c1-cee0-4437-b8c7-8991cf32ae95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290055960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.2290055960
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.891837987
Short name T630
Test name
Test status
Simulation time 3430946986 ps
CPU time 8.87 seconds
Started Jun 25 05:53:02 PM PDT 24
Finished Jun 25 05:53:12 PM PDT 24
Peak memory 201660 kb
Host smart-502bca00-5c19-4501-ae8d-258c80d51d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891837987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.891837987
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.939450707
Short name T113
Test name
Test status
Simulation time 5760698585 ps
CPU time 13.02 seconds
Started Jun 25 05:52:54 PM PDT 24
Finished Jun 25 05:53:08 PM PDT 24
Peak memory 201656 kb
Host smart-7699b314-2df8-4767-958c-94d23159dcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939450707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.939450707
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3419856900
Short name T86
Test name
Test status
Simulation time 362737258 ps
CPU time 1.44 seconds
Started Jun 25 05:53:14 PM PDT 24
Finished Jun 25 05:53:16 PM PDT 24
Peak memory 201624 kb
Host smart-e9a8ade8-1ba0-46ae-89bc-e9e6a095be5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419856900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3419856900
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.2313607966
Short name T283
Test name
Test status
Simulation time 335158773484 ps
CPU time 790.18 seconds
Started Jun 25 05:53:13 PM PDT 24
Finished Jun 25 06:06:24 PM PDT 24
Peak memory 201884 kb
Host smart-ed915fbd-05e3-435e-aa46-bb88a10ab855
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313607966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.2313607966
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3032670128
Short name T200
Test name
Test status
Simulation time 490794976604 ps
CPU time 239 seconds
Started Jun 25 05:53:12 PM PDT 24
Finished Jun 25 05:57:12 PM PDT 24
Peak memory 201820 kb
Host smart-63ef930d-346f-4ae3-99d2-3214ed0ccec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032670128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3032670128
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.542187520
Short name T453
Test name
Test status
Simulation time 162241002331 ps
CPU time 180.79 seconds
Started Jun 25 05:53:14 PM PDT 24
Finished Jun 25 05:56:16 PM PDT 24
Peak memory 201836 kb
Host smart-dbc2ad4d-d9e5-48ec-baba-2df63e49cff2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=542187520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrup
t_fixed.542187520
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.2952878481
Short name T786
Test name
Test status
Simulation time 159994029117 ps
CPU time 365 seconds
Started Jun 25 05:53:05 PM PDT 24
Finished Jun 25 05:59:11 PM PDT 24
Peak memory 201932 kb
Host smart-bb8e55d3-173e-46ac-b1ce-adc56cc903fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952878481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.2952878481
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2164595860
Short name T686
Test name
Test status
Simulation time 497964402429 ps
CPU time 555.15 seconds
Started Jun 25 05:53:14 PM PDT 24
Finished Jun 25 06:02:30 PM PDT 24
Peak memory 201840 kb
Host smart-bdc6ce62-7acc-4f69-b02f-a60b337d3683
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164595860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2164595860
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.1372087787
Short name T614
Test name
Test status
Simulation time 179552432471 ps
CPU time 71.83 seconds
Started Jun 25 05:53:13 PM PDT 24
Finished Jun 25 05:54:26 PM PDT 24
Peak memory 201900 kb
Host smart-dccd5de0-c51a-43eb-b36a-c28d594ba152
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372087787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.1372087787
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2373553429
Short name T367
Test name
Test status
Simulation time 599528789980 ps
CPU time 354.87 seconds
Started Jun 25 05:53:16 PM PDT 24
Finished Jun 25 05:59:11 PM PDT 24
Peak memory 201904 kb
Host smart-48746706-5b31-4d45-9302-7e67c07c7e2e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373553429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.2373553429
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2442916209
Short name T487
Test name
Test status
Simulation time 90244800539 ps
CPU time 302.79 seconds
Started Jun 25 05:53:13 PM PDT 24
Finished Jun 25 05:58:16 PM PDT 24
Peak memory 202248 kb
Host smart-e3103dd1-3e39-4cfb-8cd4-d10f4c2e65e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442916209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2442916209
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3857466472
Short name T735
Test name
Test status
Simulation time 33439960196 ps
CPU time 13.5 seconds
Started Jun 25 05:53:13 PM PDT 24
Finished Jun 25 05:53:28 PM PDT 24
Peak memory 201676 kb
Host smart-fc640874-2991-4306-8809-7acd5ca59b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857466472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3857466472
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.1963567088
Short name T515
Test name
Test status
Simulation time 5095956315 ps
CPU time 12.76 seconds
Started Jun 25 05:53:15 PM PDT 24
Finished Jun 25 05:53:28 PM PDT 24
Peak memory 201668 kb
Host smart-82f27c01-dcec-4296-8d62-2f967b1b3408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963567088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1963567088
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3083691253
Short name T570
Test name
Test status
Simulation time 5927907802 ps
CPU time 4.41 seconds
Started Jun 25 05:53:01 PM PDT 24
Finished Jun 25 05:53:06 PM PDT 24
Peak memory 201692 kb
Host smart-2a67b247-95a0-44f5-8e03-d93292d32e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083691253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3083691253
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1440862025
Short name T555
Test name
Test status
Simulation time 491553555 ps
CPU time 0.91 seconds
Started Jun 25 05:53:18 PM PDT 24
Finished Jun 25 05:53:19 PM PDT 24
Peak memory 201608 kb
Host smart-da08b443-4e52-4b32-89d5-b55f8d51683a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440862025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1440862025
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.1850565609
Short name T604
Test name
Test status
Simulation time 162497672208 ps
CPU time 361.28 seconds
Started Jun 25 05:53:19 PM PDT 24
Finished Jun 25 05:59:21 PM PDT 24
Peak memory 201860 kb
Host smart-4153eaf9-64b5-428e-a498-d3e1376f7245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850565609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.1850565609
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.2262634575
Short name T128
Test name
Test status
Simulation time 332911891280 ps
CPU time 749.18 seconds
Started Jun 25 05:53:18 PM PDT 24
Finished Jun 25 06:05:48 PM PDT 24
Peak memory 201920 kb
Host smart-272f3033-186a-4fc3-a2d0-32b5265ee8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262634575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.2262634575
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.4122735317
Short name T425
Test name
Test status
Simulation time 322624633715 ps
CPU time 161.25 seconds
Started Jun 25 05:53:16 PM PDT 24
Finished Jun 25 05:55:58 PM PDT 24
Peak memory 201848 kb
Host smart-f3626b43-1d13-42ef-b229-aba011d4629c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122735317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.4122735317
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.2190068012
Short name T480
Test name
Test status
Simulation time 493248732222 ps
CPU time 265.14 seconds
Started Jun 25 05:53:17 PM PDT 24
Finished Jun 25 05:57:43 PM PDT 24
Peak memory 201872 kb
Host smart-1c3b4c6d-a878-4a0f-ae9d-69a300d54a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190068012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2190068012
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.3568644846
Short name T180
Test name
Test status
Simulation time 479970156680 ps
CPU time 1174.21 seconds
Started Jun 25 05:53:16 PM PDT 24
Finished Jun 25 06:12:51 PM PDT 24
Peak memory 201852 kb
Host smart-c6c19248-1812-4951-8a8b-0105b1f940a0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568644846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.3568644846
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.2466061756
Short name T546
Test name
Test status
Simulation time 391903250660 ps
CPU time 203.32 seconds
Started Jun 25 05:53:17 PM PDT 24
Finished Jun 25 05:56:40 PM PDT 24
Peak memory 201840 kb
Host smart-5ba27913-e7eb-4be1-9d91-f1a2214d76db
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466061756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.2466061756
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.4269170476
Short name T705
Test name
Test status
Simulation time 139506997963 ps
CPU time 734.15 seconds
Started Jun 25 05:53:17 PM PDT 24
Finished Jun 25 06:05:32 PM PDT 24
Peak memory 202240 kb
Host smart-afb0b663-1eea-4d82-b207-6b74b2b97335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269170476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.4269170476
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1772066831
Short name T503
Test name
Test status
Simulation time 42276117581 ps
CPU time 99.25 seconds
Started Jun 25 05:53:16 PM PDT 24
Finished Jun 25 05:54:56 PM PDT 24
Peak memory 201664 kb
Host smart-d6c52db9-44c7-488f-a351-d3b7d70c8546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772066831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1772066831
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.4280108775
Short name T125
Test name
Test status
Simulation time 5209630612 ps
CPU time 1.66 seconds
Started Jun 25 05:53:18 PM PDT 24
Finished Jun 25 05:53:20 PM PDT 24
Peak memory 201652 kb
Host smart-a54a099e-b7f7-4f6c-bbb8-f0996ba92575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280108775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.4280108775
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.3664910909
Short name T722
Test name
Test status
Simulation time 5999681878 ps
CPU time 4.57 seconds
Started Jun 25 05:53:18 PM PDT 24
Finished Jun 25 05:53:24 PM PDT 24
Peak memory 201660 kb
Host smart-aaeaaab5-4931-4794-a274-81765423e5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664910909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.3664910909
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.1472206214
Short name T334
Test name
Test status
Simulation time 174260096252 ps
CPU time 191.19 seconds
Started Jun 25 05:53:18 PM PDT 24
Finished Jun 25 05:56:29 PM PDT 24
Peak memory 201848 kb
Host smart-df10d65e-e2da-4d5e-ab5d-04d0b252ddea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472206214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.1472206214
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.186931344
Short name T18
Test name
Test status
Simulation time 174761847928 ps
CPU time 145.64 seconds
Started Jun 25 05:53:17 PM PDT 24
Finished Jun 25 05:55:43 PM PDT 24
Peak memory 210500 kb
Host smart-c865a0ae-61a7-46de-ac06-710062e67407
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186931344 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.186931344
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.847892723
Short name T606
Test name
Test status
Simulation time 329278496 ps
CPU time 0.89 seconds
Started Jun 25 05:53:31 PM PDT 24
Finished Jun 25 05:53:33 PM PDT 24
Peak memory 201616 kb
Host smart-b816fc85-99ec-46c2-9725-0f0af76d62d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847892723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.847892723
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.164996692
Short name T108
Test name
Test status
Simulation time 332219727447 ps
CPU time 89.63 seconds
Started Jun 25 05:53:26 PM PDT 24
Finished Jun 25 05:54:57 PM PDT 24
Peak memory 201936 kb
Host smart-9fca4d2e-fd81-46f6-8367-5224638609bc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164996692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gati
ng.164996692
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1326495542
Short name T253
Test name
Test status
Simulation time 166619987104 ps
CPU time 183.51 seconds
Started Jun 25 05:53:26 PM PDT 24
Finished Jun 25 05:56:30 PM PDT 24
Peak memory 201896 kb
Host smart-d59d1d5b-9047-45a6-abbb-1b311b434526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326495542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1326495542
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3093038072
Short name T777
Test name
Test status
Simulation time 336135203252 ps
CPU time 719 seconds
Started Jun 25 05:53:22 PM PDT 24
Finished Jun 25 06:05:22 PM PDT 24
Peak memory 201828 kb
Host smart-b7079b4c-f5ed-45d2-ad04-599ee4f203de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093038072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.3093038072
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.2670935533
Short name T598
Test name
Test status
Simulation time 170997289244 ps
CPU time 383.21 seconds
Started Jun 25 05:53:23 PM PDT 24
Finished Jun 25 05:59:48 PM PDT 24
Peak memory 201928 kb
Host smart-086d58f7-9ffa-4e80-8d64-622ca03464f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670935533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.2670935533
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.4072482918
Short name T647
Test name
Test status
Simulation time 328879319387 ps
CPU time 204.28 seconds
Started Jun 25 05:53:24 PM PDT 24
Finished Jun 25 05:56:49 PM PDT 24
Peak memory 202084 kb
Host smart-2bad3dd7-c328-41e3-8502-75efdba9dda9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072482918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.4072482918
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.3856180549
Short name T279
Test name
Test status
Simulation time 167219041858 ps
CPU time 96.76 seconds
Started Jun 25 05:53:24 PM PDT 24
Finished Jun 25 05:55:02 PM PDT 24
Peak memory 201940 kb
Host smart-19e3e7b8-35a4-443a-9901-c8f0f37f9595
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856180549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.3856180549
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.763935504
Short name T498
Test name
Test status
Simulation time 388691256412 ps
CPU time 80.62 seconds
Started Jun 25 05:53:22 PM PDT 24
Finished Jun 25 05:54:43 PM PDT 24
Peak memory 201864 kb
Host smart-225985b4-3213-4090-aff1-9d83eea5b85b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763935504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
adc_ctrl_filters_wakeup_fixed.763935504
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.2314711281
Short name T592
Test name
Test status
Simulation time 73469682209 ps
CPU time 379.3 seconds
Started Jun 25 05:53:25 PM PDT 24
Finished Jun 25 05:59:45 PM PDT 24
Peak memory 202192 kb
Host smart-a6f59b45-aa7f-4f3f-bdc4-06a4e92d3c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314711281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.2314711281
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1068928439
Short name T364
Test name
Test status
Simulation time 43152305957 ps
CPU time 22.75 seconds
Started Jun 25 05:53:24 PM PDT 24
Finished Jun 25 05:53:48 PM PDT 24
Peak memory 201672 kb
Host smart-4059f2e9-4691-43ad-bedf-60cc3cc4ad54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068928439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1068928439
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.4127835563
Short name T678
Test name
Test status
Simulation time 4334603079 ps
CPU time 3.41 seconds
Started Jun 25 05:53:23 PM PDT 24
Finished Jun 25 05:53:27 PM PDT 24
Peak memory 201684 kb
Host smart-8ce2c0a6-2e6c-44e1-bdcb-aaf8d4698693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127835563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.4127835563
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.259477964
Short name T57
Test name
Test status
Simulation time 5601320955 ps
CPU time 4 seconds
Started Jun 25 05:53:23 PM PDT 24
Finished Jun 25 05:53:29 PM PDT 24
Peak memory 201668 kb
Host smart-347b5398-44b7-460a-bc02-fb9e5f192143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259477964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.259477964
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2904189001
Short name T621
Test name
Test status
Simulation time 63764032712 ps
CPU time 99.1 seconds
Started Jun 25 05:53:25 PM PDT 24
Finished Jun 25 05:55:05 PM PDT 24
Peak memory 210508 kb
Host smart-592488a6-93d9-4aff-a8eb-f8568b41dfeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904189001 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2904189001
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.3412859831
Short name T466
Test name
Test status
Simulation time 534380619 ps
CPU time 1.23 seconds
Started Jun 25 05:53:38 PM PDT 24
Finished Jun 25 05:53:40 PM PDT 24
Peak memory 201608 kb
Host smart-3e848fa9-0ae0-402b-9637-b207cea9e554
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412859831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3412859831
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.74382392
Short name T312
Test name
Test status
Simulation time 325612111778 ps
CPU time 726.25 seconds
Started Jun 25 05:53:31 PM PDT 24
Finished Jun 25 06:05:38 PM PDT 24
Peak memory 201860 kb
Host smart-6d91fb53-e55f-4f80-9d12-712a2bad54e2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74382392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gatin
g.74382392
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3487549815
Short name T548
Test name
Test status
Simulation time 323639013615 ps
CPU time 387.26 seconds
Started Jun 25 05:53:31 PM PDT 24
Finished Jun 25 05:59:59 PM PDT 24
Peak memory 201864 kb
Host smart-543f08ea-18e9-4684-aa5c-bc2b2ac38614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487549815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3487549815
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.12142229
Short name T586
Test name
Test status
Simulation time 326289540644 ps
CPU time 357.96 seconds
Started Jun 25 05:53:28 PM PDT 24
Finished Jun 25 05:59:27 PM PDT 24
Peak memory 201872 kb
Host smart-03c218ea-9d65-470f-bfcf-b1be011b74b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12142229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.12142229
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1858357870
Short name T706
Test name
Test status
Simulation time 493272159200 ps
CPU time 299.71 seconds
Started Jun 25 05:53:31 PM PDT 24
Finished Jun 25 05:58:32 PM PDT 24
Peak memory 201916 kb
Host smart-5642f000-a90a-47ad-a595-c6c048b88bd8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858357870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.1858357870
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2975416042
Short name T769
Test name
Test status
Simulation time 168269161326 ps
CPU time 54.74 seconds
Started Jun 25 05:53:31 PM PDT 24
Finished Jun 25 05:54:27 PM PDT 24
Peak memory 201912 kb
Host smart-87915c80-e04a-4d24-bdc3-688200d5be3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975416042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2975416042
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.2589956445
Short name T531
Test name
Test status
Simulation time 326152650887 ps
CPU time 172.85 seconds
Started Jun 25 05:53:30 PM PDT 24
Finished Jun 25 05:56:24 PM PDT 24
Peak memory 201832 kb
Host smart-eda4fe66-b04e-41ba-bc05-e96340d2f809
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589956445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.2589956445
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.1106554437
Short name T123
Test name
Test status
Simulation time 197972211599 ps
CPU time 203.53 seconds
Started Jun 25 05:53:30 PM PDT 24
Finished Jun 25 05:56:54 PM PDT 24
Peak memory 201964 kb
Host smart-439908df-86ba-47f8-b043-2e4ae0eb5d50
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106554437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.1106554437
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2616577805
Short name T732
Test name
Test status
Simulation time 405887620796 ps
CPU time 105.56 seconds
Started Jun 25 05:53:31 PM PDT 24
Finished Jun 25 05:55:17 PM PDT 24
Peak memory 201756 kb
Host smart-043a8f40-8b80-4059-8269-593c9031e9f4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616577805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.2616577805
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.4201319577
Short name T350
Test name
Test status
Simulation time 109287555141 ps
CPU time 633.32 seconds
Started Jun 25 05:53:31 PM PDT 24
Finished Jun 25 06:04:05 PM PDT 24
Peak memory 202184 kb
Host smart-93edbbae-093d-4404-a5c6-49efca3c11d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201319577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.4201319577
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1184760586
Short name T122
Test name
Test status
Simulation time 41232073572 ps
CPU time 92.06 seconds
Started Jun 25 05:53:29 PM PDT 24
Finished Jun 25 05:55:02 PM PDT 24
Peak memory 201648 kb
Host smart-3a3a42f7-6783-46d9-8632-42d5a318bc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184760586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1184760586
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1138129557
Short name T501
Test name
Test status
Simulation time 3312507065 ps
CPU time 4.14 seconds
Started Jun 25 05:53:30 PM PDT 24
Finished Jun 25 05:53:35 PM PDT 24
Peak memory 201664 kb
Host smart-747bab41-77cc-4677-9c1f-e72d83d2ea3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138129557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1138129557
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.2847937262
Short name T537
Test name
Test status
Simulation time 5775292415 ps
CPU time 4.44 seconds
Started Jun 25 05:53:32 PM PDT 24
Finished Jun 25 05:53:37 PM PDT 24
Peak memory 201656 kb
Host smart-88a37107-7c6c-48e7-bc9b-5b32cc94543e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847937262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2847937262
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.337169652
Short name T39
Test name
Test status
Simulation time 244694875075 ps
CPU time 777.77 seconds
Started Jun 25 05:53:39 PM PDT 24
Finished Jun 25 06:06:37 PM PDT 24
Peak memory 202148 kb
Host smart-bf78fdb0-ee6f-4cf7-97f7-9b73c367d762
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337169652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.
337169652
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2782325575
Short name T13
Test name
Test status
Simulation time 212946990836 ps
CPU time 190.29 seconds
Started Jun 25 05:53:30 PM PDT 24
Finished Jun 25 05:56:41 PM PDT 24
Peak memory 217756 kb
Host smart-c2648299-729d-4eaa-98b7-b90ab688f689
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782325575 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.2782325575
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1991714853
Short name T745
Test name
Test status
Simulation time 331385972 ps
CPU time 0.74 seconds
Started Jun 25 05:53:56 PM PDT 24
Finished Jun 25 05:53:57 PM PDT 24
Peak memory 201624 kb
Host smart-b7f8b32c-4d26-43e3-98f8-0f47bbf49f3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991714853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1991714853
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.3446502106
Short name T317
Test name
Test status
Simulation time 519622096307 ps
CPU time 629.47 seconds
Started Jun 25 05:53:57 PM PDT 24
Finished Jun 25 06:04:27 PM PDT 24
Peak memory 201988 kb
Host smart-d4540199-f7e2-4f79-baaa-6cb85621d03d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446502106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.3446502106
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.2557650989
Short name T251
Test name
Test status
Simulation time 500047302854 ps
CPU time 1178.87 seconds
Started Jun 25 05:53:58 PM PDT 24
Finished Jun 25 06:13:37 PM PDT 24
Peak memory 201952 kb
Host smart-b245ed5f-5ca9-4ed1-b227-2030bd2dd3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557650989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.2557650989
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.1603536109
Short name T517
Test name
Test status
Simulation time 331266739394 ps
CPU time 762.13 seconds
Started Jun 25 05:53:40 PM PDT 24
Finished Jun 25 06:06:22 PM PDT 24
Peak memory 201944 kb
Host smart-ed9705c3-e7ab-4f82-ae9c-c1c4624f54e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603536109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.1603536109
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3453678412
Short name T693
Test name
Test status
Simulation time 161133301071 ps
CPU time 86.9 seconds
Started Jun 25 05:53:55 PM PDT 24
Finished Jun 25 05:55:23 PM PDT 24
Peak memory 201828 kb
Host smart-891ce56a-4247-4370-82f1-1736c0ed9db3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453678412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.3453678412
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.2116280794
Short name T770
Test name
Test status
Simulation time 317801649111 ps
CPU time 324.37 seconds
Started Jun 25 05:53:37 PM PDT 24
Finished Jun 25 05:59:02 PM PDT 24
Peak memory 201948 kb
Host smart-50cbf27b-6d34-4921-b3d7-c54a8e2347df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116280794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.2116280794
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.996114136
Short name T448
Test name
Test status
Simulation time 485991055457 ps
CPU time 543.94 seconds
Started Jun 25 05:53:38 PM PDT 24
Finished Jun 25 06:02:43 PM PDT 24
Peak memory 201924 kb
Host smart-d14fe234-d531-4202-a5cc-8e91c1fe13e6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=996114136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixe
d.996114136
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.1718316943
Short name T734
Test name
Test status
Simulation time 204114353854 ps
CPU time 38.18 seconds
Started Jun 25 05:53:56 PM PDT 24
Finished Jun 25 05:54:35 PM PDT 24
Peak memory 201928 kb
Host smart-c6320254-88d5-4d60-86c2-28d19b427b85
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718316943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.1718316943
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.1834958333
Short name T509
Test name
Test status
Simulation time 212342437981 ps
CPU time 51.99 seconds
Started Jun 25 05:53:57 PM PDT 24
Finished Jun 25 05:54:49 PM PDT 24
Peak memory 201856 kb
Host smart-3070c7ec-4d0d-49a2-9566-7c3223139169
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834958333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.1834958333
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2908366903
Short name T349
Test name
Test status
Simulation time 80868240073 ps
CPU time 401.63 seconds
Started Jun 25 05:53:56 PM PDT 24
Finished Jun 25 06:00:39 PM PDT 24
Peak memory 202176 kb
Host smart-84d59a18-7a1a-4af6-8e2c-6720af3dd8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908366903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2908366903
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.4164316409
Short name T645
Test name
Test status
Simulation time 45762847820 ps
CPU time 95.01 seconds
Started Jun 25 05:54:04 PM PDT 24
Finished Jun 25 05:55:40 PM PDT 24
Peak memory 201692 kb
Host smart-0fd8445f-dedc-4a03-9561-358e3deb2952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164316409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.4164316409
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.2741949276
Short name T510
Test name
Test status
Simulation time 3293414321 ps
CPU time 4.81 seconds
Started Jun 25 05:54:04 PM PDT 24
Finished Jun 25 05:54:09 PM PDT 24
Peak memory 201664 kb
Host smart-48826f1e-1d17-451c-ac8e-e86e1b3ee18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741949276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.2741949276
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.3221463637
Short name T585
Test name
Test status
Simulation time 5918786432 ps
CPU time 4.21 seconds
Started Jun 25 05:53:38 PM PDT 24
Finished Jun 25 05:53:43 PM PDT 24
Peak memory 201672 kb
Host smart-cf3024f0-f266-4fc2-87cd-f09bc21ce475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221463637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3221463637
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3843459702
Short name T789
Test name
Test status
Simulation time 78524797794 ps
CPU time 181.82 seconds
Started Jun 25 05:54:08 PM PDT 24
Finished Jun 25 05:57:10 PM PDT 24
Peak memory 210548 kb
Host smart-c4e47166-6d9e-4369-a50e-c44881cfbd63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843459702 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.3843459702
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.812578587
Short name T618
Test name
Test status
Simulation time 341868865 ps
CPU time 0.98 seconds
Started Jun 25 05:54:06 PM PDT 24
Finished Jun 25 05:54:07 PM PDT 24
Peak memory 201600 kb
Host smart-8f702fbe-a94c-4fad-a406-7d0261e1759f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812578587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.812578587
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.409983368
Short name T791
Test name
Test status
Simulation time 333333363195 ps
CPU time 772.37 seconds
Started Jun 25 05:53:56 PM PDT 24
Finished Jun 25 06:06:50 PM PDT 24
Peak memory 201860 kb
Host smart-09fc204b-99ce-4b73-9581-c32bbd0e0b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409983368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.409983368
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.2620343334
Short name T496
Test name
Test status
Simulation time 166710943964 ps
CPU time 191.18 seconds
Started Jun 25 05:53:56 PM PDT 24
Finished Jun 25 05:57:08 PM PDT 24
Peak memory 201832 kb
Host smart-70f5d39f-edd2-42f2-9899-30bd24a25c98
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620343334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.2620343334
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.385280736
Short name T486
Test name
Test status
Simulation time 492236508007 ps
CPU time 1045.7 seconds
Started Jun 25 05:53:57 PM PDT 24
Finished Jun 25 06:11:23 PM PDT 24
Peak memory 201852 kb
Host smart-1ac65be2-f76d-4962-b8ac-2e32f81de1da
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=385280736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixe
d.385280736
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.2136555256
Short name T635
Test name
Test status
Simulation time 537913319777 ps
CPU time 1230.56 seconds
Started Jun 25 05:54:05 PM PDT 24
Finished Jun 25 06:14:36 PM PDT 24
Peak memory 201868 kb
Host smart-f1d5ae87-b1b3-4e95-b29d-f870fc9a0ada
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136555256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.2136555256
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.111881743
Short name T750
Test name
Test status
Simulation time 205318859259 ps
CPU time 238.42 seconds
Started Jun 25 05:53:57 PM PDT 24
Finished Jun 25 05:57:56 PM PDT 24
Peak memory 201872 kb
Host smart-c190ee23-8282-4cae-b2b8-001b90cd0271
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111881743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
adc_ctrl_filters_wakeup_fixed.111881743
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.508284783
Short name T228
Test name
Test status
Simulation time 109393709390 ps
CPU time 461.73 seconds
Started Jun 25 05:54:03 PM PDT 24
Finished Jun 25 06:01:45 PM PDT 24
Peak memory 202196 kb
Host smart-2a76eb0f-9ae2-4377-87ee-6e93f3a5b4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508284783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.508284783
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2123169075
Short name T378
Test name
Test status
Simulation time 44037337091 ps
CPU time 38.98 seconds
Started Jun 25 05:54:09 PM PDT 24
Finished Jun 25 05:54:49 PM PDT 24
Peak memory 201660 kb
Host smart-2d3c0f69-1ad4-457b-9808-74119de084fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123169075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2123169075
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.2346259132
Short name T45
Test name
Test status
Simulation time 4949950875 ps
CPU time 3.51 seconds
Started Jun 25 05:54:04 PM PDT 24
Finished Jun 25 05:54:08 PM PDT 24
Peak memory 201680 kb
Host smart-2561c694-f7ea-4e07-84dc-aa60989d66bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346259132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2346259132
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.4033839435
Short name T397
Test name
Test status
Simulation time 6065008004 ps
CPU time 13.96 seconds
Started Jun 25 05:54:04 PM PDT 24
Finished Jun 25 05:54:19 PM PDT 24
Peak memory 201676 kb
Host smart-efd28efe-7d28-4edf-90eb-aee672d400c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033839435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.4033839435
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.4033834579
Short name T549
Test name
Test status
Simulation time 163869435719 ps
CPU time 488.01 seconds
Started Jun 25 05:54:06 PM PDT 24
Finished Jun 25 06:02:15 PM PDT 24
Peak memory 210400 kb
Host smart-6c9e4ac0-3858-4ad4-91ac-6f8130fb2022
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033834579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.4033834579
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.671502080
Short name T16
Test name
Test status
Simulation time 39334457679 ps
CPU time 73.37 seconds
Started Jun 25 05:54:06 PM PDT 24
Finished Jun 25 05:55:20 PM PDT 24
Peak memory 210260 kb
Host smart-394f1343-128e-4504-91eb-b8d682b4259c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671502080 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.671502080
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.1451941549
Short name T213
Test name
Test status
Simulation time 557055103 ps
CPU time 0.8 seconds
Started Jun 25 05:54:16 PM PDT 24
Finished Jun 25 05:54:17 PM PDT 24
Peak memory 201616 kb
Host smart-695e88c6-5f43-4a88-9af7-8c3edb295e41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451941549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1451941549
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.1850677029
Short name T11
Test name
Test status
Simulation time 496670677031 ps
CPU time 308.15 seconds
Started Jun 25 05:54:05 PM PDT 24
Finished Jun 25 05:59:14 PM PDT 24
Peak memory 201864 kb
Host smart-b0f60234-8b35-445e-94c6-a83765d9442c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850677029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1850677029
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1451883675
Short name T393
Test name
Test status
Simulation time 495836582975 ps
CPU time 946.52 seconds
Started Jun 25 05:54:10 PM PDT 24
Finished Jun 25 06:09:57 PM PDT 24
Peak memory 201864 kb
Host smart-e7025271-0258-4e1d-99ec-cb25b2db9fe5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451883675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1451883675
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.465048167
Short name T744
Test name
Test status
Simulation time 471798317153 ps
CPU time 253.83 seconds
Started Jun 25 05:54:05 PM PDT 24
Finished Jun 25 05:58:20 PM PDT 24
Peak memory 201888 kb
Host smart-42d2ea10-c817-4e07-bda0-314568be840d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465048167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.465048167
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.2427230406
Short name T407
Test name
Test status
Simulation time 493121330073 ps
CPU time 281.9 seconds
Started Jun 25 05:54:03 PM PDT 24
Finished Jun 25 05:58:45 PM PDT 24
Peak memory 201876 kb
Host smart-a37369d8-10a0-4c20-8d61-1c13587f38e5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427230406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.2427230406
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.760431952
Short name T730
Test name
Test status
Simulation time 546980483882 ps
CPU time 215.6 seconds
Started Jun 25 05:54:09 PM PDT 24
Finished Jun 25 05:57:46 PM PDT 24
Peak memory 201936 kb
Host smart-cfe9e411-b9fa-4c63-b6c2-402f92833ae4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760431952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_
wakeup.760431952
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.2053548313
Short name T640
Test name
Test status
Simulation time 391005396353 ps
CPU time 859.51 seconds
Started Jun 25 05:54:11 PM PDT 24
Finished Jun 25 06:08:31 PM PDT 24
Peak memory 201840 kb
Host smart-cb0c8ad8-dad7-47e5-a670-356747b29c4e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053548313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.2053548313
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3039878354
Short name T473
Test name
Test status
Simulation time 92621540377 ps
CPU time 492.78 seconds
Started Jun 25 05:54:10 PM PDT 24
Finished Jun 25 06:02:24 PM PDT 24
Peak memory 202180 kb
Host smart-c5a958e9-dcac-40f9-9bf2-3378d6ef2661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039878354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3039878354
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1490575171
Short name T672
Test name
Test status
Simulation time 40236661275 ps
CPU time 83.28 seconds
Started Jun 25 05:54:11 PM PDT 24
Finished Jun 25 05:55:35 PM PDT 24
Peak memory 201664 kb
Host smart-ad2cb8df-86bc-44a9-82bc-802693d353b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490575171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1490575171
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.894977452
Short name T24
Test name
Test status
Simulation time 3022730334 ps
CPU time 2.45 seconds
Started Jun 25 05:54:10 PM PDT 24
Finished Jun 25 05:54:13 PM PDT 24
Peak memory 201664 kb
Host smart-7606846d-577f-4bde-bfe8-564ee84562c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894977452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.894977452
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.3829273287
Short name T527
Test name
Test status
Simulation time 5902817267 ps
CPU time 4.55 seconds
Started Jun 25 05:54:03 PM PDT 24
Finished Jun 25 05:54:08 PM PDT 24
Peak memory 201644 kb
Host smart-3f9806b5-a115-4663-a7a6-df72300a2558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829273287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.3829273287
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2449664785
Short name T63
Test name
Test status
Simulation time 173096953132 ps
CPU time 97.1 seconds
Started Jun 25 05:54:08 PM PDT 24
Finished Jun 25 05:55:46 PM PDT 24
Peak memory 210192 kb
Host smart-52bcc076-c815-420f-9b4c-19b3f8637b9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449664785 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.2449664785
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1115819611
Short name T701
Test name
Test status
Simulation time 365686367 ps
CPU time 1.03 seconds
Started Jun 25 05:54:26 PM PDT 24
Finished Jun 25 05:54:27 PM PDT 24
Peak memory 201608 kb
Host smart-2364de34-ca07-4a53-a26c-8a986fd66507
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115819611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1115819611
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.1827384560
Short name T330
Test name
Test status
Simulation time 353349800633 ps
CPU time 422.89 seconds
Started Jun 25 05:54:15 PM PDT 24
Finished Jun 25 06:01:19 PM PDT 24
Peak memory 201868 kb
Host smart-95472bb8-801a-41f5-963d-5c004cb17823
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827384560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.1827384560
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3006487728
Short name T492
Test name
Test status
Simulation time 326024603224 ps
CPU time 362.78 seconds
Started Jun 25 05:54:18 PM PDT 24
Finished Jun 25 06:00:21 PM PDT 24
Peak memory 201828 kb
Host smart-129a354e-e3dc-41f0-9834-6c9c54638be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006487728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3006487728
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1194819076
Short name T298
Test name
Test status
Simulation time 323934921089 ps
CPU time 771.34 seconds
Started Jun 25 05:54:15 PM PDT 24
Finished Jun 25 06:07:07 PM PDT 24
Peak memory 201948 kb
Host smart-38ac23ff-a035-4c76-87c3-5683d571dc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194819076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1194819076
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1702922573
Short name T718
Test name
Test status
Simulation time 161667601252 ps
CPU time 365.28 seconds
Started Jun 25 05:54:19 PM PDT 24
Finished Jun 25 06:00:24 PM PDT 24
Peak memory 201832 kb
Host smart-881e808c-f914-4c6b-b2f3-4f0098cc55de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702922573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1702922573
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.861953679
Short name T670
Test name
Test status
Simulation time 325770064225 ps
CPU time 758.78 seconds
Started Jun 25 05:54:18 PM PDT 24
Finished Jun 25 06:06:57 PM PDT 24
Peak memory 201832 kb
Host smart-ff6702b8-1f43-49cf-9fdd-ffdf0a6e6c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861953679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.861953679
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.808107025
Short name T424
Test name
Test status
Simulation time 168572540194 ps
CPU time 347.89 seconds
Started Jun 25 05:54:15 PM PDT 24
Finished Jun 25 06:00:04 PM PDT 24
Peak memory 201852 kb
Host smart-03cef3b7-326f-4b63-a98e-8799b3944afd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=808107025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.808107025
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.2851124614
Short name T752
Test name
Test status
Simulation time 179335962177 ps
CPU time 100.88 seconds
Started Jun 25 05:54:18 PM PDT 24
Finished Jun 25 05:55:59 PM PDT 24
Peak memory 201928 kb
Host smart-964740de-3365-4c72-8906-236cf8764201
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851124614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.2851124614
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.247737616
Short name T383
Test name
Test status
Simulation time 395023124434 ps
CPU time 415.16 seconds
Started Jun 25 05:54:17 PM PDT 24
Finished Jun 25 06:01:13 PM PDT 24
Peak memory 201864 kb
Host smart-0cf4694b-be46-44f5-8f61-c253dddd7ba6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247737616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
adc_ctrl_filters_wakeup_fixed.247737616
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.859363041
Short name T376
Test name
Test status
Simulation time 31418041704 ps
CPU time 17.24 seconds
Started Jun 25 05:54:26 PM PDT 24
Finished Jun 25 05:54:44 PM PDT 24
Peak memory 201688 kb
Host smart-39f82854-e106-49b8-8f79-8a98ef9f5ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859363041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.859363041
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3694123216
Short name T716
Test name
Test status
Simulation time 4111051596 ps
CPU time 9.76 seconds
Started Jun 25 05:54:25 PM PDT 24
Finished Jun 25 05:54:35 PM PDT 24
Peak memory 201644 kb
Host smart-3336bc5d-f716-4dcb-96b7-8e8af33c7edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694123216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3694123216
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.4095196268
Short name T643
Test name
Test status
Simulation time 6035562771 ps
CPU time 4.54 seconds
Started Jun 25 05:54:17 PM PDT 24
Finished Jun 25 05:54:22 PM PDT 24
Peak memory 201680 kb
Host smart-34bda2c2-540a-402e-a19c-b346de995369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095196268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.4095196268
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.689083629
Short name T309
Test name
Test status
Simulation time 65264849475 ps
CPU time 71.81 seconds
Started Jun 25 05:54:23 PM PDT 24
Finished Jun 25 05:55:36 PM PDT 24
Peak memory 210216 kb
Host smart-495ba665-e3c7-4c78-9737-67dfbac97112
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689083629 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.689083629
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.655929706
Short name T386
Test name
Test status
Simulation time 339293070 ps
CPU time 1.4 seconds
Started Jun 25 05:52:01 PM PDT 24
Finished Jun 25 05:52:04 PM PDT 24
Peak memory 201612 kb
Host smart-0bc202a7-05c0-41df-bb0b-57b98d0d8e05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655929706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.655929706
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1772154300
Short name T775
Test name
Test status
Simulation time 534179793653 ps
CPU time 264.67 seconds
Started Jun 25 05:52:00 PM PDT 24
Finished Jun 25 05:56:27 PM PDT 24
Peak memory 201916 kb
Host smart-f80b8c92-9318-472d-92c6-8721b707fb9a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772154300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1772154300
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2699730401
Short name T169
Test name
Test status
Simulation time 494033399359 ps
CPU time 565.66 seconds
Started Jun 25 05:52:01 PM PDT 24
Finished Jun 25 06:01:29 PM PDT 24
Peak memory 201840 kb
Host smart-25b3c869-e20b-4bbc-ad49-f96187a02628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699730401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2699730401
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.4180306698
Short name T514
Test name
Test status
Simulation time 482227464473 ps
CPU time 1053.92 seconds
Started Jun 25 05:51:58 PM PDT 24
Finished Jun 25 06:09:34 PM PDT 24
Peak memory 201856 kb
Host smart-acfedbec-1a8e-4a0f-95bf-dbabeeff2af3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180306698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.4180306698
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.601274463
Short name T172
Test name
Test status
Simulation time 319726120426 ps
CPU time 210.04 seconds
Started Jun 25 05:52:01 PM PDT 24
Finished Jun 25 05:55:32 PM PDT 24
Peak memory 201824 kb
Host smart-8e0e1478-2a17-492c-8cad-94007f90c06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601274463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.601274463
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3565419801
Short name T689
Test name
Test status
Simulation time 169996962700 ps
CPU time 375.61 seconds
Started Jun 25 05:52:03 PM PDT 24
Finished Jun 25 05:58:20 PM PDT 24
Peak memory 201860 kb
Host smart-ab612978-5a2a-4654-9bef-5c9f195976fe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565419801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3565419801
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.225136852
Short name T565
Test name
Test status
Simulation time 216677809033 ps
CPU time 132.14 seconds
Started Jun 25 05:52:04 PM PDT 24
Finished Jun 25 05:54:18 PM PDT 24
Peak memory 201864 kb
Host smart-f8e21c52-d503-4df6-bb2a-14af71e4406c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225136852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_w
akeup.225136852
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1190989518
Short name T788
Test name
Test status
Simulation time 199547475235 ps
CPU time 413.34 seconds
Started Jun 25 05:51:58 PM PDT 24
Finished Jun 25 05:58:53 PM PDT 24
Peak memory 201868 kb
Host smart-3de2da58-5d57-44dd-b57c-37f4245e1999
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190989518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1190989518
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1527238928
Short name T6
Test name
Test status
Simulation time 124984603712 ps
CPU time 404.45 seconds
Started Jun 25 05:52:04 PM PDT 24
Finished Jun 25 05:58:51 PM PDT 24
Peak memory 202124 kb
Host smart-efc072c5-f652-4ac1-b437-556e2995dd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527238928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1527238928
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.1843320004
Short name T733
Test name
Test status
Simulation time 30583502047 ps
CPU time 66.37 seconds
Started Jun 25 05:52:03 PM PDT 24
Finished Jun 25 05:53:11 PM PDT 24
Peak memory 201660 kb
Host smart-d1a81fe0-2b77-4615-948d-fe9d0e161f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843320004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.1843320004
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.2912982130
Short name T58
Test name
Test status
Simulation time 3704527608 ps
CPU time 9.46 seconds
Started Jun 25 05:52:00 PM PDT 24
Finished Jun 25 05:52:11 PM PDT 24
Peak memory 201796 kb
Host smart-8832935a-f128-4511-8281-1c1f72e250aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912982130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2912982130
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.2416900070
Short name T95
Test name
Test status
Simulation time 4563918027 ps
CPU time 3.42 seconds
Started Jun 25 05:52:01 PM PDT 24
Finished Jun 25 05:52:07 PM PDT 24
Peak memory 217152 kb
Host smart-8aa93bbf-4021-4cd9-a8ef-f9bf4dd67efa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416900070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.2416900070
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1672285981
Short name T430
Test name
Test status
Simulation time 5708151115 ps
CPU time 7.28 seconds
Started Jun 25 05:52:00 PM PDT 24
Finished Jun 25 05:52:09 PM PDT 24
Peak memory 201668 kb
Host smart-0c7acbd4-c94e-4660-b1b9-10ff07ddab52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672285981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1672285981
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.1622431867
Short name T258
Test name
Test status
Simulation time 199066303087 ps
CPU time 51.33 seconds
Started Jun 25 05:52:00 PM PDT 24
Finished Jun 25 05:52:53 PM PDT 24
Peak memory 201880 kb
Host smart-c99228aa-4fb0-4aac-8d60-d372e27830bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622431867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
1622431867
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1220067052
Short name T756
Test name
Test status
Simulation time 78825241420 ps
CPU time 96.02 seconds
Started Jun 25 05:51:59 PM PDT 24
Finished Jun 25 05:53:36 PM PDT 24
Peak memory 210548 kb
Host smart-65c39b34-f4cf-4595-a85e-562d2e9bec47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220067052 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1220067052
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2373021573
Short name T679
Test name
Test status
Simulation time 528351978 ps
CPU time 0.91 seconds
Started Jun 25 05:54:39 PM PDT 24
Finished Jun 25 05:54:41 PM PDT 24
Peak memory 201628 kb
Host smart-4fc225eb-1b55-402f-a935-3470616da39c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373021573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2373021573
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.1763549351
Short name T311
Test name
Test status
Simulation time 486910718007 ps
CPU time 265.51 seconds
Started Jun 25 05:54:26 PM PDT 24
Finished Jun 25 05:58:52 PM PDT 24
Peak memory 201864 kb
Host smart-5ec62005-3a17-4b29-a2b0-a5f2f8c6a8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763549351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1763549351
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2161912844
Short name T539
Test name
Test status
Simulation time 329738208951 ps
CPU time 193.05 seconds
Started Jun 25 05:54:34 PM PDT 24
Finished Jun 25 05:57:48 PM PDT 24
Peak memory 201844 kb
Host smart-29768acf-4aed-48f2-890b-69a3288ce457
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161912844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2161912844
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.1305420283
Short name T48
Test name
Test status
Simulation time 323849772095 ps
CPU time 76.01 seconds
Started Jun 25 05:54:24 PM PDT 24
Finished Jun 25 05:55:41 PM PDT 24
Peak memory 201916 kb
Host smart-18ebfa1f-62de-473e-bac0-d6a15267cb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305420283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.1305420283
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2632655089
Short name T557
Test name
Test status
Simulation time 334132892393 ps
CPU time 779.04 seconds
Started Jun 25 05:54:25 PM PDT 24
Finished Jun 25 06:07:25 PM PDT 24
Peak memory 202088 kb
Host smart-06672d76-4366-48eb-a8ab-c4fe7b47f93d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632655089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2632655089
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2180548993
Short name T637
Test name
Test status
Simulation time 181188460633 ps
CPU time 68.72 seconds
Started Jun 25 05:54:31 PM PDT 24
Finished Jun 25 05:55:41 PM PDT 24
Peak memory 201928 kb
Host smart-13b366a3-02cd-44ba-b00e-b83b8f47419a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180548993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2180548993
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3094587405
Short name T589
Test name
Test status
Simulation time 579805739725 ps
CPU time 299.37 seconds
Started Jun 25 05:54:32 PM PDT 24
Finished Jun 25 05:59:32 PM PDT 24
Peak memory 201876 kb
Host smart-4944d8fd-e6cf-4320-9cbe-739e41894f83
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094587405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3094587405
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.1966400579
Short name T66
Test name
Test status
Simulation time 95951819710 ps
CPU time 500.9 seconds
Started Jun 25 05:54:32 PM PDT 24
Finished Jun 25 06:02:53 PM PDT 24
Peak memory 202200 kb
Host smart-700118b8-1de3-4970-9639-854c3c487cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966400579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1966400579
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.1989277355
Short name T489
Test name
Test status
Simulation time 25101432354 ps
CPU time 61.25 seconds
Started Jun 25 05:54:32 PM PDT 24
Finished Jun 25 05:55:35 PM PDT 24
Peak memory 201668 kb
Host smart-31868a5d-4c2c-4e1c-b7c9-3e1395434ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989277355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.1989277355
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.1118677830
Short name T521
Test name
Test status
Simulation time 5231528494 ps
CPU time 6.41 seconds
Started Jun 25 05:54:31 PM PDT 24
Finished Jun 25 05:54:38 PM PDT 24
Peak memory 201660 kb
Host smart-c85aa8d3-03d7-42bf-9587-4794c26e09b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118677830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1118677830
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.1589876988
Short name T445
Test name
Test status
Simulation time 5910934017 ps
CPU time 14.43 seconds
Started Jun 25 05:54:22 PM PDT 24
Finished Jun 25 05:54:37 PM PDT 24
Peak memory 201656 kb
Host smart-487ce02e-ec1c-4a53-bc4c-c91d1ec41117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589876988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1589876988
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3217734966
Short name T28
Test name
Test status
Simulation time 195429035454 ps
CPU time 447.63 seconds
Started Jun 25 05:54:45 PM PDT 24
Finished Jun 25 06:02:13 PM PDT 24
Peak memory 202108 kb
Host smart-46d086a3-d7c1-4957-b3c9-3fe2bc0b4e67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217734966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3217734966
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2008679316
Short name T46
Test name
Test status
Simulation time 69863153614 ps
CPU time 160.36 seconds
Started Jun 25 05:54:34 PM PDT 24
Finished Jun 25 05:57:15 PM PDT 24
Peak memory 210268 kb
Host smart-d8946b42-d470-49de-a09b-48d987a67071
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008679316 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2008679316
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.576132798
Short name T545
Test name
Test status
Simulation time 546798834 ps
CPU time 0.91 seconds
Started Jun 25 05:54:55 PM PDT 24
Finished Jun 25 05:54:57 PM PDT 24
Peak memory 201600 kb
Host smart-79b3db10-b33d-4068-8c11-804a136c2a7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576132798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.576132798
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3683620182
Short name T220
Test name
Test status
Simulation time 187249330033 ps
CPU time 104.17 seconds
Started Jun 25 05:54:47 PM PDT 24
Finished Jun 25 05:56:32 PM PDT 24
Peak memory 201896 kb
Host smart-65e9e89c-77be-4b65-bf9c-81c6f94db577
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683620182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3683620182
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.3966249369
Short name T189
Test name
Test status
Simulation time 499405385509 ps
CPU time 1132.07 seconds
Started Jun 25 05:54:48 PM PDT 24
Finished Jun 25 06:13:41 PM PDT 24
Peak memory 201868 kb
Host smart-e1c7e95e-9850-460b-ac26-28cf605d2879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966249369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.3966249369
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.6709097
Short name T653
Test name
Test status
Simulation time 337811630885 ps
CPU time 696.33 seconds
Started Jun 25 05:54:48 PM PDT 24
Finished Jun 25 06:06:25 PM PDT 24
Peak memory 201916 kb
Host smart-40b562a0-caab-448a-bc15-ed25952e5fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6709097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.6709097
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.3347388439
Short name T538
Test name
Test status
Simulation time 323581940384 ps
CPU time 190.71 seconds
Started Jun 25 05:54:48 PM PDT 24
Finished Jun 25 05:58:00 PM PDT 24
Peak memory 201824 kb
Host smart-6b8e3f70-1acc-45d0-9e6d-f4c507de643d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347388439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.3347388439
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.1545948335
Short name T759
Test name
Test status
Simulation time 490896922505 ps
CPU time 155.06 seconds
Started Jun 25 05:54:47 PM PDT 24
Finished Jun 25 05:57:23 PM PDT 24
Peak memory 201852 kb
Host smart-49246f01-0cf0-47ff-a464-acda389cb299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545948335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.1545948335
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.873148342
Short name T600
Test name
Test status
Simulation time 331027916135 ps
CPU time 226.77 seconds
Started Jun 25 05:54:48 PM PDT 24
Finished Jun 25 05:58:36 PM PDT 24
Peak memory 201920 kb
Host smart-a56ffd6b-2c0b-4de6-90e7-4b492ce3d330
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=873148342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixe
d.873148342
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.1560734888
Short name T341
Test name
Test status
Simulation time 546535346012 ps
CPU time 1269.34 seconds
Started Jun 25 05:54:48 PM PDT 24
Finished Jun 25 06:15:58 PM PDT 24
Peak memory 201844 kb
Host smart-ad25c37e-b066-4b76-afc9-2fd94f743814
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560734888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.1560734888
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1337080957
Short name T468
Test name
Test status
Simulation time 396483240216 ps
CPU time 867.82 seconds
Started Jun 25 05:54:48 PM PDT 24
Finished Jun 25 06:09:17 PM PDT 24
Peak memory 201852 kb
Host smart-5294da63-ad4c-48cd-91f6-4d07852cb618
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337080957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1337080957
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2113696973
Short name T346
Test name
Test status
Simulation time 101399768449 ps
CPU time 361.19 seconds
Started Jun 25 05:54:49 PM PDT 24
Finished Jun 25 06:00:51 PM PDT 24
Peak memory 202240 kb
Host smart-3482502e-4bc8-481d-b16d-48678196d164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113696973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2113696973
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3701937854
Short name T479
Test name
Test status
Simulation time 46570820470 ps
CPU time 105.52 seconds
Started Jun 25 05:54:47 PM PDT 24
Finished Jun 25 05:56:34 PM PDT 24
Peak memory 201660 kb
Host smart-4beed2d2-001a-4e41-99fb-af6d545fbdf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701937854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3701937854
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.1918044468
Short name T577
Test name
Test status
Simulation time 3095585202 ps
CPU time 8.44 seconds
Started Jun 25 05:54:48 PM PDT 24
Finished Jun 25 05:54:58 PM PDT 24
Peak memory 201656 kb
Host smart-c3528b01-c7fd-458c-8d87-234d0c7f684d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918044468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.1918044468
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.3323278118
Short name T629
Test name
Test status
Simulation time 5979848311 ps
CPU time 14.81 seconds
Started Jun 25 05:54:38 PM PDT 24
Finished Jun 25 05:54:54 PM PDT 24
Peak memory 201656 kb
Host smart-b599c42f-5a69-49d4-821a-f8c6dda58e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323278118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3323278118
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.4207865602
Short name T35
Test name
Test status
Simulation time 275201274980 ps
CPU time 678.8 seconds
Started Jun 25 05:54:56 PM PDT 24
Finished Jun 25 06:06:16 PM PDT 24
Peak memory 210360 kb
Host smart-68312885-9bb0-42cb-b3d4-a5fc0b0af03e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207865602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.4207865602
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2291462965
Short name T20
Test name
Test status
Simulation time 42270468800 ps
CPU time 55.25 seconds
Started Jun 25 05:54:55 PM PDT 24
Finished Jun 25 05:55:51 PM PDT 24
Peak memory 210504 kb
Host smart-de5f50e5-bc0b-46ff-b183-f7fa61c491af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291462965 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2291462965
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.2405284659
Short name T513
Test name
Test status
Simulation time 427452616 ps
CPU time 0.71 seconds
Started Jun 25 05:55:03 PM PDT 24
Finished Jun 25 05:55:04 PM PDT 24
Peak memory 201616 kb
Host smart-c495aedd-6375-498a-a86d-9e0ce42513c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405284659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.2405284659
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.141870971
Short name T188
Test name
Test status
Simulation time 317233584363 ps
CPU time 644.61 seconds
Started Jun 25 05:54:55 PM PDT 24
Finished Jun 25 06:05:41 PM PDT 24
Peak memory 201768 kb
Host smart-2741fc59-9464-4a11-9f13-6f3aafff05f3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141870971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.141870971
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.3236226875
Short name T646
Test name
Test status
Simulation time 333537420960 ps
CPU time 712.45 seconds
Started Jun 25 05:54:55 PM PDT 24
Finished Jun 25 06:06:48 PM PDT 24
Peak memory 201868 kb
Host smart-5e7cf955-c5e0-43ce-9050-dbd361b3cd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236226875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.3236226875
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2385084448
Short name T762
Test name
Test status
Simulation time 330970256457 ps
CPU time 185.39 seconds
Started Jun 25 05:54:56 PM PDT 24
Finished Jun 25 05:58:02 PM PDT 24
Peak memory 201824 kb
Host smart-0258785c-ac98-4289-9d6e-9e3eb4a3f4bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385084448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.2385084448
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.39989543
Short name T690
Test name
Test status
Simulation time 324310420891 ps
CPU time 196.15 seconds
Started Jun 25 05:54:55 PM PDT 24
Finished Jun 25 05:58:12 PM PDT 24
Peak memory 201872 kb
Host smart-7520ec3f-542c-447f-801f-477d62169b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39989543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.39989543
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1969135267
Short name T559
Test name
Test status
Simulation time 159464088073 ps
CPU time 372.55 seconds
Started Jun 25 05:54:55 PM PDT 24
Finished Jun 25 06:01:09 PM PDT 24
Peak memory 201836 kb
Host smart-ae851071-8784-4cd5-b21a-87b824af0556
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969135267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1969135267
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3702974230
Short name T767
Test name
Test status
Simulation time 423283931639 ps
CPU time 1011.03 seconds
Started Jun 25 05:54:55 PM PDT 24
Finished Jun 25 06:11:47 PM PDT 24
Peak memory 201832 kb
Host smart-a043aa4c-8eda-4001-a69c-0776c26db3da
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702974230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.3702974230
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.3243648098
Short name T373
Test name
Test status
Simulation time 71322305811 ps
CPU time 370.78 seconds
Started Jun 25 05:55:03 PM PDT 24
Finished Jun 25 06:01:15 PM PDT 24
Peak memory 202200 kb
Host smart-9b484a07-7565-4902-a59e-50bbcfbc8a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243648098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.3243648098
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.1067956149
Short name T456
Test name
Test status
Simulation time 29609608637 ps
CPU time 17.15 seconds
Started Jun 25 05:55:06 PM PDT 24
Finished Jun 25 05:55:24 PM PDT 24
Peak memory 201660 kb
Host smart-db72a120-1f1e-4ab5-a37d-c0c389d04bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067956149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.1067956149
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.845908595
Short name T602
Test name
Test status
Simulation time 3068900992 ps
CPU time 2.37 seconds
Started Jun 25 05:54:55 PM PDT 24
Finished Jun 25 05:54:59 PM PDT 24
Peak memory 201604 kb
Host smart-99c072b2-8491-420d-ad9c-05630d5ad430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845908595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.845908595
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.1916437979
Short name T649
Test name
Test status
Simulation time 5931481084 ps
CPU time 13.31 seconds
Started Jun 25 05:54:55 PM PDT 24
Finished Jun 25 05:55:09 PM PDT 24
Peak memory 201800 kb
Host smart-e00d4466-512a-4d24-b394-1ae1ea4bee45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916437979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.1916437979
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2687984038
Short name T345
Test name
Test status
Simulation time 2144659541658 ps
CPU time 1500.84 seconds
Started Jun 25 05:55:03 PM PDT 24
Finished Jun 25 06:20:04 PM PDT 24
Peak memory 218628 kb
Host smart-7092b1fb-4879-44cf-bcf2-f8f8e2c29f48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687984038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2687984038
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3144146845
Short name T481
Test name
Test status
Simulation time 53732456338 ps
CPU time 49.44 seconds
Started Jun 25 05:55:04 PM PDT 24
Finished Jun 25 05:55:54 PM PDT 24
Peak memory 210500 kb
Host smart-5ad89474-d23b-4268-b304-9740d887ab64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144146845 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3144146845
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.3147052738
Short name T419
Test name
Test status
Simulation time 429207429 ps
CPU time 1.57 seconds
Started Jun 25 05:55:14 PM PDT 24
Finished Jun 25 05:55:16 PM PDT 24
Peak memory 201608 kb
Host smart-9b14f5ec-7464-49a1-a75f-b1b336813a8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147052738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.3147052738
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.1515438503
Short name T161
Test name
Test status
Simulation time 534774706759 ps
CPU time 552.07 seconds
Started Jun 25 05:55:18 PM PDT 24
Finished Jun 25 06:04:30 PM PDT 24
Peak memory 201836 kb
Host smart-ec4de610-8997-45d1-a8db-1806185e0144
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515438503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.1515438503
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.1245817400
Short name T792
Test name
Test status
Simulation time 163325210254 ps
CPU time 185.08 seconds
Started Jun 25 05:55:04 PM PDT 24
Finished Jun 25 05:58:10 PM PDT 24
Peak memory 201932 kb
Host smart-d986fe0d-d477-4706-89d5-7acd58f10bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245817400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1245817400
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.55506934
Short name T688
Test name
Test status
Simulation time 498137284984 ps
CPU time 1086.87 seconds
Started Jun 25 05:55:04 PM PDT 24
Finished Jun 25 06:13:12 PM PDT 24
Peak memory 201844 kb
Host smart-cebe4a4b-43f7-4b40-8a77-523a4b4a07c8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=55506934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt
_fixed.55506934
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.3184334529
Short name T247
Test name
Test status
Simulation time 165434455447 ps
CPU time 117.91 seconds
Started Jun 25 05:55:02 PM PDT 24
Finished Jun 25 05:57:00 PM PDT 24
Peak memory 201888 kb
Host smart-8b6e046c-5125-46b7-9088-abd863127116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184334529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3184334529
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.273509573
Short name T573
Test name
Test status
Simulation time 158921443673 ps
CPU time 351.29 seconds
Started Jun 25 05:55:06 PM PDT 24
Finished Jun 25 06:00:58 PM PDT 24
Peak memory 201840 kb
Host smart-7dab3348-724e-40ac-a2c5-0b177c0c0d09
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=273509573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixe
d.273509573
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1463599733
Short name T532
Test name
Test status
Simulation time 587358120996 ps
CPU time 630.83 seconds
Started Jun 25 05:55:09 PM PDT 24
Finished Jun 25 06:05:41 PM PDT 24
Peak memory 201840 kb
Host smart-507b120c-0350-4832-bea9-bbe956681c46
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463599733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1463599733
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.360255870
Short name T224
Test name
Test status
Simulation time 116661350694 ps
CPU time 545.01 seconds
Started Jun 25 05:55:18 PM PDT 24
Finished Jun 25 06:04:23 PM PDT 24
Peak memory 202180 kb
Host smart-78747f6a-b400-4cdb-9109-e409d2bd63f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360255870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.360255870
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2224553469
Short name T776
Test name
Test status
Simulation time 26564441608 ps
CPU time 18.61 seconds
Started Jun 25 05:55:18 PM PDT 24
Finished Jun 25 05:55:37 PM PDT 24
Peak memory 201624 kb
Host smart-1e55f769-9d69-433e-911e-155bf6a502f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224553469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2224553469
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1465025393
Short name T505
Test name
Test status
Simulation time 4987308542 ps
CPU time 3.96 seconds
Started Jun 25 05:55:18 PM PDT 24
Finished Jun 25 05:55:22 PM PDT 24
Peak memory 201572 kb
Host smart-462a1b32-b9cb-4281-b84c-03c011a7cefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465025393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1465025393
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.1006419592
Short name T472
Test name
Test status
Simulation time 5991483211 ps
CPU time 13.21 seconds
Started Jun 25 05:55:03 PM PDT 24
Finished Jun 25 05:55:17 PM PDT 24
Peak memory 201656 kb
Host smart-8bbbb893-9150-42a5-87d2-02e119fe5b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006419592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1006419592
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.615857064
Short name T36
Test name
Test status
Simulation time 220522121058 ps
CPU time 510.06 seconds
Started Jun 25 05:55:14 PM PDT 24
Finished Jun 25 06:03:45 PM PDT 24
Peak memory 201848 kb
Host smart-8a7e79c0-4db3-4c4b-baa5-7cec906323ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615857064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
615857064
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1752408540
Short name T652
Test name
Test status
Simulation time 15571601320 ps
CPU time 32.81 seconds
Started Jun 25 05:55:18 PM PDT 24
Finished Jun 25 05:55:52 PM PDT 24
Peak memory 202044 kb
Host smart-425c0b63-0e7f-4ff7-9f47-49caaf884219
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752408540 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.1752408540
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.4135025057
Short name T702
Test name
Test status
Simulation time 302824894 ps
CPU time 1.31 seconds
Started Jun 25 05:55:25 PM PDT 24
Finished Jun 25 05:55:27 PM PDT 24
Peak memory 201628 kb
Host smart-f0a1c8cd-272a-4b37-bb9a-d118e745c66a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135025057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.4135025057
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.2264877100
Short name T191
Test name
Test status
Simulation time 493241428845 ps
CPU time 564.65 seconds
Started Jun 25 05:55:17 PM PDT 24
Finished Jun 25 06:04:42 PM PDT 24
Peak memory 201924 kb
Host smart-03dedf00-822e-4a0f-8c72-a8107c028b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264877100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2264877100
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.4063113478
Short name T433
Test name
Test status
Simulation time 492389937080 ps
CPU time 310.61 seconds
Started Jun 25 05:55:19 PM PDT 24
Finished Jun 25 06:00:30 PM PDT 24
Peak memory 201832 kb
Host smart-87b9aa67-da94-4040-b33c-6abfb63798c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063113478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.4063113478
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.3293534031
Short name T494
Test name
Test status
Simulation time 322840115027 ps
CPU time 731.2 seconds
Started Jun 25 05:55:10 PM PDT 24
Finished Jun 25 06:07:22 PM PDT 24
Peak memory 201856 kb
Host smart-52bd0ca6-bead-4afa-95e6-5d96504001f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293534031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.3293534031
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.1070443449
Short name T398
Test name
Test status
Simulation time 492873827749 ps
CPU time 266.03 seconds
Started Jun 25 05:55:17 PM PDT 24
Finished Jun 25 05:59:44 PM PDT 24
Peak memory 201896 kb
Host smart-7b5706d0-2f3c-48a9-86ed-d5014b33a0dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070443449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.1070443449
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.229129068
Short name T160
Test name
Test status
Simulation time 344302043482 ps
CPU time 422.21 seconds
Started Jun 25 05:55:17 PM PDT 24
Finished Jun 25 06:02:19 PM PDT 24
Peak memory 201860 kb
Host smart-028b1148-f715-4cea-9964-2d41f1ddbe27
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229129068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_
wakeup.229129068
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.374109065
Short name T482
Test name
Test status
Simulation time 615972997951 ps
CPU time 1303.9 seconds
Started Jun 25 05:55:16 PM PDT 24
Finished Jun 25 06:17:01 PM PDT 24
Peak memory 201840 kb
Host smart-2ae51f2e-d8ab-4460-b6d6-ddde604675e5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374109065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
adc_ctrl_filters_wakeup_fixed.374109065
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.3380900381
Short name T226
Test name
Test status
Simulation time 143510748633 ps
CPU time 443.5 seconds
Started Jun 25 05:55:25 PM PDT 24
Finished Jun 25 06:02:49 PM PDT 24
Peak memory 202204 kb
Host smart-ab96e8e8-0cb7-42d4-b8b1-b7eec0a093a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380900381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3380900381
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.1339753961
Short name T639
Test name
Test status
Simulation time 28155465425 ps
CPU time 17.09 seconds
Started Jun 25 05:55:25 PM PDT 24
Finished Jun 25 05:55:43 PM PDT 24
Peak memory 201692 kb
Host smart-9bcb1046-9752-4d9f-a72c-b9925d419b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339753961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.1339753961
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.637876631
Short name T379
Test name
Test status
Simulation time 4937298709 ps
CPU time 3.62 seconds
Started Jun 25 05:55:24 PM PDT 24
Finished Jun 25 05:55:29 PM PDT 24
Peak memory 201680 kb
Host smart-f2d46f4b-4880-4528-8012-bb5eb752198a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637876631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.637876631
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.578232416
Short name T404
Test name
Test status
Simulation time 5676596294 ps
CPU time 7.22 seconds
Started Jun 25 05:55:14 PM PDT 24
Finished Jun 25 05:55:22 PM PDT 24
Peak memory 201660 kb
Host smart-398b9b5c-1cc7-48cc-a081-cbf9de31e0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578232416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.578232416
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.917502707
Short name T129
Test name
Test status
Simulation time 191021721918 ps
CPU time 45.08 seconds
Started Jun 25 05:55:26 PM PDT 24
Finished Jun 25 05:56:11 PM PDT 24
Peak memory 210560 kb
Host smart-2b8a8b10-3d6e-4500-987c-f174afb51c0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917502707 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.917502707
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.473766602
Short name T422
Test name
Test status
Simulation time 501218857 ps
CPU time 0.95 seconds
Started Jun 25 05:55:33 PM PDT 24
Finished Jun 25 05:55:35 PM PDT 24
Peak memory 201612 kb
Host smart-8cfac2ef-90c2-4914-891d-a50c827c08fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473766602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.473766602
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3830268782
Short name T208
Test name
Test status
Simulation time 357891657295 ps
CPU time 208.64 seconds
Started Jun 25 05:55:34 PM PDT 24
Finished Jun 25 05:59:03 PM PDT 24
Peak memory 201936 kb
Host smart-350e5bc2-bb15-4cd7-a74c-2dc5fd3bd288
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830268782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3830268782
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.432433528
Short name T261
Test name
Test status
Simulation time 162023017456 ps
CPU time 88.12 seconds
Started Jun 25 05:55:24 PM PDT 24
Finished Jun 25 05:56:53 PM PDT 24
Peak memory 201864 kb
Host smart-c1944c37-0970-436b-b5df-480640efaf99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432433528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.432433528
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.4035778040
Short name T572
Test name
Test status
Simulation time 331053170497 ps
CPU time 81.06 seconds
Started Jun 25 05:55:27 PM PDT 24
Finished Jun 25 05:56:49 PM PDT 24
Peak memory 201788 kb
Host smart-9498579a-d10e-437b-a8a7-6c02f982b993
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035778040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.4035778040
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.3421988275
Short name T710
Test name
Test status
Simulation time 332486463186 ps
CPU time 195.23 seconds
Started Jun 25 05:55:26 PM PDT 24
Finished Jun 25 05:58:42 PM PDT 24
Peak memory 201916 kb
Host smart-9285f6c2-3aab-433f-83a8-10f0e46187a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421988275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3421988275
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.3462209926
Short name T401
Test name
Test status
Simulation time 159746814376 ps
CPU time 179.36 seconds
Started Jun 25 05:55:24 PM PDT 24
Finished Jun 25 05:58:24 PM PDT 24
Peak memory 201816 kb
Host smart-1bbe0431-c18e-497e-9cae-a4f836bc5bfb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462209926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.3462209926
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.413588171
Short name T707
Test name
Test status
Simulation time 477660140073 ps
CPU time 393.53 seconds
Started Jun 25 05:55:25 PM PDT 24
Finished Jun 25 06:01:59 PM PDT 24
Peak memory 201884 kb
Host smart-6ce18609-d54a-49b7-bca4-f981cb01f63e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413588171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_
wakeup.413588171
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1395408214
Short name T782
Test name
Test status
Simulation time 601216264816 ps
CPU time 337.96 seconds
Started Jun 25 05:55:34 PM PDT 24
Finished Jun 25 06:01:13 PM PDT 24
Peak memory 201892 kb
Host smart-497efc52-6cfc-419f-97bd-ecaf069af8a5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395408214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.1395408214
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1629199541
Short name T738
Test name
Test status
Simulation time 103853182699 ps
CPU time 385.8 seconds
Started Jun 25 05:55:32 PM PDT 24
Finished Jun 25 06:01:59 PM PDT 24
Peak memory 202192 kb
Host smart-bca59e50-c2bf-4ce4-b517-ced6bb509aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629199541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1629199541
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2677144289
Short name T478
Test name
Test status
Simulation time 38677771872 ps
CPU time 23.04 seconds
Started Jun 25 05:55:32 PM PDT 24
Finished Jun 25 05:55:56 PM PDT 24
Peak memory 201660 kb
Host smart-8f4172d4-0471-49ae-b02c-0e43fe7461b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677144289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2677144289
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3435073943
Short name T449
Test name
Test status
Simulation time 3213800124 ps
CPU time 7.84 seconds
Started Jun 25 05:55:34 PM PDT 24
Finished Jun 25 05:55:42 PM PDT 24
Peak memory 201688 kb
Host smart-8d149184-057c-4e22-905a-e29779f15797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435073943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3435073943
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.4054621356
Short name T402
Test name
Test status
Simulation time 5867567838 ps
CPU time 7.34 seconds
Started Jun 25 05:55:27 PM PDT 24
Finished Jun 25 05:55:35 PM PDT 24
Peak memory 201616 kb
Host smart-8dbc06bc-d268-40af-986a-e47bddf534f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054621356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.4054621356
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.1155258019
Short name T265
Test name
Test status
Simulation time 331350726279 ps
CPU time 176.79 seconds
Started Jun 25 05:55:33 PM PDT 24
Finished Jun 25 05:58:30 PM PDT 24
Peak memory 201876 kb
Host smart-8d68e272-9c53-4855-9342-f30c4c985608
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155258019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.1155258019
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.1444875055
Short name T683
Test name
Test status
Simulation time 374303230 ps
CPU time 1.4 seconds
Started Jun 25 05:55:42 PM PDT 24
Finished Jun 25 05:55:44 PM PDT 24
Peak memory 201592 kb
Host smart-85734664-9cfc-4c8b-a49e-cca40c8a9e79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444875055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.1444875055
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.2878352213
Short name T737
Test name
Test status
Simulation time 508762014373 ps
CPU time 1154.26 seconds
Started Jun 25 05:55:42 PM PDT 24
Finished Jun 25 06:14:57 PM PDT 24
Peak memory 201856 kb
Host smart-9cf5ea49-5e65-40e7-bc36-b29f890f8895
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878352213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.2878352213
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3221901403
Short name T499
Test name
Test status
Simulation time 498415945424 ps
CPU time 1200.98 seconds
Started Jun 25 05:55:34 PM PDT 24
Finished Jun 25 06:15:36 PM PDT 24
Peak memory 201940 kb
Host smart-1846971b-0cd9-4ac4-a28b-9c875a315bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221901403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3221901403
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.3485696179
Short name T633
Test name
Test status
Simulation time 503206251549 ps
CPU time 154.1 seconds
Started Jun 25 05:55:33 PM PDT 24
Finished Jun 25 05:58:08 PM PDT 24
Peak memory 201824 kb
Host smart-49f985ff-79bc-4f65-8fb1-489c39681791
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485696179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.3485696179
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.143787919
Short name T324
Test name
Test status
Simulation time 490943296105 ps
CPU time 140.94 seconds
Started Jun 25 05:55:34 PM PDT 24
Finished Jun 25 05:57:56 PM PDT 24
Peak memory 201888 kb
Host smart-e1e0ec93-b241-44f9-93c0-6363325ce49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143787919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.143787919
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.3890599587
Short name T214
Test name
Test status
Simulation time 329256375474 ps
CPU time 706.86 seconds
Started Jun 25 05:55:33 PM PDT 24
Finished Jun 25 06:07:20 PM PDT 24
Peak memory 201832 kb
Host smart-aa117a9a-1260-4177-89ef-a147febfe6e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890599587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.3890599587
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2948701547
Short name T526
Test name
Test status
Simulation time 198740652729 ps
CPU time 121.76 seconds
Started Jun 25 05:55:43 PM PDT 24
Finished Jun 25 05:57:46 PM PDT 24
Peak memory 201836 kb
Host smart-649abe3a-878c-43a9-a102-3c5b3f1002c9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948701547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2948701547
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.2935721586
Short name T67
Test name
Test status
Simulation time 119380704206 ps
CPU time 654.64 seconds
Started Jun 25 05:55:42 PM PDT 24
Finished Jun 25 06:06:37 PM PDT 24
Peak memory 202192 kb
Host smart-fca7c416-fa3d-41c8-a04a-b672e651e37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935721586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.2935721586
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.173172254
Short name T414
Test name
Test status
Simulation time 35384189644 ps
CPU time 18.98 seconds
Started Jun 25 05:55:42 PM PDT 24
Finished Jun 25 05:56:01 PM PDT 24
Peak memory 201684 kb
Host smart-b7d6fce8-0452-4df2-a1ac-099cc66c16f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173172254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.173172254
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.795015069
Short name T428
Test name
Test status
Simulation time 4958277747 ps
CPU time 12.72 seconds
Started Jun 25 05:55:41 PM PDT 24
Finished Jun 25 05:55:54 PM PDT 24
Peak memory 201664 kb
Host smart-6f0b0afc-256e-4d8b-babe-283f7907dc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795015069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.795015069
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.2037062154
Short name T382
Test name
Test status
Simulation time 5710361632 ps
CPU time 7.93 seconds
Started Jun 25 05:55:34 PM PDT 24
Finished Jun 25 05:55:43 PM PDT 24
Peak memory 201660 kb
Host smart-ef28ac9b-09c6-44ac-8d57-046bd1a4ec2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037062154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2037062154
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2353457820
Short name T673
Test name
Test status
Simulation time 404528578289 ps
CPU time 1048.97 seconds
Started Jun 25 05:55:42 PM PDT 24
Finished Jun 25 06:13:11 PM PDT 24
Peak memory 210448 kb
Host smart-79fe39a8-5279-462e-a639-f77e403e8985
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353457820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2353457820
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.2228429002
Short name T655
Test name
Test status
Simulation time 484838598 ps
CPU time 1.18 seconds
Started Jun 25 05:55:57 PM PDT 24
Finished Jun 25 05:55:59 PM PDT 24
Peak memory 201608 kb
Host smart-d08297ec-618e-4fc5-ba54-a53781f3183d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228429002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2228429002
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.2000307637
Short name T761
Test name
Test status
Simulation time 351676064597 ps
CPU time 193.66 seconds
Started Jun 25 05:55:58 PM PDT 24
Finished Jun 25 05:59:12 PM PDT 24
Peak memory 201872 kb
Host smart-fc903d94-734e-4823-b294-86e12b0badf9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000307637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.2000307637
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.3325827353
Short name T164
Test name
Test status
Simulation time 517130070333 ps
CPU time 1172.32 seconds
Started Jun 25 05:55:55 PM PDT 24
Finished Jun 25 06:15:28 PM PDT 24
Peak memory 201784 kb
Host smart-a4868f66-7575-464b-824a-29da982c8072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325827353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.3325827353
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.4103973788
Short name T459
Test name
Test status
Simulation time 163601585493 ps
CPU time 395.29 seconds
Started Jun 25 05:55:48 PM PDT 24
Finished Jun 25 06:02:24 PM PDT 24
Peak memory 201804 kb
Host smart-8ebcee94-c014-4906-bde0-3f26ce654461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103973788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.4103973788
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1729989810
Short name T780
Test name
Test status
Simulation time 328323798781 ps
CPU time 363.28 seconds
Started Jun 25 05:55:48 PM PDT 24
Finished Jun 25 06:01:52 PM PDT 24
Peak memory 201844 kb
Host smart-c8a24d56-e0e9-4a86-a3c1-8acacd091972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729989810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1729989810
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1981209895
Short name T474
Test name
Test status
Simulation time 162413789604 ps
CPU time 350.96 seconds
Started Jun 25 05:55:50 PM PDT 24
Finished Jun 25 06:01:41 PM PDT 24
Peak memory 201820 kb
Host smart-7a1209a9-635d-4969-ac69-252971b02526
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981209895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1981209895
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2582019736
Short name T764
Test name
Test status
Simulation time 536310501864 ps
CPU time 278.27 seconds
Started Jun 25 05:56:00 PM PDT 24
Finished Jun 25 06:00:39 PM PDT 24
Peak memory 201852 kb
Host smart-a23f959b-8764-4db6-88c1-49e4de8a52c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582019736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2582019736
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2525763279
Short name T754
Test name
Test status
Simulation time 400073007062 ps
CPU time 95.16 seconds
Started Jun 25 05:55:57 PM PDT 24
Finished Jun 25 05:57:33 PM PDT 24
Peak memory 201836 kb
Host smart-864195ac-a0b0-4a85-ad5b-b6e3cc20d30e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525763279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2525763279
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.3319847135
Short name T665
Test name
Test status
Simulation time 132526326050 ps
CPU time 708.59 seconds
Started Jun 25 05:55:57 PM PDT 24
Finished Jun 25 06:07:47 PM PDT 24
Peak memory 202372 kb
Host smart-3c59cb7a-bba0-46ca-bdd9-c86383f84ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319847135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3319847135
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.3201107290
Short name T366
Test name
Test status
Simulation time 28298118798 ps
CPU time 65.06 seconds
Started Jun 25 05:55:58 PM PDT 24
Finished Jun 25 05:57:04 PM PDT 24
Peak memory 201680 kb
Host smart-3c431f2c-dc25-465f-9e3b-2ec700411726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201107290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3201107290
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.2547945726
Short name T362
Test name
Test status
Simulation time 3782823036 ps
CPU time 9.05 seconds
Started Jun 25 05:55:56 PM PDT 24
Finished Jun 25 05:56:06 PM PDT 24
Peak memory 201668 kb
Host smart-abe8c0f1-180a-4999-bb9f-e5eb93082677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547945726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2547945726
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.796718426
Short name T681
Test name
Test status
Simulation time 5974293961 ps
CPU time 13.79 seconds
Started Jun 25 05:55:41 PM PDT 24
Finished Jun 25 05:55:55 PM PDT 24
Peak memory 201688 kb
Host smart-e9be85af-99c1-4fdb-9439-407d7b54bb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796718426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.796718426
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.919437892
Short name T55
Test name
Test status
Simulation time 263980587653 ps
CPU time 518.95 seconds
Started Jun 25 05:55:56 PM PDT 24
Finished Jun 25 06:04:36 PM PDT 24
Peak memory 218544 kb
Host smart-7f4bf258-7265-49bb-b7d7-6815327d2b57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919437892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
919437892
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1205125246
Short name T275
Test name
Test status
Simulation time 97670465849 ps
CPU time 184.23 seconds
Started Jun 25 05:56:00 PM PDT 24
Finished Jun 25 05:59:05 PM PDT 24
Peak memory 217956 kb
Host smart-01c4e785-9890-47ee-9c32-ca4b1f3e9d1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205125246 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.1205125246
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3254082384
Short name T719
Test name
Test status
Simulation time 560810955 ps
CPU time 0.83 seconds
Started Jun 25 05:56:03 PM PDT 24
Finished Jun 25 05:56:05 PM PDT 24
Peak memory 201612 kb
Host smart-649cbc3d-c0de-4bd1-8810-5f9d3db329c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254082384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3254082384
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.2320541465
Short name T223
Test name
Test status
Simulation time 345791183415 ps
CPU time 208.57 seconds
Started Jun 25 05:56:04 PM PDT 24
Finished Jun 25 05:59:33 PM PDT 24
Peak memory 201928 kb
Host smart-6f888ee6-4ced-4536-b07b-60f978275cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320541465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.2320541465
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.3498924029
Short name T755
Test name
Test status
Simulation time 496159613188 ps
CPU time 196.77 seconds
Started Jun 25 05:56:00 PM PDT 24
Finished Jun 25 05:59:17 PM PDT 24
Peak memory 201924 kb
Host smart-ac4b6592-8bc5-45f3-a1e6-93d2e7e0cd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498924029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.3498924029
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.3372132904
Short name T437
Test name
Test status
Simulation time 173607795187 ps
CPU time 105.83 seconds
Started Jun 25 05:56:06 PM PDT 24
Finished Jun 25 05:57:52 PM PDT 24
Peak memory 201844 kb
Host smart-f595d59b-fa14-421b-9f43-f93baa735be2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372132904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.3372132904
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.501489119
Short name T664
Test name
Test status
Simulation time 321997819288 ps
CPU time 189.02 seconds
Started Jun 25 05:55:59 PM PDT 24
Finished Jun 25 05:59:09 PM PDT 24
Peak memory 201864 kb
Host smart-c90bbda7-dfd4-44d0-908e-ee4a335dc858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501489119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.501489119
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3284197791
Short name T763
Test name
Test status
Simulation time 484482127633 ps
CPU time 923.75 seconds
Started Jun 25 05:55:57 PM PDT 24
Finished Jun 25 06:11:21 PM PDT 24
Peak memory 201832 kb
Host smart-43601267-a4bc-4fce-a48d-8c94c9e6357e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284197791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3284197791
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.2591398768
Short name T100
Test name
Test status
Simulation time 549289125212 ps
CPU time 700.85 seconds
Started Jun 25 05:56:05 PM PDT 24
Finished Jun 25 06:07:47 PM PDT 24
Peak memory 201852 kb
Host smart-f95a531f-5dce-4f77-bd90-54bd57c944d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591398768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.2591398768
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.4052680186
Short name T109
Test name
Test status
Simulation time 407550656328 ps
CPU time 262.44 seconds
Started Jun 25 05:56:03 PM PDT 24
Finished Jun 25 06:00:26 PM PDT 24
Peak memory 201784 kb
Host smart-09eb799c-a41f-494b-b832-44891b8b03e6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052680186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.4052680186
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.576177476
Short name T432
Test name
Test status
Simulation time 40380655488 ps
CPU time 23.27 seconds
Started Jun 25 05:56:03 PM PDT 24
Finished Jun 25 05:56:27 PM PDT 24
Peak memory 201680 kb
Host smart-4f9c3acf-8d89-4292-81db-4dde615b260c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576177476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.576177476
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.913454483
Short name T506
Test name
Test status
Simulation time 4992932484 ps
CPU time 12.4 seconds
Started Jun 25 05:56:05 PM PDT 24
Finished Jun 25 05:56:18 PM PDT 24
Peak memory 201680 kb
Host smart-be19dbf4-d0fb-4a27-ada4-0479bb7118c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913454483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.913454483
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1703878826
Short name T470
Test name
Test status
Simulation time 5685978698 ps
CPU time 3.78 seconds
Started Jun 25 05:55:58 PM PDT 24
Finished Jun 25 05:56:03 PM PDT 24
Peak memory 201672 kb
Host smart-0b077cc6-b024-4f1b-8cb9-6700cca1bebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703878826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1703878826
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2569376150
Short name T19
Test name
Test status
Simulation time 53473832116 ps
CPU time 100.98 seconds
Started Jun 25 05:56:04 PM PDT 24
Finished Jun 25 05:57:46 PM PDT 24
Peak memory 210508 kb
Host smart-083b9587-1009-49f7-bfa3-e9778581d58f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569376150 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.2569376150
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3616320973
Short name T711
Test name
Test status
Simulation time 523671431 ps
CPU time 1.41 seconds
Started Jun 25 05:56:15 PM PDT 24
Finished Jun 25 05:56:17 PM PDT 24
Peak memory 201624 kb
Host smart-2650ece7-7dfa-4fbd-b28a-4c5d1680fc1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616320973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3616320973
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.880581859
Short name T240
Test name
Test status
Simulation time 194380563037 ps
CPU time 404.87 seconds
Started Jun 25 05:56:14 PM PDT 24
Finished Jun 25 06:03:00 PM PDT 24
Peak memory 201852 kb
Host smart-0cf6ae1d-3865-46c2-b771-b61c8f78d770
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880581859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gati
ng.880581859
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.1260040813
Short name T167
Test name
Test status
Simulation time 162964441936 ps
CPU time 280.92 seconds
Started Jun 25 05:56:15 PM PDT 24
Finished Jun 25 06:00:57 PM PDT 24
Peak memory 201876 kb
Host smart-4fb24d94-8ebd-4ede-b1b1-daf85bb4991f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260040813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1260040813
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.3323651174
Short name T285
Test name
Test status
Simulation time 167005120153 ps
CPU time 267.95 seconds
Started Jun 25 05:56:06 PM PDT 24
Finished Jun 25 06:00:34 PM PDT 24
Peak memory 201876 kb
Host smart-42a8991c-efd3-48a5-900e-9ee7d8ff24f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323651174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.3323651174
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.1380638804
Short name T372
Test name
Test status
Simulation time 162372790600 ps
CPU time 384.05 seconds
Started Jun 25 05:56:16 PM PDT 24
Finished Jun 25 06:02:41 PM PDT 24
Peak memory 201832 kb
Host smart-defa1537-7017-47b7-91ed-7202a0f97975
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380638804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.1380638804
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.2071115643
Short name T617
Test name
Test status
Simulation time 477335022293 ps
CPU time 283 seconds
Started Jun 25 05:56:05 PM PDT 24
Finished Jun 25 06:00:49 PM PDT 24
Peak memory 201948 kb
Host smart-5085bc31-867a-4e38-9326-287947433ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071115643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2071115643
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.519936173
Short name T739
Test name
Test status
Simulation time 161450770333 ps
CPU time 333.02 seconds
Started Jun 25 05:56:03 PM PDT 24
Finished Jun 25 06:01:37 PM PDT 24
Peak memory 201864 kb
Host smart-d2e7f66b-bd92-4c04-821f-b445ab8e1fd1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=519936173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixe
d.519936173
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2020880148
Short name T790
Test name
Test status
Simulation time 175412645472 ps
CPU time 364.93 seconds
Started Jun 25 05:56:14 PM PDT 24
Finished Jun 25 06:02:20 PM PDT 24
Peak memory 201864 kb
Host smart-1ffafef9-27b4-4fde-9be3-d540451e6d6e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020880148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2020880148
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.505485980
Short name T491
Test name
Test status
Simulation time 404189317280 ps
CPU time 867.97 seconds
Started Jun 25 05:56:16 PM PDT 24
Finished Jun 25 06:10:45 PM PDT 24
Peak memory 201856 kb
Host smart-86d29225-2818-4e8e-9fcd-a7d89bbe7e9c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505485980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
adc_ctrl_filters_wakeup_fixed.505485980
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.815198453
Short name T605
Test name
Test status
Simulation time 107467236628 ps
CPU time 523.91 seconds
Started Jun 25 05:56:16 PM PDT 24
Finished Jun 25 06:05:00 PM PDT 24
Peak memory 202192 kb
Host smart-3ed0dbbe-f5c2-4039-9036-1deb3c06f807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815198453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.815198453
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.241295525
Short name T616
Test name
Test status
Simulation time 39934654758 ps
CPU time 53.34 seconds
Started Jun 25 05:56:15 PM PDT 24
Finished Jun 25 05:57:09 PM PDT 24
Peak memory 201660 kb
Host smart-e4ef849b-7804-4858-be83-46cd24820fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241295525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.241295525
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.3313813196
Short name T218
Test name
Test status
Simulation time 3820273354 ps
CPU time 10.07 seconds
Started Jun 25 05:56:15 PM PDT 24
Finished Jun 25 05:56:26 PM PDT 24
Peak memory 201612 kb
Host smart-9bf0d142-cd9a-4a2f-adc8-feb418a89623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313813196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.3313813196
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.4229890932
Short name T471
Test name
Test status
Simulation time 5862173592 ps
CPU time 13.42 seconds
Started Jun 25 05:56:04 PM PDT 24
Finished Jun 25 05:56:19 PM PDT 24
Peak memory 201656 kb
Host smart-337892e8-a80c-4b8c-9fc4-40cb9bd5c3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229890932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.4229890932
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.4162754741
Short name T85
Test name
Test status
Simulation time 319505969893 ps
CPU time 352.46 seconds
Started Jun 25 05:56:14 PM PDT 24
Finished Jun 25 06:02:08 PM PDT 24
Peak memory 201856 kb
Host smart-00d82add-8afb-4f57-aa41-7997e55d501c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162754741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.4162754741
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1917217952
Short name T610
Test name
Test status
Simulation time 96932381393 ps
CPU time 108.99 seconds
Started Jun 25 05:56:15 PM PDT 24
Finished Jun 25 05:58:04 PM PDT 24
Peak memory 210260 kb
Host smart-83f2c309-b2cd-498f-8a45-4f3664aab586
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917217952 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1917217952
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.348575882
Short name T620
Test name
Test status
Simulation time 460916156 ps
CPU time 0.94 seconds
Started Jun 25 05:51:58 PM PDT 24
Finished Jun 25 05:52:00 PM PDT 24
Peak memory 201616 kb
Host smart-f3c145fa-e95e-42c8-bf11-3ae525c76b59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348575882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.348575882
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.4085211422
Short name T736
Test name
Test status
Simulation time 360242506976 ps
CPU time 390.33 seconds
Started Jun 25 05:51:58 PM PDT 24
Finished Jun 25 05:58:30 PM PDT 24
Peak memory 201924 kb
Host smart-eb1f0429-be79-48f8-89b1-e61ead6d3e29
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085211422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.4085211422
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.1289743322
Short name T743
Test name
Test status
Simulation time 351626213101 ps
CPU time 112.23 seconds
Started Jun 25 05:52:04 PM PDT 24
Finished Jun 25 05:53:58 PM PDT 24
Peak memory 201872 kb
Host smart-829d755d-c53d-443a-aee4-90d1d4ffab3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289743322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1289743322
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.4098801170
Short name T642
Test name
Test status
Simulation time 166396822248 ps
CPU time 202.22 seconds
Started Jun 25 05:51:59 PM PDT 24
Finished Jun 25 05:55:23 PM PDT 24
Peak memory 201940 kb
Host smart-77ab2c85-c2c8-4cf8-9ee5-8716f9face4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098801170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.4098801170
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1827988691
Short name T429
Test name
Test status
Simulation time 333120987772 ps
CPU time 771.67 seconds
Started Jun 25 05:52:05 PM PDT 24
Finished Jun 25 06:04:58 PM PDT 24
Peak memory 201776 kb
Host smart-a653fa06-06a1-49c6-b0b3-de7b4d4169b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827988691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.1827988691
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.1616568859
Short name T520
Test name
Test status
Simulation time 164982798692 ps
CPU time 32.03 seconds
Started Jun 25 05:52:05 PM PDT 24
Finished Jun 25 05:52:39 PM PDT 24
Peak memory 201868 kb
Host smart-a24975a2-f48c-4beb-9831-1fab41844568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616568859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1616568859
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.1419178206
Short name T564
Test name
Test status
Simulation time 490363596609 ps
CPU time 294.99 seconds
Started Jun 25 05:52:05 PM PDT 24
Finished Jun 25 05:57:02 PM PDT 24
Peak memory 201848 kb
Host smart-dd496dc1-6158-4a87-a3c1-4bc8e9bc0de2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419178206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.1419178206
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1767401233
Short name T340
Test name
Test status
Simulation time 554289832622 ps
CPU time 312.56 seconds
Started Jun 25 05:52:05 PM PDT 24
Finished Jun 25 05:57:20 PM PDT 24
Peak memory 201612 kb
Host smart-0bec318e-caed-4354-9d31-0da59093877d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767401233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1767401233
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.431391985
Short name T9
Test name
Test status
Simulation time 201118285737 ps
CPU time 208.82 seconds
Started Jun 25 05:52:04 PM PDT 24
Finished Jun 25 05:55:34 PM PDT 24
Peak memory 201872 kb
Host smart-a4b0d238-7ec5-49d5-b24f-cad4c06ccd00
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431391985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.a
dc_ctrl_filters_wakeup_fixed.431391985
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.111054540
Short name T65
Test name
Test status
Simulation time 99473197568 ps
CPU time 402.9 seconds
Started Jun 25 05:52:01 PM PDT 24
Finished Jun 25 05:58:46 PM PDT 24
Peak memory 202180 kb
Host smart-a7f50d45-755f-40ec-81fa-52068195a761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111054540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.111054540
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1665561140
Short name T523
Test name
Test status
Simulation time 22305193985 ps
CPU time 5.98 seconds
Started Jun 25 05:52:04 PM PDT 24
Finished Jun 25 05:52:12 PM PDT 24
Peak memory 201696 kb
Host smart-91b47366-ec33-4160-8a64-31ffd537c6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665561140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1665561140
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.888200290
Short name T493
Test name
Test status
Simulation time 3233945604 ps
CPU time 4.12 seconds
Started Jun 25 05:52:03 PM PDT 24
Finished Jun 25 05:52:08 PM PDT 24
Peak memory 201672 kb
Host smart-4caf015c-afde-46b0-94fd-055e67ab5dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888200290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.888200290
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2577009562
Short name T96
Test name
Test status
Simulation time 7647706021 ps
CPU time 19.44 seconds
Started Jun 25 05:52:00 PM PDT 24
Finished Jun 25 05:52:21 PM PDT 24
Peak memory 217868 kb
Host smart-756faf45-3bd0-4175-bb04-6fd967319714
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577009562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2577009562
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.3669386343
Short name T361
Test name
Test status
Simulation time 5897415958 ps
CPU time 11.57 seconds
Started Jun 25 05:52:02 PM PDT 24
Finished Jun 25 05:52:15 PM PDT 24
Peak memory 201664 kb
Host smart-98e066fd-e251-4017-b291-c820eb175687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669386343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.3669386343
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.115307879
Short name T124
Test name
Test status
Simulation time 344984126179 ps
CPU time 348.73 seconds
Started Jun 25 05:52:01 PM PDT 24
Finished Jun 25 05:57:52 PM PDT 24
Peak memory 211604 kb
Host smart-40f4eb7e-86be-4601-8f1f-72bc714fd731
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115307879 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.115307879
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2149837883
Short name T666
Test name
Test status
Simulation time 362657614 ps
CPU time 1.03 seconds
Started Jun 25 05:56:19 PM PDT 24
Finished Jun 25 05:56:20 PM PDT 24
Peak memory 201604 kb
Host smart-bca6d91e-0886-4a0c-a151-fb15f41ab41b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149837883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2149837883
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1920876937
Short name T10
Test name
Test status
Simulation time 510569109472 ps
CPU time 347.22 seconds
Started Jun 25 05:56:18 PM PDT 24
Finished Jun 25 06:02:06 PM PDT 24
Peak memory 201872 kb
Host smart-bb30b4e6-3328-4f8a-9859-afd2dccabe3d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920876937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1920876937
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.1650741969
Short name T696
Test name
Test status
Simulation time 487793082865 ps
CPU time 83.28 seconds
Started Jun 25 05:56:14 PM PDT 24
Finished Jun 25 05:57:38 PM PDT 24
Peak memory 201820 kb
Host smart-aa64af5c-7ce2-413b-824d-57fc4c396228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650741969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1650741969
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3005196157
Short name T455
Test name
Test status
Simulation time 326255613146 ps
CPU time 369.25 seconds
Started Jun 25 05:56:19 PM PDT 24
Finished Jun 25 06:02:29 PM PDT 24
Peak memory 201812 kb
Host smart-7443f45d-7d3e-42dc-82f5-ccb45654f1de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005196157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.3005196157
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3969830265
Short name T97
Test name
Test status
Simulation time 323530308498 ps
CPU time 375.09 seconds
Started Jun 25 05:56:14 PM PDT 24
Finished Jun 25 06:02:30 PM PDT 24
Peak memory 201940 kb
Host smart-0eb84a3c-9337-40e2-887c-9e90bcb26fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969830265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3969830265
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.446727526
Short name T409
Test name
Test status
Simulation time 160782743738 ps
CPU time 182.33 seconds
Started Jun 25 05:56:16 PM PDT 24
Finished Jun 25 05:59:19 PM PDT 24
Peak memory 201848 kb
Host smart-2dd257e4-f391-4603-8284-08c47bbdbc77
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=446727526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixe
d.446727526
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.1054052216
Short name T43
Test name
Test status
Simulation time 530967304502 ps
CPU time 300.35 seconds
Started Jun 25 05:56:18 PM PDT 24
Finished Jun 25 06:01:19 PM PDT 24
Peak memory 201964 kb
Host smart-3a9fec23-eef4-4acf-8edc-edbc1449735b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054052216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.1054052216
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2680351563
Short name T391
Test name
Test status
Simulation time 578879492362 ps
CPU time 379.5 seconds
Started Jun 25 05:56:19 PM PDT 24
Finished Jun 25 06:02:39 PM PDT 24
Peak memory 201836 kb
Host smart-412a4b59-5cd5-42d3-b8d4-b5f76352f880
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680351563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2680351563
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.493221130
Short name T554
Test name
Test status
Simulation time 87939897561 ps
CPU time 324.89 seconds
Started Jun 25 05:56:20 PM PDT 24
Finished Jun 25 06:01:46 PM PDT 24
Peak memory 202252 kb
Host smart-032b1e08-6f2b-4abc-9eec-01e73b1150b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493221130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.493221130
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2068188034
Short name T624
Test name
Test status
Simulation time 30538654076 ps
CPU time 36.32 seconds
Started Jun 25 05:56:19 PM PDT 24
Finished Jun 25 05:56:56 PM PDT 24
Peak memory 201644 kb
Host smart-795ce85f-232d-436c-a7a1-1a1f765525b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068188034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2068188034
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.1868063371
Short name T636
Test name
Test status
Simulation time 4685351990 ps
CPU time 3.09 seconds
Started Jun 25 05:56:19 PM PDT 24
Finished Jun 25 05:56:23 PM PDT 24
Peak memory 201664 kb
Host smart-9975d178-899b-4bc5-b2fb-f951e7bd2f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868063371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.1868063371
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.2961037377
Short name T511
Test name
Test status
Simulation time 6043960985 ps
CPU time 7.85 seconds
Started Jun 25 05:56:15 PM PDT 24
Finished Jun 25 05:56:23 PM PDT 24
Peak memory 201912 kb
Host smart-11195233-b56e-44fa-bcdd-e5a73f465676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961037377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2961037377
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.1990186590
Short name T117
Test name
Test status
Simulation time 168083899722 ps
CPU time 403.45 seconds
Started Jun 25 05:56:19 PM PDT 24
Finished Jun 25 06:03:03 PM PDT 24
Peak memory 201848 kb
Host smart-22e3df37-1d7b-4348-9b11-cdd08810176f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990186590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.1990186590
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.4046190513
Short name T563
Test name
Test status
Simulation time 248007325950 ps
CPU time 268.41 seconds
Started Jun 25 05:56:19 PM PDT 24
Finished Jun 25 06:00:48 PM PDT 24
Peak memory 210500 kb
Host smart-ed7739f3-b44b-4b0e-a966-09265619bd9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046190513 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.4046190513
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.3149681153
Short name T720
Test name
Test status
Simulation time 519914440 ps
CPU time 1.78 seconds
Started Jun 25 05:56:33 PM PDT 24
Finished Jun 25 05:56:35 PM PDT 24
Peak memory 201608 kb
Host smart-b377c4da-e435-40ae-8911-1c0e2da931fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149681153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3149681153
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.3671175797
Short name T101
Test name
Test status
Simulation time 357374591700 ps
CPU time 422.08 seconds
Started Jun 25 05:56:26 PM PDT 24
Finished Jun 25 06:03:29 PM PDT 24
Peak memory 201836 kb
Host smart-059e81c9-ba66-40c6-8601-42e4803f3934
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671175797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.3671175797
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.2024241602
Short name T333
Test name
Test status
Simulation time 328854510788 ps
CPU time 198.3 seconds
Started Jun 25 05:56:29 PM PDT 24
Finished Jun 25 05:59:48 PM PDT 24
Peak memory 201948 kb
Host smart-ac64d5ec-39b4-4f2c-8eb6-aa48bec5528b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024241602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2024241602
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.910924947
Short name T198
Test name
Test status
Simulation time 503201962053 ps
CPU time 327.2 seconds
Started Jun 25 05:56:27 PM PDT 24
Finished Jun 25 06:01:55 PM PDT 24
Peak memory 201956 kb
Host smart-163234f3-f108-4bf8-a812-e797bc3d8cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910924947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.910924947
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3207285878
Short name T596
Test name
Test status
Simulation time 333075240036 ps
CPU time 207.06 seconds
Started Jun 25 05:56:26 PM PDT 24
Finished Jun 25 05:59:54 PM PDT 24
Peak memory 201844 kb
Host smart-4079af36-e066-4a47-85b4-215a63c18c1a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207285878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3207285878
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.114614876
Short name T276
Test name
Test status
Simulation time 491712522082 ps
CPU time 1135.22 seconds
Started Jun 25 05:56:19 PM PDT 24
Finished Jun 25 06:15:15 PM PDT 24
Peak memory 201940 kb
Host smart-eb9e72d1-86af-493b-abc8-f2d4fad39d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114614876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.114614876
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3530698469
Short name T427
Test name
Test status
Simulation time 325632559798 ps
CPU time 109.58 seconds
Started Jun 25 05:56:19 PM PDT 24
Finished Jun 25 05:58:09 PM PDT 24
Peak memory 201908 kb
Host smart-ebcaad2b-1bef-44a3-93e9-6d735a4bda78
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530698469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3530698469
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.810091556
Short name T219
Test name
Test status
Simulation time 195400564155 ps
CPU time 31.05 seconds
Started Jun 25 05:56:26 PM PDT 24
Finished Jun 25 05:56:57 PM PDT 24
Peak memory 201852 kb
Host smart-4f35d5e4-28b6-4704-b310-29cce08cde5c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810091556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_
wakeup.810091556
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.117150203
Short name T114
Test name
Test status
Simulation time 199309545519 ps
CPU time 452.4 seconds
Started Jun 25 05:56:25 PM PDT 24
Finished Jun 25 06:03:58 PM PDT 24
Peak memory 201844 kb
Host smart-665d65de-2ae8-45fc-937b-98cd404150f1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117150203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
adc_ctrl_filters_wakeup_fixed.117150203
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3960978442
Short name T227
Test name
Test status
Simulation time 116775595282 ps
CPU time 640.44 seconds
Started Jun 25 05:56:27 PM PDT 24
Finished Jun 25 06:07:08 PM PDT 24
Peak memory 202276 kb
Host smart-a36544a3-1443-4225-bdbb-b424eb4dc883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960978442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3960978442
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.395146405
Short name T458
Test name
Test status
Simulation time 34313484275 ps
CPU time 78.39 seconds
Started Jun 25 05:56:25 PM PDT 24
Finished Jun 25 05:57:44 PM PDT 24
Peak memory 201668 kb
Host smart-ddab6e8d-1a6f-4b4f-bc86-6f96d53a0f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395146405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.395146405
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.601358836
Short name T435
Test name
Test status
Simulation time 3779073933 ps
CPU time 5 seconds
Started Jun 25 05:56:26 PM PDT 24
Finished Jun 25 05:56:32 PM PDT 24
Peak memory 201660 kb
Host smart-777854cd-6584-4f3e-b468-45fd0aa7cb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601358836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.601358836
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.412632182
Short name T781
Test name
Test status
Simulation time 5800873254 ps
CPU time 6.01 seconds
Started Jun 25 05:56:19 PM PDT 24
Finished Jun 25 05:56:26 PM PDT 24
Peak memory 201656 kb
Host smart-9e4253dd-7f98-407f-b28b-8516523cfc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412632182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.412632182
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.1387849571
Short name T772
Test name
Test status
Simulation time 493858073023 ps
CPU time 285.33 seconds
Started Jun 25 05:56:36 PM PDT 24
Finished Jun 25 06:01:22 PM PDT 24
Peak memory 201880 kb
Host smart-35a310b3-0203-4f32-aebd-ff5f7cc13784
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387849571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.1387849571
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.364775560
Short name T76
Test name
Test status
Simulation time 56699915270 ps
CPU time 127.41 seconds
Started Jun 25 05:56:26 PM PDT 24
Finished Jun 25 05:58:34 PM PDT 24
Peak memory 210560 kb
Host smart-c399eaa3-40bf-4553-806a-770b28e3fe3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364775560 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.364775560
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1264138361
Short name T25
Test name
Test status
Simulation time 528571878 ps
CPU time 1.69 seconds
Started Jun 25 05:56:41 PM PDT 24
Finished Jun 25 05:56:43 PM PDT 24
Peak memory 201604 kb
Host smart-ddabb1b4-4e5f-4efc-9d9a-41ccb49197d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264138361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1264138361
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.1111137497
Short name T203
Test name
Test status
Simulation time 517583674117 ps
CPU time 288.18 seconds
Started Jun 25 05:56:34 PM PDT 24
Finished Jun 25 06:01:23 PM PDT 24
Peak memory 201920 kb
Host smart-a3b8fcd3-0c0f-4248-a4fc-a2f38926ac8a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111137497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.1111137497
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.3956571572
Short name T286
Test name
Test status
Simulation time 510325200365 ps
CPU time 1116.98 seconds
Started Jun 25 05:56:35 PM PDT 24
Finished Jun 25 06:15:13 PM PDT 24
Peak memory 201932 kb
Host smart-92c1b6c5-b91d-425d-97cb-65b1c10624f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956571572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3956571572
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.4081165579
Short name T698
Test name
Test status
Simulation time 488487160348 ps
CPU time 1069.28 seconds
Started Jun 25 05:56:32 PM PDT 24
Finished Jun 25 06:14:22 PM PDT 24
Peak memory 201940 kb
Host smart-2d472e7b-4dd3-44d7-9f19-ba423d3a8268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081165579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.4081165579
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2643790804
Short name T355
Test name
Test status
Simulation time 162976621295 ps
CPU time 95.9 seconds
Started Jun 25 05:56:33 PM PDT 24
Finished Jun 25 05:58:10 PM PDT 24
Peak memory 201848 kb
Host smart-58b0b314-4480-455a-aaa6-0c6670512181
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643790804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2643790804
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.3679063920
Short name T99
Test name
Test status
Simulation time 328174408948 ps
CPU time 191.6 seconds
Started Jun 25 05:56:34 PM PDT 24
Finished Jun 25 05:59:46 PM PDT 24
Peak memory 201924 kb
Host smart-a991071e-5420-4550-b7cd-7ded43ccd54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679063920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3679063920
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3493337832
Short name T612
Test name
Test status
Simulation time 166746041240 ps
CPU time 235.78 seconds
Started Jun 25 05:56:33 PM PDT 24
Finished Jun 25 06:00:30 PM PDT 24
Peak memory 201840 kb
Host smart-0baa2384-01d6-4559-94fc-7ab62d7bddf7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493337832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.3493337832
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1391411597
Short name T778
Test name
Test status
Simulation time 163309254229 ps
CPU time 175.32 seconds
Started Jun 25 05:56:33 PM PDT 24
Finished Jun 25 05:59:29 PM PDT 24
Peak memory 201860 kb
Host smart-3a1ad75a-15c5-46d0-be61-3f58047bf445
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391411597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1391411597
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1739350168
Short name T535
Test name
Test status
Simulation time 208659854665 ps
CPU time 463.96 seconds
Started Jun 25 05:56:33 PM PDT 24
Finished Jun 25 06:04:17 PM PDT 24
Peak memory 201888 kb
Host smart-fa84f053-9b98-416c-82ea-7a64d96981a0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739350168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.1739350168
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.3422098318
Short name T351
Test name
Test status
Simulation time 69310811791 ps
CPU time 298.22 seconds
Started Jun 25 05:56:42 PM PDT 24
Finished Jun 25 06:01:41 PM PDT 24
Peak memory 202184 kb
Host smart-623965ae-07f8-495e-8744-6d72afdf0a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422098318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3422098318
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.328926877
Short name T68
Test name
Test status
Simulation time 25142807727 ps
CPU time 14.7 seconds
Started Jun 25 05:56:41 PM PDT 24
Finished Jun 25 05:56:56 PM PDT 24
Peak memory 201672 kb
Host smart-f217aa29-0cd9-4b3a-ad4b-39ed0c044e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328926877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.328926877
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3465837195
Short name T571
Test name
Test status
Simulation time 4450533186 ps
CPU time 5.56 seconds
Started Jun 25 05:56:40 PM PDT 24
Finished Jun 25 05:56:47 PM PDT 24
Peak memory 201676 kb
Host smart-cf515cdf-f2cb-4ae7-a029-27daad59071d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465837195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3465837195
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.3434230803
Short name T370
Test name
Test status
Simulation time 6206045566 ps
CPU time 8.04 seconds
Started Jun 25 05:56:32 PM PDT 24
Finished Jun 25 05:56:41 PM PDT 24
Peak memory 201656 kb
Host smart-8065cb89-358b-42e6-9846-341371123e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434230803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3434230803
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2444571573
Short name T335
Test name
Test status
Simulation time 42414035736 ps
CPU time 125.84 seconds
Started Jun 25 05:56:41 PM PDT 24
Finished Jun 25 05:58:48 PM PDT 24
Peak memory 218708 kb
Host smart-cdd99eaf-e542-4fbe-8da6-9bbc26c2f1e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444571573 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2444571573
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2297116465
Short name T704
Test name
Test status
Simulation time 376593829 ps
CPU time 0.85 seconds
Started Jun 25 05:56:51 PM PDT 24
Finished Jun 25 05:56:52 PM PDT 24
Peak memory 201600 kb
Host smart-24075067-397a-4d01-9de9-7f5a7fbbabd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297116465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2297116465
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.3336813489
Short name T308
Test name
Test status
Simulation time 530051210353 ps
CPU time 397.2 seconds
Started Jun 25 05:56:43 PM PDT 24
Finished Jun 25 06:03:21 PM PDT 24
Peak memory 201940 kb
Host smart-6c6769dd-e595-49e9-ac38-c98892870337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336813489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3336813489
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1762906038
Short name T304
Test name
Test status
Simulation time 332294830063 ps
CPU time 702.46 seconds
Started Jun 25 05:56:41 PM PDT 24
Finished Jun 25 06:08:25 PM PDT 24
Peak memory 201876 kb
Host smart-df5402a4-96a7-4284-a578-177bf222f742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762906038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1762906038
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.795883753
Short name T463
Test name
Test status
Simulation time 161905264319 ps
CPU time 197.49 seconds
Started Jun 25 05:56:42 PM PDT 24
Finished Jun 25 06:00:00 PM PDT 24
Peak memory 201828 kb
Host smart-7b173d64-1c6f-4e0c-81ae-e8be6af93202
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=795883753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrup
t_fixed.795883753
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.1699580698
Short name T194
Test name
Test status
Simulation time 488929099564 ps
CPU time 65.96 seconds
Started Jun 25 05:56:41 PM PDT 24
Finished Jun 25 05:57:48 PM PDT 24
Peak memory 201984 kb
Host smart-11a66d3d-6528-4481-b05f-06fd2be01cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699580698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.1699580698
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.637746517
Short name T747
Test name
Test status
Simulation time 163919406382 ps
CPU time 80.07 seconds
Started Jun 25 05:56:40 PM PDT 24
Finished Jun 25 05:58:00 PM PDT 24
Peak memory 201864 kb
Host smart-81b0f6f2-f00f-4d33-8ff3-15149171a3df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=637746517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixe
d.637746517
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.1049959513
Short name T724
Test name
Test status
Simulation time 542269020111 ps
CPU time 1194.32 seconds
Started Jun 25 05:56:43 PM PDT 24
Finished Jun 25 06:16:38 PM PDT 24
Peak memory 201924 kb
Host smart-23e70b98-6543-4d6c-a670-2705b7023f3c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049959513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.1049959513
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.3986238252
Short name T250
Test name
Test status
Simulation time 614943548235 ps
CPU time 1383.77 seconds
Started Jun 25 05:56:42 PM PDT 24
Finished Jun 25 06:19:47 PM PDT 24
Peak memory 201824 kb
Host smart-517dabea-920a-4d3a-8e69-b6b58e5e8b7d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986238252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.3986238252
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.3557041996
Short name T183
Test name
Test status
Simulation time 76727463926 ps
CPU time 219.62 seconds
Started Jun 25 05:56:52 PM PDT 24
Finished Jun 25 06:00:32 PM PDT 24
Peak memory 202200 kb
Host smart-ee7fbc77-16bd-43d2-b89b-35e23710f03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557041996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.3557041996
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.1633725125
Short name T371
Test name
Test status
Simulation time 44160835042 ps
CPU time 96.3 seconds
Started Jun 25 05:56:49 PM PDT 24
Finished Jun 25 05:58:26 PM PDT 24
Peak memory 201516 kb
Host smart-80fa8bce-3061-4890-adee-1fd7c311c522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633725125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1633725125
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.1865321871
Short name T536
Test name
Test status
Simulation time 3389348483 ps
CPU time 2.04 seconds
Started Jun 25 05:56:46 PM PDT 24
Finished Jun 25 05:56:49 PM PDT 24
Peak memory 201656 kb
Host smart-ae67108b-3ac3-42a1-b738-20007e41ea4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865321871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.1865321871
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1943449759
Short name T380
Test name
Test status
Simulation time 5826221465 ps
CPU time 14.93 seconds
Started Jun 25 05:56:40 PM PDT 24
Finished Jun 25 05:56:56 PM PDT 24
Peak memory 201656 kb
Host smart-6e221186-0fa3-4e0b-ad49-39dac25bd86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943449759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1943449759
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.4146061210
Short name T766
Test name
Test status
Simulation time 532335936246 ps
CPU time 861.28 seconds
Started Jun 25 05:56:51 PM PDT 24
Finished Jun 25 06:11:13 PM PDT 24
Peak memory 201856 kb
Host smart-fda126da-2650-42fe-8dcb-4e58465332a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146061210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.4146061210
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3395687644
Short name T106
Test name
Test status
Simulation time 374202419341 ps
CPU time 148.28 seconds
Started Jun 25 05:56:53 PM PDT 24
Finished Jun 25 05:59:22 PM PDT 24
Peak memory 212816 kb
Host smart-9ad5c8ac-7440-4b5b-82d1-767949cc7268
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395687644 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3395687644
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1488901181
Short name T426
Test name
Test status
Simulation time 523978277 ps
CPU time 0.87 seconds
Started Jun 25 05:57:00 PM PDT 24
Finished Jun 25 05:57:01 PM PDT 24
Peak memory 201620 kb
Host smart-d312e4bb-b66d-458e-bbea-1cc50fca7cf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488901181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1488901181
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.3321202751
Short name T281
Test name
Test status
Simulation time 196126226050 ps
CPU time 146.73 seconds
Started Jun 25 05:57:03 PM PDT 24
Finished Jun 25 05:59:30 PM PDT 24
Peak memory 201876 kb
Host smart-196b53d3-a533-4062-aa69-5af111ec1cac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321202751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.3321202751
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2350362274
Short name T262
Test name
Test status
Simulation time 349483976348 ps
CPU time 209.71 seconds
Started Jun 25 05:56:59 PM PDT 24
Finished Jun 25 06:00:29 PM PDT 24
Peak memory 201784 kb
Host smart-63bc6d57-f0f3-4190-bdb9-65f927bc0197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350362274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2350362274
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.2535662278
Short name T293
Test name
Test status
Simulation time 329254501021 ps
CPU time 134.94 seconds
Started Jun 25 05:56:53 PM PDT 24
Finished Jun 25 05:59:08 PM PDT 24
Peak memory 201876 kb
Host smart-41ec56f8-e048-47a4-9e62-9ebe2175788d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535662278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.2535662278
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2506264846
Short name T508
Test name
Test status
Simulation time 159432862225 ps
CPU time 88.13 seconds
Started Jun 25 05:57:00 PM PDT 24
Finished Jun 25 05:58:29 PM PDT 24
Peak memory 201820 kb
Host smart-b2f7a7ac-e7ec-4112-8451-b8d31c615e20
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506264846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.2506264846
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.4153868378
Short name T339
Test name
Test status
Simulation time 488091439919 ps
CPU time 568.86 seconds
Started Jun 25 05:56:53 PM PDT 24
Finished Jun 25 06:06:22 PM PDT 24
Peak memory 201944 kb
Host smart-56a6055a-1484-4cd7-9430-3874585d8d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153868378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.4153868378
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3186159140
Short name T434
Test name
Test status
Simulation time 163148327678 ps
CPU time 187.25 seconds
Started Jun 25 05:56:52 PM PDT 24
Finished Jun 25 06:00:00 PM PDT 24
Peak memory 201836 kb
Host smart-19f7569c-9deb-4525-b983-8c4d2100a8dd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186159140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.3186159140
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2220843696
Short name T615
Test name
Test status
Simulation time 550568198991 ps
CPU time 1138.55 seconds
Started Jun 25 05:56:59 PM PDT 24
Finished Jun 25 06:15:59 PM PDT 24
Peak memory 201864 kb
Host smart-dfc15d9f-67d4-4424-a041-3c6fde76ebab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220843696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2220843696
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3762272368
Short name T553
Test name
Test status
Simulation time 189637201687 ps
CPU time 433.19 seconds
Started Jun 25 05:56:59 PM PDT 24
Finished Jun 25 06:04:13 PM PDT 24
Peak memory 201848 kb
Host smart-8b66fbe0-be11-408d-98f2-43d8946377e6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762272368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3762272368
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.3287882949
Short name T38
Test name
Test status
Simulation time 81417601026 ps
CPU time 288.2 seconds
Started Jun 25 05:56:58 PM PDT 24
Finished Jun 25 06:01:46 PM PDT 24
Peak memory 202264 kb
Host smart-96a8e45e-44a8-408a-a959-245cb64c6a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287882949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3287882949
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.4051123658
Short name T518
Test name
Test status
Simulation time 23311717549 ps
CPU time 24.9 seconds
Started Jun 25 05:56:58 PM PDT 24
Finished Jun 25 05:57:24 PM PDT 24
Peak memory 201656 kb
Host smart-ca68d94f-cdff-4a57-9f5d-41a836a2665f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051123658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.4051123658
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.3819886280
Short name T356
Test name
Test status
Simulation time 4144005470 ps
CPU time 5.21 seconds
Started Jun 25 05:56:58 PM PDT 24
Finished Jun 25 05:57:04 PM PDT 24
Peak memory 201668 kb
Host smart-6b250400-4b12-44dc-8709-acd25fc1d8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819886280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.3819886280
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.2477577917
Short name T93
Test name
Test status
Simulation time 5540949227 ps
CPU time 13.38 seconds
Started Jun 25 05:56:51 PM PDT 24
Finished Jun 25 05:57:05 PM PDT 24
Peak memory 201672 kb
Host smart-624cc465-de74-43ef-b1aa-3eaf0024477c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477577917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.2477577917
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.3854747160
Short name T567
Test name
Test status
Simulation time 177722892226 ps
CPU time 35.44 seconds
Started Jun 25 05:56:58 PM PDT 24
Finished Jun 25 05:57:34 PM PDT 24
Peak memory 201868 kb
Host smart-b7261e5f-78f0-463d-b6c0-ab17f6ef9a7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854747160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.3854747160
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.3046384046
Short name T594
Test name
Test status
Simulation time 94488115064 ps
CPU time 84.42 seconds
Started Jun 25 05:57:02 PM PDT 24
Finished Jun 25 05:58:27 PM PDT 24
Peak memory 210260 kb
Host smart-c5b3d76b-a79f-44fd-943a-161ed64c47c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046384046 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.3046384046
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.4041009717
Short name T773
Test name
Test status
Simulation time 370470833 ps
CPU time 1.33 seconds
Started Jun 25 05:57:08 PM PDT 24
Finished Jun 25 05:57:10 PM PDT 24
Peak memory 201596 kb
Host smart-dad53484-6a0e-4ea0-ba97-9ff679723c70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041009717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.4041009717
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.3331940020
Short name T684
Test name
Test status
Simulation time 356653820936 ps
CPU time 770.26 seconds
Started Jun 25 05:57:07 PM PDT 24
Finished Jun 25 06:09:58 PM PDT 24
Peak memory 201852 kb
Host smart-6b26c9b9-67e0-47fa-82bc-99e020e779ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331940020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.3331940020
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.3923694547
Short name T313
Test name
Test status
Simulation time 323870924881 ps
CPU time 356.63 seconds
Started Jun 25 05:57:07 PM PDT 24
Finished Jun 25 06:03:04 PM PDT 24
Peak memory 201864 kb
Host smart-690bec21-705e-484e-9653-01dea883a6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923694547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.3923694547
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.1714392638
Short name T292
Test name
Test status
Simulation time 331301382698 ps
CPU time 353.33 seconds
Started Jun 25 05:57:00 PM PDT 24
Finished Jun 25 06:02:54 PM PDT 24
Peak memory 201924 kb
Host smart-f207d1fa-a6aa-4de9-a7d9-335646b8591f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714392638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1714392638
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.231025215
Short name T695
Test name
Test status
Simulation time 494002851797 ps
CPU time 1112.75 seconds
Started Jun 25 05:57:03 PM PDT 24
Finished Jun 25 06:15:36 PM PDT 24
Peak memory 201860 kb
Host smart-5b188224-bbae-4dc1-bebf-2435356f0e94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=231025215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrup
t_fixed.231025215
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.4103044497
Short name T507
Test name
Test status
Simulation time 328891802187 ps
CPU time 744.56 seconds
Started Jun 25 05:57:03 PM PDT 24
Finished Jun 25 06:09:28 PM PDT 24
Peak memory 201892 kb
Host smart-2e6eba2c-8e5b-46fe-91d3-4496b50a2d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103044497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.4103044497
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1825505844
Short name T713
Test name
Test status
Simulation time 324475995247 ps
CPU time 696.17 seconds
Started Jun 25 05:56:59 PM PDT 24
Finished Jun 25 06:08:36 PM PDT 24
Peak memory 201848 kb
Host smart-fb6955da-7e77-4f83-91a3-0c507dc81d52
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825505844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1825505844
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.2381739212
Short name T327
Test name
Test status
Simulation time 458874023634 ps
CPU time 1040.59 seconds
Started Jun 25 05:57:07 PM PDT 24
Finished Jun 25 06:14:28 PM PDT 24
Peak memory 201940 kb
Host smart-4f936f2c-3a01-4865-a09a-4847a0d5927a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381739212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.2381739212
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3530895603
Short name T153
Test name
Test status
Simulation time 210635659239 ps
CPU time 130.24 seconds
Started Jun 25 05:57:06 PM PDT 24
Finished Jun 25 05:59:17 PM PDT 24
Peak memory 201888 kb
Host smart-9b694096-6260-429c-a4b8-2fd18cc72a5a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530895603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.3530895603
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.3547489953
Short name T465
Test name
Test status
Simulation time 80923280915 ps
CPU time 301.55 seconds
Started Jun 25 05:57:07 PM PDT 24
Finished Jun 25 06:02:09 PM PDT 24
Peak memory 202172 kb
Host smart-97e052ce-4518-4eb2-b512-69dd751a6005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547489953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.3547489953
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.4160740922
Short name T542
Test name
Test status
Simulation time 26365901169 ps
CPU time 63.89 seconds
Started Jun 25 05:57:07 PM PDT 24
Finished Jun 25 05:58:11 PM PDT 24
Peak memory 201604 kb
Host smart-8f334705-0b72-4bbd-9e22-c3fbe449eb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160740922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.4160740922
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.3030994387
Short name T608
Test name
Test status
Simulation time 5021413593 ps
CPU time 2.55 seconds
Started Jun 25 05:57:09 PM PDT 24
Finished Jun 25 05:57:12 PM PDT 24
Peak memory 201660 kb
Host smart-7bf90b12-e832-4a11-a23b-6598aa909b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030994387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.3030994387
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.519828961
Short name T524
Test name
Test status
Simulation time 5903092537 ps
CPU time 7.25 seconds
Started Jun 25 05:56:58 PM PDT 24
Finished Jun 25 05:57:05 PM PDT 24
Peak memory 201664 kb
Host smart-0ddb3352-8e07-4a49-b033-e4b02dec466a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519828961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.519828961
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1412733204
Short name T691
Test name
Test status
Simulation time 387892380960 ps
CPU time 685.67 seconds
Started Jun 25 05:57:09 PM PDT 24
Finished Jun 25 06:08:35 PM PDT 24
Peak memory 210376 kb
Host smart-90d7fc92-cbff-4c2e-b3a7-61aeacb607d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412733204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1412733204
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1993735920
Short name T14
Test name
Test status
Simulation time 57677243168 ps
CPU time 61.17 seconds
Started Jun 25 05:57:09 PM PDT 24
Finished Jun 25 05:58:11 PM PDT 24
Peak memory 210180 kb
Host smart-206b16c6-ee27-4cae-82bc-4efa2c2dc066
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993735920 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1993735920
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2222225399
Short name T671
Test name
Test status
Simulation time 324912841 ps
CPU time 1 seconds
Started Jun 25 05:57:14 PM PDT 24
Finished Jun 25 05:57:16 PM PDT 24
Peak memory 201608 kb
Host smart-e1efc913-07d9-426b-bc46-a9bf6275f522
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222225399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2222225399
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.253902155
Short name T207
Test name
Test status
Simulation time 579549663614 ps
CPU time 256.48 seconds
Started Jun 25 05:57:18 PM PDT 24
Finished Jun 25 06:01:36 PM PDT 24
Peak memory 201856 kb
Host smart-c945431a-cc51-4fbe-9f33-71b7ff1368f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253902155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gati
ng.253902155
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.4046536660
Short name T321
Test name
Test status
Simulation time 164574021235 ps
CPU time 88.76 seconds
Started Jun 25 05:57:15 PM PDT 24
Finished Jun 25 05:58:45 PM PDT 24
Peak memory 201892 kb
Host smart-44479c5d-c42a-409d-917a-b71715bd0018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046536660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.4046536660
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1388033092
Short name T529
Test name
Test status
Simulation time 159035924142 ps
CPU time 71.11 seconds
Started Jun 25 05:57:08 PM PDT 24
Finished Jun 25 05:58:19 PM PDT 24
Peak memory 201812 kb
Host smart-005b91b6-73a0-40ea-a355-1da04c20be42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388033092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1388033092
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2599065641
Short name T182
Test name
Test status
Simulation time 498250236101 ps
CPU time 294.13 seconds
Started Jun 25 05:57:08 PM PDT 24
Finished Jun 25 06:02:03 PM PDT 24
Peak memory 201848 kb
Host smart-197c6fe6-e101-4f8b-b7b3-57845d18ff3d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599065641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.2599065641
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.1505009351
Short name T111
Test name
Test status
Simulation time 161709734988 ps
CPU time 366.96 seconds
Started Jun 25 05:57:08 PM PDT 24
Finished Jun 25 06:03:15 PM PDT 24
Peak memory 201884 kb
Host smart-5cca91b7-8294-464a-b47c-1e9da691636d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505009351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.1505009351
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.168496222
Short name T591
Test name
Test status
Simulation time 486727245943 ps
CPU time 260.82 seconds
Started Jun 25 05:57:06 PM PDT 24
Finished Jun 25 06:01:27 PM PDT 24
Peak memory 201884 kb
Host smart-4fe2bd24-1be8-4015-8064-3d07ddb9f408
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=168496222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixe
d.168496222
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1223069012
Short name T1
Test name
Test status
Simulation time 387613307397 ps
CPU time 232.45 seconds
Started Jun 25 05:57:15 PM PDT 24
Finished Jun 25 06:01:09 PM PDT 24
Peak memory 202100 kb
Host smart-5aebc0c3-a538-47b7-bc39-0df30cfd363f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223069012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1223069012
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.4031819450
Short name T746
Test name
Test status
Simulation time 611929993338 ps
CPU time 315.31 seconds
Started Jun 25 05:57:14 PM PDT 24
Finished Jun 25 06:02:30 PM PDT 24
Peak memory 201856 kb
Host smart-b1b73773-8a8d-432b-8ac4-f04c2f0f6a91
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031819450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.4031819450
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.343005530
Short name T421
Test name
Test status
Simulation time 113814196292 ps
CPU time 657.73 seconds
Started Jun 25 05:57:14 PM PDT 24
Finished Jun 25 06:08:12 PM PDT 24
Peak memory 202168 kb
Host smart-5fce9855-416a-4a4c-a276-505276f9bee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343005530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.343005530
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3696045599
Short name T420
Test name
Test status
Simulation time 24106728845 ps
CPU time 57.28 seconds
Started Jun 25 05:57:18 PM PDT 24
Finished Jun 25 05:58:16 PM PDT 24
Peak memory 201668 kb
Host smart-2d0edad6-bc3c-481b-8dcf-2b356309c1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696045599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3696045599
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.972014686
Short name T692
Test name
Test status
Simulation time 5263168179 ps
CPU time 3.69 seconds
Started Jun 25 05:57:15 PM PDT 24
Finished Jun 25 05:57:19 PM PDT 24
Peak memory 201516 kb
Host smart-86b4b44a-11dc-40a9-932b-e1b201ab046a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972014686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.972014686
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.2109334403
Short name T622
Test name
Test status
Simulation time 6126956521 ps
CPU time 14.94 seconds
Started Jun 25 05:57:08 PM PDT 24
Finished Jun 25 05:57:23 PM PDT 24
Peak memory 201644 kb
Host smart-d6c5becc-6e7d-4806-9e7d-acedd0283390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109334403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.2109334403
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.645037726
Short name T675
Test name
Test status
Simulation time 331729160327 ps
CPU time 395.22 seconds
Started Jun 25 05:57:15 PM PDT 24
Finished Jun 25 06:03:51 PM PDT 24
Peak memory 201900 kb
Host smart-f06bfc96-4be5-44b5-9eeb-fb1dcc00862e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645037726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.
645037726
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.2290506203
Short name T52
Test name
Test status
Simulation time 127929763280 ps
CPU time 149.75 seconds
Started Jun 25 05:57:15 PM PDT 24
Finished Jun 25 05:59:45 PM PDT 24
Peak memory 210556 kb
Host smart-abfdba32-86bf-46cc-a0c2-3a2f12c6eecf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290506203 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.2290506203
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2606550992
Short name T451
Test name
Test status
Simulation time 459198814 ps
CPU time 1.13 seconds
Started Jun 25 05:57:31 PM PDT 24
Finished Jun 25 05:57:38 PM PDT 24
Peak memory 201628 kb
Host smart-fd95c957-2dd2-466f-8631-0b5c0196d33d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606550992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2606550992
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.2415754394
Short name T634
Test name
Test status
Simulation time 341399218169 ps
CPU time 473.49 seconds
Started Jun 25 05:57:23 PM PDT 24
Finished Jun 25 06:05:19 PM PDT 24
Peak memory 201856 kb
Host smart-cdeb6003-99fa-4ff4-93e5-c6abdf296dd5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415754394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.2415754394
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.2692031377
Short name T252
Test name
Test status
Simulation time 347899043971 ps
CPU time 813.41 seconds
Started Jun 25 05:57:23 PM PDT 24
Finished Jun 25 06:10:59 PM PDT 24
Peak memory 201820 kb
Host smart-4a69c970-2329-41ce-b7a5-e691fa9f8972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692031377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2692031377
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.3621104131
Short name T168
Test name
Test status
Simulation time 161873098092 ps
CPU time 353.03 seconds
Started Jun 25 05:57:23 PM PDT 24
Finished Jun 25 06:03:19 PM PDT 24
Peak memory 201856 kb
Host smart-b72eb40e-1c86-4b05-a01f-e54672f1d3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621104131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.3621104131
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.2674484309
Short name T611
Test name
Test status
Simulation time 329197685340 ps
CPU time 311.66 seconds
Started Jun 25 05:57:23 PM PDT 24
Finished Jun 25 06:02:36 PM PDT 24
Peak memory 201880 kb
Host smart-f8884f8f-8ad4-4052-903a-1229bba4205f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674484309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.2674484309
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.4152663562
Short name T411
Test name
Test status
Simulation time 494598014453 ps
CPU time 495.19 seconds
Started Jun 25 05:57:24 PM PDT 24
Finished Jun 25 06:05:42 PM PDT 24
Peak memory 201860 kb
Host smart-ddee7e4a-385c-4609-b739-9dba6f29d488
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152663562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.4152663562
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.2741283307
Short name T42
Test name
Test status
Simulation time 343338561140 ps
CPU time 193.18 seconds
Started Jun 25 05:57:24 PM PDT 24
Finished Jun 25 06:00:39 PM PDT 24
Peak memory 201916 kb
Host smart-98cf84d5-2cb9-4845-ae7b-5095283860d3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741283307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.2741283307
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1940374069
Short name T725
Test name
Test status
Simulation time 612212006367 ps
CPU time 388.62 seconds
Started Jun 25 05:57:25 PM PDT 24
Finished Jun 25 06:03:56 PM PDT 24
Peak memory 201852 kb
Host smart-732949c3-197a-4b1c-bf2f-94d08a42eb38
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940374069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1940374069
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.630916590
Short name T231
Test name
Test status
Simulation time 88663627098 ps
CPU time 488.98 seconds
Started Jun 25 05:57:24 PM PDT 24
Finished Jun 25 06:05:35 PM PDT 24
Peak memory 202088 kb
Host smart-54f03a52-e8a7-4fd6-89d3-38b488a2ca65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630916590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.630916590
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3318568853
Short name T682
Test name
Test status
Simulation time 38999822244 ps
CPU time 95.92 seconds
Started Jun 25 05:57:23 PM PDT 24
Finished Jun 25 05:59:01 PM PDT 24
Peak memory 201676 kb
Host smart-53928b7b-89bf-4cd9-b416-9a0579f96efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318568853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3318568853
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.976565035
Short name T394
Test name
Test status
Simulation time 4460962389 ps
CPU time 10.64 seconds
Started Jun 25 05:57:24 PM PDT 24
Finished Jun 25 05:57:37 PM PDT 24
Peak memory 201668 kb
Host smart-e5721e70-91f1-44df-a72c-85c82a19f670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976565035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.976565035
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2172539422
Short name T399
Test name
Test status
Simulation time 6151763971 ps
CPU time 14.41 seconds
Started Jun 25 05:57:22 PM PDT 24
Finished Jun 25 05:57:38 PM PDT 24
Peak memory 201664 kb
Host smart-014279e9-6511-402a-a54b-6311d5ba9489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172539422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2172539422
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1203292821
Short name T741
Test name
Test status
Simulation time 718468716378 ps
CPU time 1624.64 seconds
Started Jun 25 05:57:33 PM PDT 24
Finished Jun 25 06:24:43 PM PDT 24
Peak memory 201916 kb
Host smart-52d71eb0-1914-41f8-b8af-95d47f2008bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203292821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1203292821
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2579189409
Short name T296
Test name
Test status
Simulation time 154350349925 ps
CPU time 161.27 seconds
Started Jun 25 05:57:31 PM PDT 24
Finished Jun 25 06:00:18 PM PDT 24
Peak memory 217744 kb
Host smart-ff1cbc2c-ec87-4090-a4e2-33d8e412107e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579189409 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2579189409
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.2653280056
Short name T440
Test name
Test status
Simulation time 521445773 ps
CPU time 0.92 seconds
Started Jun 25 05:57:53 PM PDT 24
Finished Jun 25 05:57:55 PM PDT 24
Peak memory 201592 kb
Host smart-7038fcc3-c549-419b-875c-620bca4ce8be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653280056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.2653280056
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1702524204
Short name T712
Test name
Test status
Simulation time 324928071830 ps
CPU time 242.61 seconds
Started Jun 25 05:57:31 PM PDT 24
Finished Jun 25 06:01:39 PM PDT 24
Peak memory 201856 kb
Host smart-102a7fc5-50a0-491c-a6ac-ffdd3f654fa0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702524204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1702524204
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.2720632399
Short name T680
Test name
Test status
Simulation time 493556788325 ps
CPU time 889.72 seconds
Started Jun 25 05:57:32 PM PDT 24
Finished Jun 25 06:12:27 PM PDT 24
Peak memory 201776 kb
Host smart-9dc3d388-763b-4513-acbd-44ea665156dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720632399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.2720632399
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.1181557706
Short name T184
Test name
Test status
Simulation time 163940156562 ps
CPU time 106.13 seconds
Started Jun 25 05:57:31 PM PDT 24
Finished Jun 25 05:59:23 PM PDT 24
Peak memory 201824 kb
Host smart-15f99ed6-3203-49e9-b93f-a41f4460e6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181557706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1181557706
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.224952318
Short name T785
Test name
Test status
Simulation time 325821318774 ps
CPU time 738.68 seconds
Started Jun 25 05:57:33 PM PDT 24
Finished Jun 25 06:09:57 PM PDT 24
Peak memory 202088 kb
Host smart-3810194f-e4d4-42c7-83d9-dbde31958e57
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=224952318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixe
d.224952318
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2493251975
Short name T550
Test name
Test status
Simulation time 556387515985 ps
CPU time 353.63 seconds
Started Jun 25 05:57:33 PM PDT 24
Finished Jun 25 06:03:31 PM PDT 24
Peak memory 201876 kb
Host smart-23c04159-b5cd-4434-922d-fc61308d268b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493251975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2493251975
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.1763030346
Short name T490
Test name
Test status
Simulation time 597775352413 ps
CPU time 761.77 seconds
Started Jun 25 05:57:32 PM PDT 24
Finished Jun 25 06:10:19 PM PDT 24
Peak memory 201856 kb
Host smart-6a60b384-fe35-4494-9a62-af7f3675a1ac
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763030346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.1763030346
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.3287033905
Short name T561
Test name
Test status
Simulation time 104673342276 ps
CPU time 388.86 seconds
Started Jun 25 05:57:39 PM PDT 24
Finished Jun 25 06:04:10 PM PDT 24
Peak memory 202188 kb
Host smart-a0431d60-d662-49c1-a07b-1797ffcf143c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287033905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3287033905
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.2343116795
Short name T357
Test name
Test status
Simulation time 32923025331 ps
CPU time 18.82 seconds
Started Jun 25 05:57:40 PM PDT 24
Finished Jun 25 05:58:01 PM PDT 24
Peak memory 201672 kb
Host smart-ac62a014-692c-4779-90ba-21e8c5e92fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343116795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.2343116795
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.2179519804
Short name T760
Test name
Test status
Simulation time 4780035684 ps
CPU time 8.49 seconds
Started Jun 25 05:57:31 PM PDT 24
Finished Jun 25 05:57:45 PM PDT 24
Peak memory 201660 kb
Host smart-748f4e20-1bd4-458f-886b-d15900f96303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179519804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2179519804
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.829043546
Short name T107
Test name
Test status
Simulation time 5639922266 ps
CPU time 7.11 seconds
Started Jun 25 05:57:30 PM PDT 24
Finished Jun 25 05:57:43 PM PDT 24
Peak memory 201696 kb
Host smart-e03b12bf-a6e3-4003-9e40-097a090a2391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829043546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.829043546
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.384258416
Short name T631
Test name
Test status
Simulation time 9116598713 ps
CPU time 22.15 seconds
Started Jun 25 05:57:40 PM PDT 24
Finished Jun 25 05:58:04 PM PDT 24
Peak memory 201656 kb
Host smart-22aa4d5c-036b-44de-bfdc-9f5b0adc6968
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384258416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
384258416
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2257147454
Short name T47
Test name
Test status
Simulation time 363194263148 ps
CPU time 140.14 seconds
Started Jun 25 05:57:52 PM PDT 24
Finished Jun 25 06:00:13 PM PDT 24
Peak memory 210164 kb
Host smart-a9b33627-7ddd-4f60-8012-34fbc8c59ca2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257147454 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.2257147454
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3437649564
Short name T674
Test name
Test status
Simulation time 443818562 ps
CPU time 1.1 seconds
Started Jun 25 05:57:53 PM PDT 24
Finished Jun 25 05:57:56 PM PDT 24
Peak memory 201592 kb
Host smart-cceb184d-8382-462d-8bd6-77d6ae6e7a21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437649564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3437649564
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.3002974899
Short name T476
Test name
Test status
Simulation time 163101539625 ps
CPU time 85.45 seconds
Started Jun 25 05:57:54 PM PDT 24
Finished Jun 25 05:59:20 PM PDT 24
Peak memory 201824 kb
Host smart-59f8adfa-55d8-41c3-a72e-c71a74adfc69
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002974899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.3002974899
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2764320273
Short name T607
Test name
Test status
Simulation time 164588307507 ps
CPU time 390.92 seconds
Started Jun 25 05:57:46 PM PDT 24
Finished Jun 25 06:04:18 PM PDT 24
Peak memory 201976 kb
Host smart-decefd89-a1cf-424f-adf7-21376c905ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764320273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2764320273
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.2550018162
Short name T205
Test name
Test status
Simulation time 490357257935 ps
CPU time 89.19 seconds
Started Jun 25 05:57:54 PM PDT 24
Finished Jun 25 05:59:24 PM PDT 24
Peak memory 201844 kb
Host smart-c8876109-32f1-4e4c-a066-86806f871deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550018162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2550018162
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.62440760
Short name T727
Test name
Test status
Simulation time 334786376616 ps
CPU time 367.47 seconds
Started Jun 25 05:57:40 PM PDT 24
Finished Jun 25 06:03:49 PM PDT 24
Peak memory 201748 kb
Host smart-747de329-8582-42d7-978e-617b8abf14ac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=62440760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt
_fixed.62440760
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1613391114
Short name T525
Test name
Test status
Simulation time 325839552833 ps
CPU time 390.48 seconds
Started Jun 25 05:57:53 PM PDT 24
Finished Jun 25 06:04:24 PM PDT 24
Peak memory 201912 kb
Host smart-b3ccb97a-0c7d-4792-afe8-893c7f923043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613391114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1613391114
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.3750825953
Short name T41
Test name
Test status
Simulation time 161306796851 ps
CPU time 348.2 seconds
Started Jun 25 05:57:53 PM PDT 24
Finished Jun 25 06:03:43 PM PDT 24
Peak memory 201812 kb
Host smart-3d34074f-f081-4df4-831c-333beaa4e65c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750825953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.3750825953
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.2047580959
Short name T338
Test name
Test status
Simulation time 527928239097 ps
CPU time 627.77 seconds
Started Jun 25 05:57:39 PM PDT 24
Finished Jun 25 06:08:09 PM PDT 24
Peak memory 201868 kb
Host smart-d3f24e2a-ef84-499b-944c-78e257b91d03
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047580959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.2047580959
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1754370584
Short name T623
Test name
Test status
Simulation time 203513955635 ps
CPU time 119.65 seconds
Started Jun 25 05:57:53 PM PDT 24
Finished Jun 25 05:59:54 PM PDT 24
Peak memory 201824 kb
Host smart-9b461d38-dd05-4d15-92b8-f473e3804e94
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754370584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.1754370584
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.462829494
Short name T641
Test name
Test status
Simulation time 126427348298 ps
CPU time 441.65 seconds
Started Jun 25 05:57:45 PM PDT 24
Finished Jun 25 06:05:08 PM PDT 24
Peak memory 202196 kb
Host smart-a84185ba-a301-47a1-b58f-29c01c2315f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462829494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.462829494
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.916707365
Short name T544
Test name
Test status
Simulation time 25417095630 ps
CPU time 9.92 seconds
Started Jun 25 05:57:45 PM PDT 24
Finished Jun 25 05:57:56 PM PDT 24
Peak memory 201652 kb
Host smart-daa12e32-01a6-456e-8346-5652a055d2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916707365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.916707365
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1098183747
Short name T721
Test name
Test status
Simulation time 5512313795 ps
CPU time 3.7 seconds
Started Jun 25 05:57:46 PM PDT 24
Finished Jun 25 05:57:51 PM PDT 24
Peak memory 201516 kb
Host smart-3915f10a-8bbc-488b-b2ef-2381284e9b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098183747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1098183747
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3883087522
Short name T556
Test name
Test status
Simulation time 6025606287 ps
CPU time 14.79 seconds
Started Jun 25 05:57:50 PM PDT 24
Finished Jun 25 05:58:07 PM PDT 24
Peak memory 201640 kb
Host smart-8905a316-a272-46f3-8977-06a66117c9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883087522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3883087522
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.2523602392
Short name T765
Test name
Test status
Simulation time 358363650177 ps
CPU time 226.39 seconds
Started Jun 25 05:57:47 PM PDT 24
Finished Jun 25 06:01:34 PM PDT 24
Peak memory 201916 kb
Host smart-0af40ac9-0050-409c-b4e5-533cb4c95a65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523602392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.2523602392
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2478415874
Short name T21
Test name
Test status
Simulation time 378568112772 ps
CPU time 323.08 seconds
Started Jun 25 05:57:47 PM PDT 24
Finished Jun 25 06:03:11 PM PDT 24
Peak memory 210492 kb
Host smart-5ad59d9a-0242-4626-b2bb-66935ed5727c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478415874 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2478415874
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.890208953
Short name T94
Test name
Test status
Simulation time 355383930 ps
CPU time 1.45 seconds
Started Jun 25 05:52:10 PM PDT 24
Finished Jun 25 05:52:13 PM PDT 24
Peak memory 201612 kb
Host smart-16cf19e2-1da4-43fd-ad56-00fd2d473bfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890208953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.890208953
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.4014561373
Short name T260
Test name
Test status
Simulation time 541207966754 ps
CPU time 775.79 seconds
Started Jun 25 05:51:59 PM PDT 24
Finished Jun 25 06:04:56 PM PDT 24
Peak memory 201844 kb
Host smart-c318bb43-09cc-449d-aded-88057ea3dfce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014561373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.4014561373
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3487057341
Short name T256
Test name
Test status
Simulation time 197547731752 ps
CPU time 440.06 seconds
Started Jun 25 05:52:05 PM PDT 24
Finished Jun 25 05:59:27 PM PDT 24
Peak memory 201620 kb
Host smart-c35f18f5-4257-4466-9354-8384f745aa68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487057341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3487057341
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.944712236
Short name T597
Test name
Test status
Simulation time 331523506134 ps
CPU time 794.8 seconds
Started Jun 25 05:52:00 PM PDT 24
Finished Jun 25 06:05:16 PM PDT 24
Peak memory 201876 kb
Host smart-867d9c1b-1143-4533-aa5c-580578ad4b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944712236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.944712236
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2917980265
Short name T656
Test name
Test status
Simulation time 494713125097 ps
CPU time 1132.1 seconds
Started Jun 25 05:52:00 PM PDT 24
Finished Jun 25 06:10:53 PM PDT 24
Peak memory 201888 kb
Host smart-5ac5d574-1f1d-4b19-b639-861dc5660c54
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917980265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2917980265
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.4056117000
Short name T731
Test name
Test status
Simulation time 320846410975 ps
CPU time 461.71 seconds
Started Jun 25 05:52:01 PM PDT 24
Finished Jun 25 05:59:45 PM PDT 24
Peak memory 201872 kb
Host smart-5d554141-c3cf-47df-b9ab-e0aeaa1c525e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056117000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.4056117000
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3574704165
Short name T751
Test name
Test status
Simulation time 490665915181 ps
CPU time 1071.59 seconds
Started Jun 25 05:52:01 PM PDT 24
Finished Jun 25 06:09:55 PM PDT 24
Peak memory 201904 kb
Host smart-8989920f-32f1-43b6-af1e-96d3c0bb071a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574704165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3574704165
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.414739320
Short name T216
Test name
Test status
Simulation time 611289184618 ps
CPU time 1287.9 seconds
Started Jun 25 05:52:03 PM PDT 24
Finished Jun 25 06:13:33 PM PDT 24
Peak memory 201916 kb
Host smart-4cef38b1-16bd-401e-b7ce-5f50dd316bbe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414739320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_w
akeup.414739320
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.793077019
Short name T403
Test name
Test status
Simulation time 190207296699 ps
CPU time 424.1 seconds
Started Jun 25 05:52:05 PM PDT 24
Finished Jun 25 05:59:11 PM PDT 24
Peak memory 201900 kb
Host smart-cd7fa3df-916c-45c7-ad32-9737087af4a4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793077019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.a
dc_ctrl_filters_wakeup_fixed.793077019
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.612854000
Short name T677
Test name
Test status
Simulation time 114530505687 ps
CPU time 338.62 seconds
Started Jun 25 05:52:09 PM PDT 24
Finished Jun 25 05:57:50 PM PDT 24
Peak memory 202176 kb
Host smart-f18f3e60-80cc-469b-b2d2-deeb8ff08722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612854000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.612854000
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.770964524
Short name T358
Test name
Test status
Simulation time 42160613198 ps
CPU time 67.21 seconds
Started Jun 25 05:52:10 PM PDT 24
Finished Jun 25 05:53:19 PM PDT 24
Peak memory 201620 kb
Host smart-f4d21fe7-acac-4044-beb1-11bebf0d4aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770964524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.770964524
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2558327804
Short name T483
Test name
Test status
Simulation time 4533687825 ps
CPU time 5.89 seconds
Started Jun 25 05:52:11 PM PDT 24
Finished Jun 25 05:52:19 PM PDT 24
Peak memory 201684 kb
Host smart-ba461683-bf27-4d84-b2d1-5edb0df166bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558327804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2558327804
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.1935551902
Short name T439
Test name
Test status
Simulation time 6065556434 ps
CPU time 14.99 seconds
Started Jun 25 05:52:01 PM PDT 24
Finished Jun 25 05:52:18 PM PDT 24
Peak memory 201672 kb
Host smart-030fa7f2-3c11-4f81-b0f9-7f58654660fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935551902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1935551902
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.1075369309
Short name T619
Test name
Test status
Simulation time 415310801388 ps
CPU time 1087.01 seconds
Started Jun 25 05:52:09 PM PDT 24
Finished Jun 25 06:10:18 PM PDT 24
Peak memory 218528 kb
Host smart-0f22b3c0-7277-4f14-9f83-49b8d5c67ff8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075369309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
1075369309
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.4114116590
Short name T287
Test name
Test status
Simulation time 118179356485 ps
CPU time 327.55 seconds
Started Jun 25 05:52:12 PM PDT 24
Finished Jun 25 05:57:41 PM PDT 24
Peak memory 210564 kb
Host smart-f5522259-50f2-4048-8ec8-4eac1c5798eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114116590 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.4114116590
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.514665534
Short name T387
Test name
Test status
Simulation time 438305821 ps
CPU time 1.66 seconds
Started Jun 25 05:52:13 PM PDT 24
Finished Jun 25 05:52:16 PM PDT 24
Peak memory 201612 kb
Host smart-d2459eda-5abe-46ed-a239-c9be8bebf6b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514665534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.514665534
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.59646285
Short name T332
Test name
Test status
Simulation time 213724721566 ps
CPU time 66.71 seconds
Started Jun 25 05:52:09 PM PDT 24
Finished Jun 25 05:53:18 PM PDT 24
Peak memory 201932 kb
Host smart-c4e62af4-6492-40c7-bcb9-ce5adbdf4790
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59646285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gating
.59646285
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.4155880242
Short name T442
Test name
Test status
Simulation time 168028068202 ps
CPU time 189.96 seconds
Started Jun 25 05:52:13 PM PDT 24
Finished Jun 25 05:55:24 PM PDT 24
Peak memory 201876 kb
Host smart-c25b9b4b-5010-4a71-b71a-157d1ab5c4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155880242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.4155880242
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.293898873
Short name T155
Test name
Test status
Simulation time 333714515279 ps
CPU time 540.33 seconds
Started Jun 25 05:52:08 PM PDT 24
Finished Jun 25 06:01:09 PM PDT 24
Peak memory 201860 kb
Host smart-3fd387a8-8d64-4116-84a0-ccfb3b9d461e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293898873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.293898873
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3970949627
Short name T115
Test name
Test status
Simulation time 163548367048 ps
CPU time 385.77 seconds
Started Jun 25 05:52:09 PM PDT 24
Finished Jun 25 05:58:37 PM PDT 24
Peak memory 201692 kb
Host smart-33786cf4-0418-4f0e-af26-91ed61d347de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970949627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3970949627
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.187849527
Short name T116
Test name
Test status
Simulation time 499131698772 ps
CPU time 158.51 seconds
Started Jun 25 05:52:08 PM PDT 24
Finished Jun 25 05:54:48 PM PDT 24
Peak memory 201880 kb
Host smart-890b549d-c084-4654-8591-1e8a8ab10fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187849527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.187849527
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3879963452
Short name T562
Test name
Test status
Simulation time 319786836009 ps
CPU time 715.06 seconds
Started Jun 25 05:52:09 PM PDT 24
Finished Jun 25 06:04:06 PM PDT 24
Peak memory 201848 kb
Host smart-b9c0b379-1580-4636-b722-a8e4e87db33c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879963452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3879963452
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2401434328
Short name T157
Test name
Test status
Simulation time 182008720887 ps
CPU time 98.04 seconds
Started Jun 25 05:52:09 PM PDT 24
Finished Jun 25 05:53:48 PM PDT 24
Peak memory 201872 kb
Host smart-7d3f6d3e-5994-4277-abe9-89593802a5b9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401434328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2401434328
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1405531921
Short name T566
Test name
Test status
Simulation time 406175635294 ps
CPU time 215.46 seconds
Started Jun 25 05:52:09 PM PDT 24
Finished Jun 25 05:55:47 PM PDT 24
Peak memory 201868 kb
Host smart-6bbf3b33-e5fb-4d1f-91cf-c8c1bd8a9e8b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405531921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.1405531921
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3900676371
Short name T352
Test name
Test status
Simulation time 79217126602 ps
CPU time 315.79 seconds
Started Jun 25 05:52:12 PM PDT 24
Finished Jun 25 05:57:29 PM PDT 24
Peak memory 202196 kb
Host smart-f6591d5b-a07f-4fb4-ae23-59e5a56ff8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900676371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3900676371
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.3951058180
Short name T179
Test name
Test status
Simulation time 37956812450 ps
CPU time 82.18 seconds
Started Jun 25 05:52:09 PM PDT 24
Finished Jun 25 05:53:34 PM PDT 24
Peak memory 201688 kb
Host smart-e0fd9421-b089-4bae-96f1-0f388f3e8afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951058180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3951058180
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2532104164
Short name T120
Test name
Test status
Simulation time 2950223386 ps
CPU time 2.5 seconds
Started Jun 25 05:52:08 PM PDT 24
Finished Jun 25 05:52:13 PM PDT 24
Peak memory 201592 kb
Host smart-68106bf8-df71-40d1-ab9c-eda591966fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532104164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2532104164
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.729841043
Short name T384
Test name
Test status
Simulation time 5954739117 ps
CPU time 13.42 seconds
Started Jun 25 05:52:09 PM PDT 24
Finished Jun 25 05:52:25 PM PDT 24
Peak memory 201656 kb
Host smart-12cf19ca-5449-4744-b478-14015aa87617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729841043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.729841043
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.4260153802
Short name T163
Test name
Test status
Simulation time 328969864485 ps
CPU time 81.36 seconds
Started Jun 25 05:52:09 PM PDT 24
Finished Jun 25 05:53:32 PM PDT 24
Peak memory 201916 kb
Host smart-ecd82e7d-1625-46ff-9654-a4707c1c1859
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260153802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
4260153802
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.644365329
Short name T105
Test name
Test status
Simulation time 221358947902 ps
CPU time 204.18 seconds
Started Jun 25 05:52:09 PM PDT 24
Finished Jun 25 05:55:35 PM PDT 24
Peak memory 210516 kb
Host smart-1c677d27-ee2a-47d6-a56e-c77405a3318d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644365329 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.644365329
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.946109809
Short name T413
Test name
Test status
Simulation time 397230412 ps
CPU time 0.74 seconds
Started Jun 25 05:52:08 PM PDT 24
Finished Jun 25 05:52:10 PM PDT 24
Peak memory 201608 kb
Host smart-fc58d4f9-8195-481d-924f-21485a2e9b39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946109809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.946109809
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.4177626027
Short name T27
Test name
Test status
Simulation time 158838614505 ps
CPU time 347.24 seconds
Started Jun 25 05:52:09 PM PDT 24
Finished Jun 25 05:57:58 PM PDT 24
Peak memory 201880 kb
Host smart-73d58802-d142-4f63-82ce-6c65fbfe678b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177626027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.4177626027
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.3135334431
Short name T708
Test name
Test status
Simulation time 322790497125 ps
CPU time 116.76 seconds
Started Jun 25 05:52:13 PM PDT 24
Finished Jun 25 05:54:11 PM PDT 24
Peak memory 201836 kb
Host smart-8079bf80-ae1b-4d56-b0ac-ff7d8d46a3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135334431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.3135334431
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3701350195
Short name T715
Test name
Test status
Simulation time 160550470919 ps
CPU time 52.9 seconds
Started Jun 25 05:52:10 PM PDT 24
Finished Jun 25 05:53:05 PM PDT 24
Peak memory 201812 kb
Host smart-2e3fe748-d3ec-410d-8bda-c3d08e73166b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701350195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.3701350195
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.82065868
Short name T461
Test name
Test status
Simulation time 484665163059 ps
CPU time 141.39 seconds
Started Jun 25 05:52:10 PM PDT 24
Finished Jun 25 05:54:33 PM PDT 24
Peak memory 201936 kb
Host smart-e27f4e4f-b113-4041-b025-5887c0d4a0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82065868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.82065868
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.3980851555
Short name T389
Test name
Test status
Simulation time 489108148585 ps
CPU time 557.09 seconds
Started Jun 25 05:52:10 PM PDT 24
Finished Jun 25 06:01:29 PM PDT 24
Peak memory 201760 kb
Host smart-533b1091-c0d4-4a90-8a79-7c67ea5379df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980851555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.3980851555
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.1703509696
Short name T588
Test name
Test status
Simulation time 172145112939 ps
CPU time 206.28 seconds
Started Jun 25 05:52:11 PM PDT 24
Finished Jun 25 05:55:39 PM PDT 24
Peak memory 201816 kb
Host smart-363af881-6ce1-43ba-89cd-5c2a483a4348
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703509696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.1703509696
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1375744384
Short name T512
Test name
Test status
Simulation time 399901993947 ps
CPU time 118.36 seconds
Started Jun 25 05:52:08 PM PDT 24
Finished Jun 25 05:54:07 PM PDT 24
Peak memory 201840 kb
Host smart-b3387b1a-7c28-4359-8729-1bda85c916db
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375744384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1375744384
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.2047580225
Short name T102
Test name
Test status
Simulation time 79701063712 ps
CPU time 314.09 seconds
Started Jun 25 05:52:13 PM PDT 24
Finished Jun 25 05:57:28 PM PDT 24
Peak memory 202212 kb
Host smart-d57448a4-96eb-472a-bf6c-f9b4d28a01a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047580225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.2047580225
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.1475611408
Short name T381
Test name
Test status
Simulation time 40455649311 ps
CPU time 14.9 seconds
Started Jun 25 05:52:14 PM PDT 24
Finished Jun 25 05:52:29 PM PDT 24
Peak memory 201664 kb
Host smart-78a88618-8b1e-4964-b3a5-c3464eb0e0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475611408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.1475611408
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.820804046
Short name T441
Test name
Test status
Simulation time 4651195601 ps
CPU time 10.93 seconds
Started Jun 25 05:52:13 PM PDT 24
Finished Jun 25 05:52:25 PM PDT 24
Peak memory 201660 kb
Host smart-5a085866-146c-44db-90aa-8e182d904e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820804046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.820804046
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.4024843161
Short name T632
Test name
Test status
Simulation time 5850252648 ps
CPU time 14.98 seconds
Started Jun 25 05:52:10 PM PDT 24
Finished Jun 25 05:52:27 PM PDT 24
Peak memory 201680 kb
Host smart-3df5a3e4-135c-4e9d-82ad-234603b07ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024843161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.4024843161
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.950020486
Short name T278
Test name
Test status
Simulation time 368813899786 ps
CPU time 866.5 seconds
Started Jun 25 05:52:17 PM PDT 24
Finished Jun 25 06:06:44 PM PDT 24
Peak memory 201876 kb
Host smart-2e0cdefe-3dd8-4ad1-9fb7-8ac829579cdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950020486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.950020486
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.1693280218
Short name T444
Test name
Test status
Simulation time 430956086 ps
CPU time 1.6 seconds
Started Jun 25 05:52:16 PM PDT 24
Finished Jun 25 05:52:19 PM PDT 24
Peak memory 201624 kb
Host smart-6fe16493-0e49-418f-bf9e-aedd8ff8e7a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693280218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1693280218
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.998792180
Short name T574
Test name
Test status
Simulation time 163880200879 ps
CPU time 383.56 seconds
Started Jun 25 05:52:16 PM PDT 24
Finished Jun 25 05:58:40 PM PDT 24
Peak memory 201964 kb
Host smart-700a3c08-be1b-414b-a935-035d369c3679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998792180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.998792180
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2623474381
Short name T190
Test name
Test status
Simulation time 330173359796 ps
CPU time 166.51 seconds
Started Jun 25 05:52:09 PM PDT 24
Finished Jun 25 05:54:57 PM PDT 24
Peak memory 201872 kb
Host smart-1be9dc6c-92e0-4424-a454-b52be6e4f0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623474381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2623474381
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2804940087
Short name T423
Test name
Test status
Simulation time 324889550531 ps
CPU time 761.03 seconds
Started Jun 25 05:52:17 PM PDT 24
Finished Jun 25 06:04:59 PM PDT 24
Peak memory 201788 kb
Host smart-41ff8fca-eae7-4df1-a7bc-1d3754400892
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804940087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2804940087
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.4221393303
Short name T222
Test name
Test status
Simulation time 326339573583 ps
CPU time 93.73 seconds
Started Jun 25 05:52:12 PM PDT 24
Finished Jun 25 05:53:47 PM PDT 24
Peak memory 201848 kb
Host smart-2992bef6-53e4-49bc-8b27-b282673e2dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221393303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.4221393303
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2511479059
Short name T558
Test name
Test status
Simulation time 323915190522 ps
CPU time 188.86 seconds
Started Jun 25 05:52:16 PM PDT 24
Finished Jun 25 05:55:26 PM PDT 24
Peak memory 201864 kb
Host smart-4a0f98d2-e765-4efb-a669-299036161f3a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511479059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2511479059
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.842554624
Short name T742
Test name
Test status
Simulation time 183543905844 ps
CPU time 422.58 seconds
Started Jun 25 05:52:11 PM PDT 24
Finished Jun 25 05:59:16 PM PDT 24
Peak memory 201860 kb
Host smart-23a24c11-5722-4e74-8b0e-57753433e855
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842554624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_w
akeup.842554624
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.2682188707
Short name T374
Test name
Test status
Simulation time 197742262596 ps
CPU time 359.19 seconds
Started Jun 25 05:52:08 PM PDT 24
Finished Jun 25 05:58:09 PM PDT 24
Peak memory 201840 kb
Host smart-19795e3d-7424-4d93-816b-d50fba9aa962
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682188707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.2682188707
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.4226991747
Short name T685
Test name
Test status
Simulation time 74094147830 ps
CPU time 379.74 seconds
Started Jun 25 05:52:17 PM PDT 24
Finished Jun 25 05:58:38 PM PDT 24
Peak memory 202076 kb
Host smart-f219938c-bfce-433c-83c9-8ecf01ac434b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226991747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.4226991747
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.3964038764
Short name T126
Test name
Test status
Simulation time 40132338189 ps
CPU time 24.2 seconds
Started Jun 25 05:52:12 PM PDT 24
Finished Jun 25 05:52:38 PM PDT 24
Peak memory 201664 kb
Host smart-a01aaa20-dbaf-457f-9ea3-85e765e7d6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964038764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3964038764
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2951690254
Short name T661
Test name
Test status
Simulation time 4283243606 ps
CPU time 9.23 seconds
Started Jun 25 05:52:08 PM PDT 24
Finished Jun 25 05:52:19 PM PDT 24
Peak memory 201704 kb
Host smart-6fa1765c-e105-4972-9e31-f620f90cad8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951690254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2951690254
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.4162716729
Short name T418
Test name
Test status
Simulation time 5615691520 ps
CPU time 3.74 seconds
Started Jun 25 05:52:14 PM PDT 24
Finished Jun 25 05:52:18 PM PDT 24
Peak memory 201408 kb
Host smart-9961831b-367b-487e-96ec-74b983b27be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162716729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.4162716729
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.61770954
Short name T294
Test name
Test status
Simulation time 1419472005994 ps
CPU time 1095.36 seconds
Started Jun 25 05:52:11 PM PDT 24
Finished Jun 25 06:10:28 PM PDT 24
Peak memory 202248 kb
Host smart-2463dba1-3f58-4ce2-af12-2c083f967b51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61770954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.61770954
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1294563633
Short name T519
Test name
Test status
Simulation time 459681039 ps
CPU time 1.25 seconds
Started Jun 25 05:52:19 PM PDT 24
Finished Jun 25 05:52:22 PM PDT 24
Peak memory 201620 kb
Host smart-e3fd3e65-352e-4f4b-9ac3-7e8311425908
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294563633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1294563633
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.3480720809
Short name T254
Test name
Test status
Simulation time 166133318466 ps
CPU time 162.17 seconds
Started Jun 25 05:52:17 PM PDT 24
Finished Jun 25 05:55:01 PM PDT 24
Peak memory 201828 kb
Host smart-d96cc209-7745-4e4e-8c7a-ca662bb37afa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480720809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.3480720809
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2123093222
Short name T627
Test name
Test status
Simulation time 185662453686 ps
CPU time 409.6 seconds
Started Jun 25 05:52:16 PM PDT 24
Finished Jun 25 05:59:06 PM PDT 24
Peak memory 201872 kb
Host smart-4caec70b-c009-451d-8591-9a2d39e5f733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123093222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2123093222
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.1475024572
Short name T300
Test name
Test status
Simulation time 489215475794 ps
CPU time 280.37 seconds
Started Jun 25 05:52:11 PM PDT 24
Finished Jun 25 05:56:53 PM PDT 24
Peak memory 201876 kb
Host smart-ecd3bab7-a13e-469e-ae97-37d13acce972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475024572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.1475024572
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2656980351
Short name T61
Test name
Test status
Simulation time 326011994561 ps
CPU time 753.96 seconds
Started Jun 25 05:52:11 PM PDT 24
Finished Jun 25 06:04:46 PM PDT 24
Peak memory 201776 kb
Host smart-10a9c91d-b29d-4f19-8a0f-632b9409023a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656980351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.2656980351
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.651824372
Short name T551
Test name
Test status
Simulation time 164116417146 ps
CPU time 187.15 seconds
Started Jun 25 05:52:10 PM PDT 24
Finished Jun 25 05:55:19 PM PDT 24
Peak memory 201880 kb
Host smart-2693c31f-483e-44a0-9469-a804607d4ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651824372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.651824372
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.714902612
Short name T178
Test name
Test status
Simulation time 324424086326 ps
CPU time 86.73 seconds
Started Jun 25 05:52:09 PM PDT 24
Finished Jun 25 05:53:38 PM PDT 24
Peak memory 201908 kb
Host smart-4d4ca196-2178-4652-ac6f-f24797ecd572
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=714902612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.714902612
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1121669511
Short name T729
Test name
Test status
Simulation time 204024340398 ps
CPU time 31.48 seconds
Started Jun 25 05:52:18 PM PDT 24
Finished Jun 25 05:52:52 PM PDT 24
Peak memory 201848 kb
Host smart-445b6b79-c4b2-471b-bcac-8d55b9f13f37
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121669511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.1121669511
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3558554672
Short name T353
Test name
Test status
Simulation time 84914456542 ps
CPU time 303.51 seconds
Started Jun 25 05:52:17 PM PDT 24
Finished Jun 25 05:57:23 PM PDT 24
Peak memory 202188 kb
Host smart-9a2ab0cb-ba2d-4032-b696-c55c6b1cf68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558554672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3558554672
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.531779154
Short name T599
Test name
Test status
Simulation time 25862301963 ps
CPU time 14.73 seconds
Started Jun 25 05:52:18 PM PDT 24
Finished Jun 25 05:52:35 PM PDT 24
Peak memory 201672 kb
Host smart-b70dbb2f-1b1b-486b-a8f2-00cedc231811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531779154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.531779154
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.3569439693
Short name T484
Test name
Test status
Simulation time 4885782010 ps
CPU time 5.96 seconds
Started Jun 25 05:52:17 PM PDT 24
Finished Jun 25 05:52:25 PM PDT 24
Peak memory 201676 kb
Host smart-d74ff7de-ac81-4d7a-9b91-98db1a118bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569439693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3569439693
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.252559098
Short name T396
Test name
Test status
Simulation time 5951067178 ps
CPU time 14.39 seconds
Started Jun 25 05:52:11 PM PDT 24
Finished Jun 25 05:52:27 PM PDT 24
Peak memory 201688 kb
Host smart-6c0c66c0-8541-48e9-93c6-89752ad6a28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252559098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.252559098
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.1594391541
Short name T121
Test name
Test status
Simulation time 330874142294 ps
CPU time 714.02 seconds
Started Jun 25 05:52:18 PM PDT 24
Finished Jun 25 06:04:14 PM PDT 24
Peak memory 201864 kb
Host smart-2594ad12-9984-4b51-adfb-87fa1cef92d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594391541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
1594391541
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2734198943
Short name T336
Test name
Test status
Simulation time 329467122119 ps
CPU time 241.45 seconds
Started Jun 25 05:52:17 PM PDT 24
Finished Jun 25 05:56:21 PM PDT 24
Peak memory 218668 kb
Host smart-03447480-ae90-4241-90dd-540944195420
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734198943 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2734198943
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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