Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7224	1			T5	44		T10	20		T12	52
testmodes[AdcCtrlTestmodeNormal]	5511	1			T2	2		T3	3		T4	1
testmodes[AdcCtrlTestmodeLowpower]	5756	1			T1	2		T4	1		T5	44
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	4028	1			T5	14		T10	19		T12	31
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1697	1			T5	18		T12	10		T55	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1383	1			T5	12		T12	10		T47	16
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1763	1			T5	14		T12	16		T55	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2034	1			T2	1		T3	2		T5	12
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1364	1			T5	13		T12	15		T14	2
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1325	1			T5	15		T12	5		T47	15
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1441	1			T4	1		T5	10		T12	21
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2757	1			T1	1		T5	19		T6	2