Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26574

1

T1

12

T2

2

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23056

1

T1

6

T2

1

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3518

1

T1

6

T2

1

T6

36

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20897

1

T1

6

T4

21

T5

128

auto[1]

5677

1

T1

6

T2

2

T3

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22513

1

T1

12

T2

2

T3

3

auto[1]

4061

1

T4

11

T7

1

T9

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	9	1			T214	6		T215	3		-	-
values[0]	42	1			T104	2		T216	9		T217	5
values[1]	550	1			T1	6		T6	13		T45	25
values[2]	3006	1			T3	3		T8	28		T11	20
values[3]	460	1			T12	13		T43	1		T170	1
values[4]	697	1			T9	7		T124	1		T24	20
values[5]	621	1			T45	14		T46	47		T29	1
values[6]	720	1			T2	1		T6	23		T11	20
values[7]	765	1			T2	1		T28	31		T74	1
values[8]	909	1			T123	1		T74	24		T218	1
values[9]	1244	1			T1	6		T4	21		T7	10
minimum	17551	1			T5	128		T10	20		T50	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	901	1			T1	6		T6	13		T45	25
values[1]	2813	1			T3	3		T8	28		T12	13
values[2]	533	1			T11	20		T43	1		T14	4
values[3]	460	1			T9	7		T124	1		T24	20
values[4]	993	1			T6	15		T45	14		T46	47
values[5]	479	1			T2	1		T6	8		T11	20
values[6]	888	1			T2	1		T123	1		T28	31
values[7]	839	1			T4	18		T24	17		T74	25
values[8]	989	1			T1	6		T4	3		T7	10
values[9]	115	1			T9	12		T162	13		T165	1
minimum	17564	1			T5	128		T10	20		T50	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22552

1

T1

2

T2

2

T3

3

auto[1]

4022

1

T1

10

T4

8

T6

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T45	12		T150	8		T28	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T1	6		T6	13		T152	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1462	1			T3	3		T8	28		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T46	15		T35	1		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T11	12		T43	1		T14	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T28	8		T32	3		T220	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T9	1		T24	9		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T124	1		T151	1		T221	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T150	3		T170	1		T32	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	358	1			T6	15		T45	10		T46	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T2	1		T59	15		T154	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T6	8		T11	11		T220	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T123	1		T222	15		T156	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	1		T28	18		T155	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T4	8		T24	7		T60	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T74	14		T223	1		T163	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T1	6		T4	2		T7	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T91	12		T194	13		T35	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T9	1		T162	1		T165	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T224	1		T225	7		T158	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17427	1			T5	128		T10	20		T50	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T45	13		T28	2		T146	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T152	28		T161	2		T226	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	975	1			T12	12		T24	10		T189	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T46	17		T35	1		T36	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T11	8		T60	10		T227	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T28	10		T32	10		T220	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T9	6		T24	11		T228	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T221	2		T229	7		T230	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T32	13		T152	8		T161	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T45	4		T46	23		T60	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T59	11		T154	9		T231	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T11	9		T220	13		T166	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T156	13		T232	10		T230	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T28	13		T155	12		T233	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T4	10		T24	10		T155	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T74	11		T223	10		T163	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T4	1		T7	1		T11	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T91	10		T194	13		T234	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T9	11		T162	12		T38	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T224	1		T225	5		T158	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T74	1		T35	3		T49	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T214	3		T215	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T104	2		T216	1		T235	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T217	1		T236	8		T237	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T45	12		T161	12		T238	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	6		T6	13		T152	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1597	1			T3	3		T8	28		T11	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T46	15		T35	1		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T12	1		T43	1		T170	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T32	3		T220	1		T37	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T9	1		T24	9		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T124	1		T28	8		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T29	1		T152	1		T179	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T45	10		T46	24		T179	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T2	1		T150	3		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T6	23		T11	11		T150	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T154	9		T222	15		T156	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	1		T28	18		T74	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T123	1		T218	1		T239	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T74	13		T223	1		T163	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T1	6		T4	10		T7	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	363	1			T91	12		T194	13		T35	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17425	1			T5	128		T10	20		T50	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T214	3		T215	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T216	8		T235	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T217	4		T237	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T45	13		T161	7		T238	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T152	28		T161	2		T226	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1039	1			T11	8		T24	10		T28	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T46	17		T35	1		T36	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T12	12		T154	5		T60	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T32	10		T220	13		T240	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T9	6		T24	11		T227	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T28	10		T221	2		T229	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T152	8		T162	10		T109	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T45	4		T46	23		T238	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T32	13		T59	11		T161	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	9		T60	1		T220	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T154	9		T156	13		T231	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T28	13		T155	12		T233	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T239	21		T232	6		T230	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T74	11		T223	10		T163	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T4	11		T7	1		T9	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T91	10		T194	13		T234	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T74	1		T35	3		T49	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T45	14		T150	1		T28	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T1	1		T6	1		T152	30
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T3	3		T8	2		T12	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T46	18		T35	2		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	9		T43	1		T14	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T28	11		T32	11		T220	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T9	7		T24	12		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T124	1		T151	1		T221	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T150	1		T170	1		T32	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T6	1		T45	5		T46	25
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T2	1		T59	13		T154	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T6	1		T11	10		T220	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T123	1		T222	1		T156	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T2	1		T28	14		T155	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T4	11		T24	11		T60	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T74	13		T223	11		T163	25
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T1	1		T4	2		T7	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	368	1			T91	11		T194	14		T35	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T9	12		T162	13		T165	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T224	2		T225	6		T158	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17564	1			T5	128		T10	20		T50	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T45	11		T150	7		T28	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T1	5		T6	12		T161	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1137	1			T8	26		T44	25		T24	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T46	14		T36	2		T233	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T11	11		T60	12		T231	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T28	7		T32	2		T109	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T24	8		T222	11		T241	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T230	10		T242	6		T243	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T150	2		T32	13		T161	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T6	14		T45	9		T46	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T59	13		T154	8		T231	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T6	7		T11	10		T244	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T222	14		T156	13		T230	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T28	17		T155	11		T233	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T4	7		T24	6		T155	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T74	12		T245	10		T246	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T1	5		T4	1		T7	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T91	11		T194	12		T234	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T38	2		T214	2		T247	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T225	6		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T214	4		T215	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T104	2		T216	9		T235	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T217	5		T236	1		T237	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T45	14		T161	8		T238	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	1		T6	1		T152	30
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1376	1			T3	3		T8	2		T11	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T46	18		T35	2		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	13		T43	1		T170	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T32	11		T220	14		T37	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T9	7		T24	12		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T124	1		T28	11		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T29	1		T152	9		T179	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T45	5		T46	25		T179	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T2	1		T150	1		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T6	2		T11	10		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T154	10		T222	1		T156	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T2	1		T28	14		T74	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T123	1		T218	1		T239	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T74	12		T223	11		T163	25
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T1	1		T4	13		T7	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	403	1			T91	11		T194	14		T35	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17551	1			T5	128		T10	20		T50	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T214	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T235	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T236	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T45	11		T161	11		T238	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T1	5		T6	12		T161	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1260	1			T8	26		T11	11		T44	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T46	14		T36	2		T233	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T154	11		T60	12		T231	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T32	2		T240	7		T39	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T24	8		T241	15		T248	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T28	7		T230	24		T109	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T222	11		T241	11		T109	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T45	9		T46	22		T238	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T150	2		T32	13		T59	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T6	21		T11	10		T150	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T154	8		T222	14		T156	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T28	17		T155	11		T233	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T230	16		T214	12		T168	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T74	12		T249	6		T51	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T1	5		T4	8		T7	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T91	11		T194	12		T234	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22552

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4022

1

T1

10

T4

8

T6

33

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26574

1

T1

12

T2

2

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22779

1

T1

6

T3

3

T4

3

auto[ADC_CTRL_FILTER_COND_OUT]

3795

1

T1

6

T2

2

T4

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20654

1

T1

6

T4

21

T5

128

auto[1]

5920

1

T1

6

T2

2

T3

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22513

1

T1

12

T2

2

T3

3

auto[1]

4061

1

T4

11

T7

1

T9

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T164	1		-	-		-	-
values[0]	116	1			T234	19		T167	15		T250	8
values[1]	450	1			T1	6		T59	12		T179	2
values[2]	611	1			T2	2		T4	18		T9	7
values[3]	849	1			T1	6		T6	15		T7	10
values[4]	770	1			T6	21		T9	12		T46	32
values[5]	719	1			T150	14		T91	22		T14	1
values[6]	619	1			T12	13		T46	24		T170	1
values[7]	651	1			T11	40		T124	1		T59	14
values[8]	677	1			T43	1		T150	8		T170	1
values[9]	3560	1			T3	3		T4	3		T8	28
minimum	17551	1			T5	128		T10	20		T50	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	699	1			T1	6		T2	1		T59	12
values[1]	817	1			T1	6		T2	1		T4	18
values[2]	691	1			T6	23		T7	10		T9	12
values[3]	688	1			T6	13		T151	1		T152	12
values[4]	709	1			T150	14		T91	22		T14	1
values[5]	569	1			T12	13		T170	1		T151	1
values[6]	2868	1			T3	3		T8	28		T11	40
values[7]	601	1			T150	8		T170	1		T24	17
values[8]	1003	1			T4	3		T46	23		T14	4
values[9]	334	1			T11	9		T194	26		T164	1
minimum	17595	1			T5	128		T10	20		T50	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22552

1

T1

2

T2

2

T3

3

auto[1]

4022

1

T1

10

T4

8

T6

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T59	10		T179	1		T238	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	6		T2	1		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T1	6		T9	1		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T2	1		T4	8		T28	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T7	9		T9	1		T45	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T6	23		T45	12		T46	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T6	13		T151	1		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T156	14		T251	13		T239	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T150	11		T91	12		T32	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T150	3		T14	1		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T12	1		T170	1		T155	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T151	1		T74	13		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1542	1			T3	3		T8	28		T11	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T11	11		T28	8		T241	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T170	1		T24	7		T35	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T150	8		T161	12		T162	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T4	2		T46	12		T28	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T14	4		T151	1		T74	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T11	4		T194	13		T165	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T164	1		T222	10		T230	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17426	1			T5	128		T10	20		T50	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T252	28		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T59	2		T238	14		T233	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T152	8		T234	10		T221	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T9	6		T24	10		T60	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	10		T28	13		T238	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T7	1		T9	11		T45	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T45	13		T46	17		T154	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T152	11		T253	11		T159	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T156	13		T239	9		T221	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T91	10		T32	13		T161	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T152	17		T227	5		T220	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T12	12		T155	15		T214	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T74	11		T233	11		T232	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1007	1			T11	8		T46	12		T32	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	9		T28	10		T223	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T24	10		T224	1		T225	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T161	7		T162	22		T155	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T4	1		T46	11		T28	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T154	9		T163	16		T232	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T11	5		T194	13		T163	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T230	11		T120	4		T254	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T74	1		T35	3		T49	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T252	15		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T164	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T250	1		T255	10		T93	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T234	9		T167	15		T256	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T59	10		T179	1		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T1	6		T179	1		T257	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T9	1		T123	1		T45	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T2	2		T4	8		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T1	6		T7	9		T45	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T6	15		T45	12		T28	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T6	13		T9	1		T24	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T6	8		T46	15		T154	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T150	11		T91	12		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T150	3		T14	1		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T12	1		T46	12		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T28	8		T151	1		T74	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T11	12		T124	1		T59	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T11	11		T223	1		T231	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T43	1		T170	1		T24	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T150	8		T161	12		T162	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1640	1			T3	3		T4	2		T8	28
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	417	1			T14	4		T151	1		T74	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17425	1			T5	128		T10	20		T50	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T250	7		T258	9		T259	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T234	10		T256	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T59	2		T233	12		T230	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T221	15		T51	17		T38	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T9	6		T45	4		T60	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T4	10		T152	8		T36	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	1		T45	2		T24	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T45	13		T28	13		T239	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	11		T24	11		T152	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T46	17		T154	5		T156	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T91	10		T161	2		T159	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T152	17		T227	5		T220	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T12	12		T46	12		T32	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T28	10		T74	11		T251	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T11	8		T59	9		T155	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T11	9		T223	10		T231	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T24	10		T228	2		T225	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T161	7		T162	10		T155	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1116	1			T4	1		T11	5		T46	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	387	1			T154	9		T162	12		T156	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T74	1		T35	3		T49	1