Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26574

1

T1

12

T2

2

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22958

1

T1

6

T2

1

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3616

1

T1

6

T2

1

T4

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20465

1

T1

12

T2

1

T4

21

auto[1]

6109

1

T2

1

T3

3

T6

28

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22513

1

T1

12

T2

2

T3

3

auto[1]

4061

1

T4

11

T7

1

T9

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	262	1			T91	22		T179	1		T154	17
values[0]	22	1			T170	1		T305	1		T211	19
values[1]	502	1			T6	8		T46	23		T227	6
values[2]	689	1			T4	18		T7	10		T11	20
values[3]	725	1			T12	13		T43	1		T14	4
values[4]	618	1			T6	13		T9	12		T11	9
values[5]	682	1			T2	1		T170	1		T59	14
values[6]	755	1			T2	1		T45	14		T46	32
values[7]	888	1			T6	15		T11	20		T123	1
values[8]	2828	1			T1	6		T3	3		T4	3
values[9]	1052	1			T1	6		T45	7		T124	1
minimum	17551	1			T5	128		T10	20		T50	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	566	1			T4	18		T45	25		T152	18
values[1]	715	1			T7	10		T11	20		T12	13
values[2]	707	1			T11	9		T43	1		T14	4
values[3]	648	1			T2	1		T6	13		T150	11
values[4]	513	1			T9	12		T59	14		T60	2
values[5]	960	1			T2	1		T45	14		T46	32
values[6]	2849	1			T3	3		T6	15		T8	28
values[7]	765	1			T1	6		T4	3		T9	7
values[8]	973	1			T1	6		T46	24		T150	3
values[9]	123	1			T232	7		T108	1		T224	3
minimum	17755	1			T5	128		T6	8		T10	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22552

1

T1

2

T2

2

T3

3

auto[1]

4022

1

T1

10

T4

8

T6

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T4	8		T45	12		T152	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T164	1		T240	8		T108	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T7	9		T151	1		T275	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T11	11		T12	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	4		T43	1		T14	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T28	18		T151	1		T74	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T2	1		T6	13		T24	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T150	11		T170	1		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T9	1		T59	5		T161	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T60	1		T220	1		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T45	10		T150	8		T74	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T2	1		T46	15		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1578	1			T3	3		T6	15		T8	28
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T179	1		T251	1		T166	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T45	5		T124	1		T24	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	6		T4	2		T9	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T1	6		T29	1		T179	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T46	12		T150	3		T91	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T232	1		T224	3		T192	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T108	1		T247	3		T314	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17515	1			T5	128		T10	20		T50	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T6	8		T170	1		T269	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T4	10		T45	13		T152	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T240	6		T253	11		T160	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T7	1		T231	12		T249	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T11	9		T12	12		T161	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T11	5		T28	12		T152	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T28	13		T74	11		T60	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T24	10		T163	16		T51	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T156	17		T238	14		T157	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T9	11		T59	9		T161	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T60	1		T220	13		T162	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T45	4		T229	2		T109	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T46	17		T152	11		T229	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	962	1			T11	8		T189	12		T266	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T251	11		T166	9		T239	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T45	2		T24	11		T194	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T4	1		T9	6		T59	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T146	17		T154	14		T162	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T46	12		T91	10		T24	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T232	6		T304	10		T313	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T247	9		T315	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T46	11		T74	1		T35	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T269	10		T300	4		T316	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T179	1		T154	12		T232	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T91	12		T234	9		T257	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T305	1		T211	10		T184	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T170	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T46	12		T227	1		T164	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T6	8		T164	1		T108	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T4	8		T7	9		T45	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	11		T151	1		T60	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T43	1		T14	4		T28	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	1		T151	1		T74	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	13		T9	1		T11	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T150	11		T28	18		T156	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T2	1		T59	5		T161	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T170	1		T60	1		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T45	10		T150	8		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T2	1		T46	15		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T6	15		T11	12		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T241	16		T251	1		T166	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1511	1			T3	3		T8	28		T44	27
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	6		T4	2		T9	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T1	6		T45	5		T124	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T46	12		T150	3		T14	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17425	1			T5	128		T10	20		T50	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T154	5		T232	6		T191	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T91	10		T234	10		T115	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T211	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T46	11		T227	5		T238	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T269	10		T253	11		T160	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T4	10		T7	1		T45	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	9		T161	7		T220	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T28	10		T152	8		T36	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	12		T74	11		T60	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T9	11		T11	5		T24	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T28	13		T156	17		T238	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T59	9		T161	2		T51	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T60	1		T162	12		T239	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T45	4		T229	2		T286	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T46	17		T152	11		T220	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T11	8		T109	11		T225	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T251	11		T166	9		T231	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	979	1			T189	12		T266	13		T153	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T4	1		T9	6		T59	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T45	2		T24	11		T146	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T46	12		T24	10		T32	23
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T74	1		T35	3		T49	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T4	11		T45	14		T152	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T164	1		T240	7		T108	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T7	2		T151	1		T275	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T11	10		T12	13		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	6		T43	1		T14	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T28	14		T151	1		T74	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T2	1		T6	1		T24	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T150	1		T170	1		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T9	12		T59	10		T161	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T60	2		T220	14		T162	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T45	5		T150	1		T74	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T2	1		T46	18		T152	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T3	3		T6	1		T8	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T179	1		T251	12		T166	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T45	3		T124	1		T24	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T1	1		T4	2		T9	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T1	1		T29	1		T179	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T46	13		T150	1		T91	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T232	7		T224	1		T192	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T108	1		T247	10		T314	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17619	1			T5	128		T10	20		T50	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T6	1		T170	1		T269	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T4	7		T45	11		T238	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T240	7		T253	10		T309	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T7	8		T249	6		T15	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T11	10		T161	11		T222	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T11	3		T28	19		T36	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T28	17		T74	12		T60	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T6	12		T24	14		T51	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T150	10		T156	12		T238	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T59	4		T161	10		T244	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T281	8		T34	17		T317	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T45	9		T150	7		T109	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T46	14		T241	15		T244	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T6	14		T8	26		T11	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T231	10		T54	9		T245	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T45	4		T24	8		T194	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	5		T4	1		T59	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T1	5		T146	14		T154	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T46	11		T150	2		T91	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T224	2		T192	10		T304	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T247	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T46	11		T222	14		T230	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T6	7		T306	9		T316	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T179	1		T154	6		T232	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T91	11		T234	11		T257	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T305	1		T211	10		T184	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T170	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T46	12		T227	6		T164	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T6	1		T164	1		T108	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T4	11		T7	2		T45	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T11	10		T151	1		T60	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T43	1		T14	4		T28	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T12	13		T151	1		T74	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	1		T9	12		T11	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T150	1		T28	14		T156	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T2	1		T59	10		T161	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T170	1		T60	2		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T45	5		T150	1		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T2	1		T46	18		T152	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T6	1		T11	9		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T241	1		T251	12		T166	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T3	3		T8	2		T44	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T1	1		T4	2		T9	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T1	1		T45	3		T124	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T46	13		T150	1		T14	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17551	1			T5	128		T10	20		T50	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T154	11		T224	2		T304	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T91	11		T234	8		T257	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T211	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T46	11		T222	14		T238	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T6	7		T253	10		T160	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T4	7		T7	8		T45	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T11	10		T161	11		T240	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T28	7		T36	2		T249	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T74	12		T60	12		T222	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T6	12		T11	3		T24	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T150	10		T28	17		T156	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T59	4		T161	10		T51	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T111	12		T41	3		T281	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T45	9		T150	7		T244	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T46	14		T38	2		T225	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T6	14		T11	11		T222	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T241	15		T244	10		T231	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1180	1			T8	26		T44	25		T26	27
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T1	5		T4	1		T59	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T1	5		T45	4		T24	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T46	11		T150	2		T24	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22552

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4022

1

T1

10

T4

8

T6

33