Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26574

1

T1

12

T2

2

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22933

1

T1

6

T2

2

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3641

1

T1

6

T4

21

T6

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20524

1

T1

6

T2

1

T4

3

auto[1]

6050

1

T1

6

T2

1

T3

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22513

1

T1

12

T2

2

T3

3

auto[1]

4061

1

T4

11

T7

1

T9

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	535	1			T5	2		T12	2		T47	1
values[0]	61	1			T6	8		T46	32		T264	11
values[1]	818	1			T12	13		T124	1		T150	8
values[2]	2874	1			T3	3		T8	28		T9	7
values[3]	601	1			T2	1		T4	18		T7	10
values[4]	663	1			T9	12		T11	20		T146	32
values[5]	755	1			T6	13		T45	14		T60	1
values[6]	696	1			T1	6		T2	1		T43	1
values[7]	674	1			T4	3		T46	23		T150	11
values[8]	653	1			T11	9		T150	3		T32	13
values[9]	1077	1			T1	6		T6	15		T11	20
minimum	17167	1			T5	126		T10	20		T50	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	751	1			T6	8		T9	7		T12	13
values[1]	2862	1			T3	3		T4	18		T8	28
values[2]	711	1			T2	1		T7	10		T151	1
values[3]	636	1			T9	12		T11	20		T45	14
values[4]	707	1			T1	6		T6	13		T161	19
values[5]	655	1			T2	1		T43	1		T45	25
values[6]	753	1			T4	3		T46	23		T24	20
values[7]	688	1			T11	9		T150	3		T32	13
values[8]	864	1			T1	6		T6	15		T45	7
values[9]	134	1			T11	20		T167	12		T17	4
minimum	17813	1			T5	128		T10	20		T50	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22552

1

T1

2

T2

2

T3

3

auto[1]

4022

1

T1

10

T4

8

T6

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T6	8		T9	1		T46	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T12	1		T150	8		T151	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1494	1			T3	3		T8	28		T44	27
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T4	8		T24	7		T234	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T2	1		T7	9		T154	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T151	1		T74	1		T155	25
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T9	1		T45	10		T146	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T11	12		T60	1		T222	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T161	12		T233	9		T109	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T1	6		T6	13		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T2	1		T43	1		T150	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T45	12		T170	1		T24	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T46	12		T24	9		T32	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T4	2		T28	18		T59	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T11	4		T150	3		T32	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T220	2		T156	14		T275	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T1	6		T6	15		T45	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T162	1		T165	1		T166	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T11	11		T17	4		T252	28
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T167	12		T318	1		T270	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17508	1			T5	128		T10	20		T50	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T29	1		T107	1		T279	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T9	6		T46	17		T220	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T12	12		T161	2		T162	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	921	1			T46	12		T28	10		T189	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T4	10		T24	10		T234	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T7	1		T154	9		T60	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T155	27		T230	11		T214	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T9	11		T45	4		T146	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T11	8		T163	7		T229	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T161	7		T233	11		T109	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T231	13		T268	9		T173	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T28	2		T230	25		T54	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T45	13		T24	10		T60	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T46	11		T24	11		T32	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T4	1		T28	13		T59	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T11	5		T32	10		T59	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T220	28		T156	13		T15	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T45	2		T91	10		T74	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T162	12		T166	9		T239	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T11	9		T252	15		T280	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T270	13		T316	5		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T74	1		T35	3		T49	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T279	8		T319	1		T169	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	435	1			T5	2		T12	2		T47	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T167	12		T320	1		T159	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T6	8		T46	15		T264	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T217	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T124	1		T220	1		T238	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T12	1		T150	8		T29	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1498	1			T3	3		T8	28		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T24	7		T162	1		T155	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T2	1		T7	9		T154	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T4	8		T151	1		T74	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T9	1		T146	15		T60	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	12		T222	10		T241	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T45	10		T161	12		T37	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T6	13		T60	1		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	1		T43	1		T14	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T1	6		T45	12		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T46	12		T150	11		T24	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T4	2		T28	18		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T11	4		T150	3		T32	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T59	10		T152	1		T220	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T1	6		T6	15		T11	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T220	1		T162	1		T165	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17041	1			T5	126		T10	20		T50	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T156	17		T321	4		T322	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T304	11		T211	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T46	17		T264	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T217	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T220	13		T238	14		T223	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T12	12		T161	2		T229	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	906	1			T9	6		T46	12		T28	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T24	10		T162	10		T155	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	1		T154	9		T227	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T4	10		T155	15		T230	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T9	11		T146	17		T60	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T11	8		T163	7		T262	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T45	4		T161	7		T233	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T231	13		T229	2		T268	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T28	2		T230	25		T54	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T45	13		T24	10		T60	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T46	11		T24	11		T32	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T4	1		T28	13		T152	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T11	5		T32	10		T59	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T59	2		T152	8		T220	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T11	9		T45	2		T91	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T220	13		T162	12		T166	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T74	1		T35	3		T49	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T6	1		T9	7		T46	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T12	13		T150	1		T151	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1259	1			T3	3		T8	2		T44	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T4	11		T24	11		T234	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T2	1		T7	2		T154	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T151	1		T74	1		T155	29
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T9	12		T45	5		T146	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T11	9		T60	1		T222	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T161	8		T233	12		T109	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	1		T6	1		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T2	1		T43	1		T150	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T45	14		T170	1		T24	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T46	12		T24	12		T32	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T4	2		T28	14		T59	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T11	6		T150	1		T32	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T220	30		T156	14		T275	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T1	1		T6	1		T45	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T162	13		T165	1		T166	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T11	10		T17	4		T252	23
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T167	1		T318	1		T270	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17641	1			T5	128		T10	20		T50	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T29	1		T107	1		T279	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T6	7		T46	14		T238	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T150	7		T161	10		T241	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1156	1			T8	26		T44	25		T46	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T4	7		T24	6		T234	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	8		T154	8		T60	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T155	23		T222	14		T241	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T45	9		T146	14		T251	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T11	11		T222	9		T157	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T161	11		T233	8		T109	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T1	5		T6	12		T231	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T150	10		T28	12		T230	30
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T45	11		T24	14		T233	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T46	11		T24	8		T32	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T4	1		T28	17		T59	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T11	3		T150	2		T32	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T156	13		T15	1		T214	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	5		T6	14		T45	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T240	7		T38	2		T260	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T11	10		T252	20		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T167	11		T270	12		T316	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T323	10		T192	6		T291	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T279	9		T169	3		T207	17

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	442	1			T5	2		T12	2		T47	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T167	1		T320	1		T159	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T6	1		T46	18		T264	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T217	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T124	1		T220	14		T238	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	13		T150	1		T29	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T3	3		T8	2		T9	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T24	11		T162	11		T155	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T2	1		T7	2		T154	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T4	11		T151	1		T74	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T9	12		T146	18		T60	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	9		T222	1		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T45	5		T161	8		T37	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T6	1		T60	1		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T2	1		T43	1		T14	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T1	1		T45	14		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T46	12		T150	1		T24	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T4	2		T28	14		T152	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T11	6		T150	1		T32	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T59	3		T152	9		T220	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T1	1		T6	1		T11	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T220	14		T162	13		T165	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17167	1			T5	126		T10	20		T50	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T156	12		T308	6		T322	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T167	11		T304	4		T211	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T6	7		T46	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T238	11		T231	10		T323	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T150	7		T161	10		T241	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1167	1			T8	26		T44	25		T46	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T24	6		T155	11		T234	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T7	8		T154	8		T36	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T4	7		T155	12		T222	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T146	14		T60	12		T251	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T11	11		T222	9		T241	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T45	9		T161	11		T233	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T6	12		T157	5		T231	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T28	12		T230	30		T224	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	5		T45	11		T24	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T46	11		T150	10		T24	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T4	1		T28	17		T194	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T11	3		T150	2		T32	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T59	9		T156	13		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T1	5		T6	14		T11	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T240	7		T38	2		T214	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22552

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4022

1

T1

10

T4

8

T6

33