Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26574

1

T1

12

T2

2

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23112

1

T1

6

T2

1

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3462

1

T1

6

T2

1

T4

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20883

1

T1

12

T2

1

T4

3

auto[1]

5691

1

T2

1

T3

3

T4

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22513

1

T1

12

T2

2

T3

3

auto[1]

4061

1

T4

11

T7

1

T9

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	333	1			T9	7		T24	20		T152	12
values[0]	66	1			T170	1		T91	22		T284	1
values[1]	683	1			T2	1		T6	13		T60	3
values[2]	619	1			T156	30		T238	26		T275	1
values[3]	633	1			T9	12		T123	1		T150	11
values[4]	843	1			T6	8		T7	10		T45	14
values[5]	2909	1			T3	3		T6	15		T8	28
values[6]	560	1			T1	6		T2	1		T11	20
values[7]	670	1			T4	21		T12	13		T46	24
values[8]	786	1			T1	6		T11	9		T43	1
values[9]	921	1			T11	20		T45	7		T150	8
minimum	17551	1			T5	128		T10	20		T50	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	661	1			T6	13		T91	22		T60	3
values[1]	612	1			T150	11		T28	31		T151	1
values[2]	695	1			T9	12		T123	1		T28	18
values[3]	2864	1			T3	3		T6	23		T7	10
values[4]	793	1			T2	1		T150	3		T29	1
values[5]	637	1			T1	6		T4	18		T11	20
values[6]	677	1			T4	3		T12	13		T43	1
values[7]	731	1			T1	6		T11	29		T28	15
values[8]	954	1			T9	7		T45	7		T150	8
values[9]	164	1			T24	20		T74	24		T227	6
minimum	17786	1			T2	1		T5	128		T10	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22552

1

T1

2

T2

2

T3

3

auto[1]

4022

1

T1

10

T4

8

T6

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T91	12		T60	1		T164	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	13		T60	1		T275	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T238	15		T244	23		T230	28
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T150	11		T28	18		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T220	1		T165	1		T251	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T9	1		T123	1		T28	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1515	1			T3	3		T8	28		T44	27
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T6	23		T7	9		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T2	1		T150	3		T29	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T151	1		T59	5		T257	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T4	8		T46	12		T14	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T1	6		T11	12		T24	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T43	1		T46	12		T35	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T4	2		T12	1		T45	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T1	6		T11	4		T28	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T11	11		T219	1		T240	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T9	1		T150	8		T14	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T45	5		T179	1		T163	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T74	13		T231	12		T224	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T24	9		T227	1		T235	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17510	1			T5	128		T10	20		T50	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T2	1		T220	1		T40	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T91	10		T60	1		T156	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T253	11		T287	21		T159	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T238	17		T230	22		T109	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T28	13		T161	13		T51	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T220	13		T251	11		T225	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T9	11		T28	10		T32	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	977	1			T45	4		T46	17		T189	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T7	1		T152	8		T161	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T146	17		T154	5		T220	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T59	9		T233	11		T224	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T4	10		T46	11		T24	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	8		T24	10		T59	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T46	12		T36	9		T286	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T4	1		T12	12		T45	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T11	5		T28	2		T60	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T11	9		T240	6		T38	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T9	6		T152	11		T154	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T45	2		T163	16		T111	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T74	11		T231	13		T324	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T24	11		T227	5		T235	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T74	1		T35	4		T49	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T220	13		T40	4		T294	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T9	1		T152	1		T74	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T24	9		T227	1		T108	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T170	1		T91	12		T284	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T182	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T60	1		T35	1		T164	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	1		T6	13		T60	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T156	13		T238	12		T244	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T275	1		T51	5		T167	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T220	1		T238	3		T244	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T9	1		T123	1		T150	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T45	10		T46	15		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T6	8		T7	9		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1518	1			T3	3		T8	28		T44	27
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T6	15		T59	5		T74	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T2	1		T46	12		T14	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T1	6		T11	12		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T4	8		T46	12		T24	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T4	2		T12	1		T32	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T1	6		T11	4		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T45	12		T219	1		T239	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T150	8		T14	1		T179	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T11	11		T45	5		T179	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17425	1			T5	128		T10	20		T50	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T9	6		T152	11		T74	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T24	11		T227	5		T173	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T91	10		T319	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T60	1		T35	1		T221	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T220	13		T40	4		T253	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T156	17		T238	14		T230	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T51	17		T303	1		T325	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T220	13		T238	3		T230	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T9	11		T28	23		T32	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T45	4		T46	17		T152	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	1		T152	8		T161	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1002	1			T189	12		T266	13		T153	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T59	9		T233	11		T229	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T46	11		T161	2		T166	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T11	8		T24	10		T59	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T4	10		T46	12		T24	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T4	1		T12	12		T32	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	5		T28	2		T60	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T45	13		T239	12		T233	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T154	9		T155	15		T156	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	9		T45	2		T163	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T74	1		T35	3		T49	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T91	11		T60	2		T164	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T6	1		T60	1		T275	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T238	19		T244	2		T230	24
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T150	1		T28	14		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T220	14		T165	1		T251	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T9	12		T123	1		T28	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1311	1			T3	3		T8	2		T44	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T6	2		T7	2		T152	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T2	1		T150	1		T29	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T151	1		T59	10		T257	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T4	11		T46	12		T14	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T1	1		T11	9		T24	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T43	1		T46	13		T35	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T4	2		T12	13		T45	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	1		T11	6		T28	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	10		T219	1		T240	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T9	7		T150	1		T14	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T45	3		T179	1		T163	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T74	12		T231	14		T224	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T24	12		T227	6		T235	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17639	1			T5	128		T10	20		T50	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T2	1		T220	14		T40	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T91	11		T156	12		T214	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T6	12		T253	10		T287	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T238	13		T244	21		T230	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T150	10		T28	17		T161	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T225	6		T261	7		T262	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T28	7		T32	2		T241	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1181	1			T8	26		T44	25		T45	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	21		T7	8		T161	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T150	2		T146	14		T154	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T59	4		T257	11		T233	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T4	7		T46	11		T24	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	5		T11	11		T24	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T46	11		T36	2		T222	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T4	1		T45	11		T32	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T1	5		T11	3		T28	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	10		T240	7		T38	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T150	7		T154	8		T156	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T45	4		T111	12		T214	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T74	12		T231	11		T224	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T24	8		T235	9		T326	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T246	10		T277	8		T242	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T246	8		T294	10		T256	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T9	7		T152	12		T74	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T24	12		T227	6		T108	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T170	1		T91	11		T284	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T182	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T60	2		T35	2		T164	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T2	1		T6	1		T60	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T156	18		T238	15		T244	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T275	1		T51	18		T167	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T220	14		T238	4		T244	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T9	12		T123	1		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T45	5		T46	18		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T6	1		T7	2		T152	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T3	3		T8	2		T44	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T6	1		T59	10		T74	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T2	1		T46	12		T14	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T1	1		T11	9		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T4	11		T46	13		T24	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T4	2		T12	13		T32	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T1	1		T11	6		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T45	14		T219	1		T239	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T150	1		T14	1		T179	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T11	10		T45	3		T179	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17551	1			T5	128		T10	20		T50	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T74	12		T224	2		T167	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T24	8		T173	16		T306	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T91	11		T319	18		T327	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T182	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T214	12		T248	9		T246	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T6	12		T253	10		T287	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T156	12		T238	11		T244	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T51	4		T167	11		T303	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T238	2		T244	11		T230	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T150	10		T28	24		T32	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T45	9		T46	14		T234	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T6	7		T7	8		T161	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1168	1			T8	26		T44	25		T150	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	14		T59	4		T233	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T46	11		T161	10		T54	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T1	5		T11	11		T24	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T4	7		T46	11		T24	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T4	1		T32	13		T194	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T1	5		T11	3		T28	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T45	11		T240	7		T41	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T150	7		T154	8		T155	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	10		T45	4		T111	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22552

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4022

1

T1

10

T4

8

T6

33