Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26574

1

T1

12

T2

2

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23051

1

T1

6

T2

1

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3523

1

T1

6

T2

1

T6

36

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20899

1

T1

6

T4

21

T5

128

auto[1]

5675

1

T1

6

T2

2

T3

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22513

1

T1

12

T2

2

T3

3

auto[1]

4061

1

T4

11

T7

1

T9

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	208	1			T4	3		T7	10		T11	9
values[0]	66	1			T238	26		T104	2		T216	9
values[1]	594	1			T1	6		T6	13		T45	25
values[2]	2932	1			T3	3		T8	28		T12	13
values[3]	458	1			T11	20		T43	1		T14	4
values[4]	583	1			T9	7		T124	1		T24	20
values[5]	770	1			T6	15		T45	14		T46	47
values[6]	681	1			T2	1		T11	20		T150	14
values[7]	792	1			T2	1		T6	8		T123	1
values[8]	879	1			T74	25		T219	1		T155	24
values[9]	1060	1			T1	6		T4	18		T9	12
minimum	17551	1			T5	128		T10	20		T50	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	677	1			T1	6		T6	13		T150	8
values[1]	2830	1			T3	3		T8	28		T12	13
values[2]	484	1			T11	20		T43	1		T14	4
values[3]	502	1			T9	7		T124	1		T24	20
values[4]	974	1			T6	15		T45	14		T46	47
values[5]	523	1			T2	1		T6	8		T11	20
values[6]	910	1			T2	1		T123	1		T28	31
values[7]	743	1			T4	18		T74	25		T219	1
values[8]	1074	1			T1	6		T4	3		T7	10
values[9]	85	1			T9	12		T162	13		T165	1
minimum	17772	1			T5	128		T10	20		T50	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22552

1

T1

2

T2

2

T3

3

auto[1]

4022

1

T1

10

T4

8

T6

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T150	8		T28	13		T146	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T1	6		T6	13		T152	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1462	1			T3	3		T8	28		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T46	15		T35	1		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T11	12		T43	1		T14	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T28	8		T32	3		T220	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T9	1		T24	9		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T124	1		T151	1		T221	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T150	3		T170	1		T32	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	360	1			T6	15		T45	10		T46	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	1		T151	1		T59	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T6	8		T11	11		T220	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T123	1		T222	15		T156	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	1		T28	18		T155	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T4	8		T219	1		T218	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T74	14		T223	1		T163	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T1	6		T4	2		T7	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T91	12		T194	13		T35	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T9	1		T162	1		T165	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T158	1		T295	1		T328	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17482	1			T5	128		T10	20		T50	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T161	11		T260	3		T160	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T28	2		T146	17		T233	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T152	28		T226	1		T119	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	980	1			T12	12		T24	10		T189	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T46	17		T35	1		T36	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T11	8		T60	10		T227	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T28	10		T32	10		T220	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T9	6		T24	11		T228	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T221	2		T229	7		T230	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T32	13		T152	8		T162	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T45	4		T46	23		T60	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T59	11		T154	9		T161	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T11	9		T220	13		T166	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T156	13		T232	10		T214	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T28	13		T155	12		T233	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T4	10		T251	11		T239	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T74	11		T223	10		T163	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T4	1		T7	1		T11	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T91	10		T194	13		T234	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T9	11		T162	12		T214	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T158	9		T329	7		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T45	13		T74	1		T161	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T161	2		T160	10		T330	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T4	2		T7	9		T11	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T168	5		T263	6		T304	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T238	12		T104	2		T216	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T217	1		T236	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T45	12		T161	12		T51	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	6		T6	13		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1554	1			T3	3		T8	28		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T46	15		T152	1		T35	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	12		T43	1		T14	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T28	8		T32	3		T220	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T9	1		T24	9		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T124	1		T151	1		T221	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T29	1		T152	1		T179	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T6	15		T45	10		T46	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T2	1		T150	3		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T11	11		T150	11		T60	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T123	1		T154	9		T222	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	1		T6	8		T28	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T219	1		T218	1		T239	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T74	14		T155	12		T223	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T1	6		T4	8		T9	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T91	12		T194	13		T35	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17425	1			T5	128		T10	20		T50	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T4	1		T7	1		T11	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T168	6		T263	7		T304	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T238	14		T216	8		T235	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T217	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T45	13		T161	7		T51	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T152	17		T161	2		T226	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1015	1			T12	12		T24	10		T28	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T46	17		T152	11		T35	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T11	8		T154	5		T60	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T28	10		T32	10		T220	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	6		T24	11		T228	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T221	2		T229	2		T230	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T152	8		T162	10		T109	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T45	4		T46	23		T238	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T32	13		T59	11		T161	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	9		T60	1		T220	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T154	9		T156	13		T231	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T28	13		T233	11		T249	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T239	21		T232	6		T230	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T74	11		T155	12		T223	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T4	10		T9	11		T45	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T91	10		T194	13		T234	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T74	1		T35	3		T49	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T150	1		T28	3		T146	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T1	1		T6	1		T152	30
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1305	1			T3	3		T8	2		T12	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T46	18		T35	2		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T11	9		T43	1		T14	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T28	11		T32	11		T220	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T9	7		T24	12		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T124	1		T151	1		T221	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T150	1		T170	1		T32	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T6	1		T45	5		T46	25
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T2	1		T151	1		T59	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T6	1		T11	10		T220	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T123	1		T222	1		T156	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T2	1		T28	14		T155	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T4	11		T219	1		T218	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T74	13		T223	11		T163	25
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	1		T4	2		T7	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	384	1			T91	11		T194	14		T35	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T9	12		T162	13		T165	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T158	10		T295	1		T328	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17616	1			T5	128		T10	20		T50	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T161	3		T260	1		T160	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T150	7		T28	12		T146	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T1	5		T6	12		T257	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1137	1			T8	26		T44	25		T24	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T46	14		T36	2		T233	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T11	11		T60	12		T231	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T28	7		T32	2		T109	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T24	8		T222	11		T241	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T230	10		T242	6		T243	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T150	2		T32	13		T241	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T6	14		T45	9		T46	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T59	13		T154	8		T161	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T6	7		T11	10		T244	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T222	14		T156	13		T214	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T28	17		T155	11		T233	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T4	7		T230	16		T109	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T74	12		T245	10		T246	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	5		T4	1		T7	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T91	11		T194	12		T234	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T214	2		T247	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T45	11		T161	11		T238	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T161	10		T260	2		T160	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T4	2		T7	2		T11	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T168	7		T263	8		T304	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T238	15		T104	2		T216	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T217	5		T236	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T45	14		T161	8		T51	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	1		T6	1		T152	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1350	1			T3	3		T8	2		T12	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T46	18		T152	12		T35	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T11	9		T43	1		T14	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T28	11		T32	11		T220	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T9	7		T24	12		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T124	1		T151	1		T221	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T29	1		T152	9		T179	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T6	1		T45	5		T46	25
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T2	1		T150	1		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T11	10		T150	1		T60	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T123	1		T154	10		T222	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T2	1		T6	1		T28	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T219	1		T218	1		T239	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T74	13		T155	13		T223	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T1	1		T4	11		T9	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T91	11		T194	14		T35	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17551	1			T5	128		T10	20		T50	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T4	1		T7	8		T11	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T168	4		T263	5		T304	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T238	11		T235	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T236	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T45	11		T161	11		T323	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T1	5		T6	12		T161	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1219	1			T8	26		T44	25		T150	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T46	14		T36	2		T233	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T11	11		T154	11		T60	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T28	7		T32	2		T240	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T24	8		T241	15		T246	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T230	10		T109	15		T167	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T222	11		T241	11		T109	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T6	14		T45	9		T46	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T150	2		T32	13		T59	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T11	10		T150	10		T244	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T154	8		T222	14		T156	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T6	7		T28	17		T233	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T230	16		T214	12		T168	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T74	12		T155	11		T51	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	5		T4	7		T45	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T91	11		T194	12		T234	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22552

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4022

1

T1

10

T4

8

T6

33