Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26574

1

T1

12

T2

2

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20877

1

T1

6

T2

1

T4

3

auto[ADC_CTRL_FILTER_COND_OUT]

5697

1

T1

6

T2

1

T3

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20614

1

T1

6

T2

1

T4

18

auto[1]

5960

1

T1

6

T2

1

T3

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22513

1

T1

12

T2

2

T3

3

auto[1]

4061

1

T4

11

T7

1

T9

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	422	1			T124	1		T234	19		T222	15
values[0]	56	1			T6	15		T40	11		T290	14
values[1]	609	1			T4	18		T7	10		T9	12
values[2]	553	1			T11	20		T45	14		T150	14
values[3]	726	1			T6	8		T11	9		T46	24
values[4]	662	1			T4	3		T6	13		T11	20
values[5]	716	1			T2	1		T45	25		T24	25
values[6]	748	1			T9	7		T24	20		T28	15
values[7]	836	1			T1	12		T12	13		T170	1
values[8]	722	1			T123	1		T45	7		T46	23
values[9]	2973	1			T2	1		T3	3		T8	28
minimum	17551	1			T5	128		T10	20		T50	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	470	1			T4	18		T7	10		T9	12
values[1]	2858	1			T3	3		T8	28		T11	29
values[2]	648	1			T6	8		T11	20		T59	12
values[3]	649	1			T2	1		T6	13		T46	32
values[4]	666	1			T4	3		T45	25		T29	1
values[5]	851	1			T9	7		T24	20		T28	15
values[6]	876	1			T1	12		T12	13		T46	23
values[7]	571	1			T2	1		T123	1		T45	7
values[8]	964	1			T43	1		T124	1		T151	1
values[9]	184	1			T234	19		T229	8		T51	22
minimum	17837	1			T5	128		T6	15		T10	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22552

1

T1

2

T2

2

T3

3

auto[1]

4022

1

T1

10

T4

8

T6

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T7	9		T9	1		T150	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T4	8		T150	8		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T45	10		T91	12		T194	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1507	1			T3	3		T8	28		T11	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T6	8		T11	11		T220	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T59	10		T38	4		T54	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T2	1		T6	13		T179	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T46	15		T24	15		T28	26
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T4	2		T32	3		T155	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T45	12		T29	1		T74	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T24	9		T59	5		T227	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T9	1		T28	13		T146	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T1	6		T12	1		T46	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T1	6		T152	1		T35	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T123	1		T14	5		T24	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T2	1		T45	5		T219	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T124	1		T60	14		T155	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T43	1		T151	1		T108	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T234	9		T51	5		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T229	1		T284	1		T215	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17482	1			T5	128		T10	20		T50	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T6	15		T223	1		T163	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T7	1		T9	11		T221	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T4	10		T152	11		T240	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T45	4		T91	10		T194	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1012	1			T11	13		T46	12		T32	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T11	9		T220	15		T233	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T59	2		T38	2		T54	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T154	9		T60	1		T161	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T46	17		T24	10		T28	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T4	1		T32	10		T155	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T45	13		T161	7		T220	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T24	11		T59	9		T227	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T9	6		T28	2		T146	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T12	12		T46	11		T224	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T152	17		T35	1		T238	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T24	10		T249	2		T160	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T45	2		T162	12		T158	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T60	10		T155	12		T238	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T268	10		T287	10		T226	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T234	10		T51	17		T226	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T229	7		T215	2		T183	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T74	12		T35	3		T49	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T223	10		T163	7		T40	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T124	1		T234	9		T222	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T229	1		T108	1		T226	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T290	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T6	15		T40	6		T291	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	9		T9	1		T74	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T4	8		T150	8		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T45	10		T150	3		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T11	12		T150	11		T251	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T6	8		T194	13		T220	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T11	4		T46	12		T32	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T4	2		T6	13		T11	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T46	15		T152	1		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T2	1		T32	3		T155	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T45	12		T24	15		T28	26
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T24	9		T59	5		T227	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T9	1		T28	13		T146	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T1	6		T12	1		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T1	6		T257	12		T238	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T123	1		T46	12		T14	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T45	5		T152	1		T35	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T151	1		T60	14		T155	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1484	1			T2	1		T3	3		T8	28
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17425	1			T5	128		T10	20		T50	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T234	10		T321	4		T295	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T229	7		T226	16		T42	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T290	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T40	5		T291	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T7	1		T9	11		T74	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T4	10		T152	11		T223	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T45	4		T91	10		T220	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T11	8		T251	11		T239	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T194	13		T220	15		T36	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T11	5		T46	12		T32	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T4	1		T11	9		T154	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T46	17		T152	8		T230	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T32	10		T155	15		T166	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T45	13		T24	10		T28	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T24	11		T59	9		T227	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T9	6		T28	2		T146	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T12	12		T156	13		T240	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T238	14		T239	12		T233	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T46	11		T24	10		T224	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T45	2		T152	17		T35	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T60	10		T155	12		T238	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	934	1			T189	12		T266	13		T153	22
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T74	1		T35	3		T49	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T7	2		T9	12		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T4	11		T150	1		T152	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T45	5		T91	11		T194	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1335	1			T3	3		T8	2		T11	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T6	1		T11	10		T220	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T59	3		T38	4		T54	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T2	1		T6	1		T179	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T46	18		T24	11		T28	25
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T4	2		T32	11		T155	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T45	14		T29	1		T74	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T24	12		T59	10		T227	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T9	7		T28	3		T146	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T1	1		T12	13		T46	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T1	1		T152	18		T35	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T123	1		T14	5		T24	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T2	1		T45	3		T219	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T124	1		T60	12		T155	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T43	1		T151	1		T108	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T234	11		T51	18		T226	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T229	8		T284	1		T215	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17630	1			T5	128		T10	20		T50	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T6	1		T223	11		T163	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T7	8		T150	2		T39	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T4	7		T150	7		T240	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T45	9		T91	11		T194	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1184	1			T8	26		T11	14		T44	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T6	7		T11	10		T233	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T59	9		T38	2		T54	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T6	12		T154	8		T161	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T46	14		T24	14		T28	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T4	1		T32	2		T155	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T45	11		T161	11		T156	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T24	8		T59	4		T222	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T28	12		T146	14		T251	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T1	5		T46	11		T157	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	5		T257	11		T238	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T24	6		T249	6		T160	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T45	4		T245	10		T274	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T60	12		T155	11		T222	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T268	10		T287	2		T226	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T234	8		T51	4		T255	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T292	7		T176	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T74	12		T214	2		T254	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T6	14		T40	4		T160	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T124	1		T234	11		T222	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T229	8		T108	1		T226	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T290	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T6	1		T40	7		T291	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T7	2		T9	12		T74	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T4	11		T150	1		T152	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T45	5		T150	1		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T11	9		T150	1		T251	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T6	1		T194	14		T220	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T11	6		T46	13		T32	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T4	2		T6	1		T11	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T46	18		T152	9		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T2	1		T32	11		T155	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T45	14		T24	11		T28	25
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T24	12		T59	10		T227	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T9	7		T28	3		T146	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T1	1		T12	13		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T1	1		T257	1		T238	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T123	1		T46	12		T14	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T45	3		T152	18		T35	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T151	1		T60	12		T155	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1269	1			T2	1		T3	3		T8	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17551	1			T5	128		T10	20		T50	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T234	8		T222	14		T276	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T226	16		T331	17		T42	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T6	14		T40	4		T291	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T7	8		T74	12		T214	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T4	7		T150	7		T240	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T45	9		T150	2		T91	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T11	11		T150	10		T230	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T6	7		T194	12		T36	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T11	3		T46	11		T32	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T4	1		T6	12		T11	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T46	14		T222	11		T230	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T32	2		T155	12		T224	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T45	11		T24	14		T28	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T24	8		T59	4		T253	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T28	12		T146	14		T156	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T1	5		T222	9		T156	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T1	5		T257	11		T238	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T46	11		T24	6		T293	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T45	4		T244	11		T245	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T60	12		T155	11		T241	26
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1149	1			T8	26		T44	25		T26	27

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22552

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4022

1

T1

10

T4

8

T6

33