Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26574

1

T1

12

T2

2

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22971

1

T1

6

T2

1

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3603

1

T1

6

T2

1

T4

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20916

1

T1

12

T2

1

T4

3

auto[1]

5658

1

T2

1

T3

3

T4

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22513

1

T1

12

T2

2

T3

3

auto[1]

4061

1

T4

11

T7

1

T9

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	47	1			T275	1		T109	16		T332	1
values[0]	122	1			T2	1		T91	22		T220	14
values[1]	637	1			T6	13		T170	1		T60	3
values[2]	580	1			T150	11		T156	30		T238	26
values[3]	639	1			T9	12		T123	1		T28	49
values[4]	871	1			T6	8		T7	10		T45	14
values[5]	2908	1			T3	3		T6	15		T8	28
values[6]	646	1			T1	6		T2	1		T11	20
values[7]	531	1			T4	21		T124	1		T24	17
values[8]	776	1			T1	6		T11	9		T12	13
values[9]	1266	1			T9	7		T11	20		T45	7
minimum	17551	1			T5	128		T10	20		T50	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	847	1			T2	1		T6	13		T170	1
values[1]	613	1			T28	31		T151	1		T161	25
values[2]	734	1			T9	12		T123	1		T150	11
values[3]	2849	1			T3	3		T6	23		T7	10
values[4]	781	1			T2	1		T150	3		T14	4
values[5]	655	1			T1	6		T4	18		T11	20
values[6]	671	1			T4	3		T12	13		T43	1
values[7]	735	1			T1	6		T11	29		T45	7
values[8]	797	1			T150	8		T14	1		T152	12
values[9]	310	1			T9	7		T24	20		T74	24
minimum	17582	1			T5	128		T10	20		T50	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22552

1

T1

2

T2

2

T3

3

auto[1]

4022

1

T1

10

T4

8

T6

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T170	1		T91	12		T60	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T2	1		T6	13		T60	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T238	15		T244	12		T230	28
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T28	18		T151	1		T161	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T220	1		T165	1		T251	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T9	1		T123	1		T150	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1556	1			T3	3		T6	8		T7	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T6	15		T152	1		T74	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T2	1		T150	3		T14	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T151	1		T59	5		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T4	8		T46	12		T161	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T1	6		T11	12		T124	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T46	12		T35	2		T222	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T4	2		T12	1		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T1	6		T11	4		T28	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T11	11		T45	5		T219	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T150	8		T14	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T154	9		T163	1		T108	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T9	1		T74	13		T231	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T24	9		T227	1		T239	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17438	1			T5	128		T10	20		T50	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T246	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T91	10		T60	1		T35	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T220	13		T156	17		T40	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T238	17		T230	22		T109	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T28	13		T161	13		T51	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T220	13		T251	11		T214	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T9	11		T28	10		T32	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	981	1			T7	1		T45	4		T46	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T152	8		T161	7		T229	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T146	17		T154	5		T220	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T59	9		T157	10		T233	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T4	10		T46	11		T161	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	8		T24	20		T59	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T46	12		T249	2		T286	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T4	1		T12	12		T45	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T11	5		T28	2		T60	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T11	9		T45	2		T240	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T152	11		T156	13		T228	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T154	9		T163	16		T111	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T9	6		T74	11		T231	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T24	11		T227	5		T239	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T74	1		T35	3		T49	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T275	1		T109	9		T332	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T333	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T91	12		T164	1		T287	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T2	1		T220	1		T275	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T170	1		T60	1		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T6	13		T60	1		T40	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T238	12		T230	17		T109	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T150	11		T156	13		T51	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T220	1		T238	3		T244	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T9	1		T123	1		T28	26
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T6	8		T7	9		T45	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T32	3		T152	1		T161	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1525	1			T3	3		T8	28		T44	27
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T6	15		T59	5		T74	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T2	1		T46	12		T14	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	6		T11	12		T24	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T4	8		T222	12		T241	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T4	2		T124	1		T24	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T1	6		T11	4		T46	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	1		T43	1		T45	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	383	1			T9	1		T150	8		T14	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T11	11		T45	5		T24	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17425	1			T5	128		T10	20		T50	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T109	7		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T333	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T91	10		T287	10		T319	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T220	13		T256	6		T175	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T60	1		T35	1		T221	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T40	4		T253	11		T287	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T238	14		T230	11		T109	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T156	17		T51	17		T54	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T220	13		T238	3		T230	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T9	11		T28	23		T161	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	1		T45	4		T46	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T32	10		T152	8		T161	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1005	1			T189	12		T266	13		T153	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T59	9		T233	11		T229	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T46	11		T161	2		T155	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T11	8		T24	10		T59	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T4	10		T249	2		T286	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T4	1		T24	10		T32	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T11	5		T46	12		T60	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	12		T45	13		T36	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T9	6		T28	2		T152	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T11	9		T45	2		T24	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T74	1		T35	3		T49	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T170	1		T91	11		T60	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T2	1		T6	1		T60	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T238	19		T244	1		T230	24
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T28	14		T151	1		T161	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T220	14		T165	1		T251	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T9	12		T123	1		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1329	1			T3	3		T6	1		T7	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T6	1		T152	9		T74	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T2	1		T150	1		T14	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T151	1		T59	10		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T4	11		T46	12		T161	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T1	1		T11	9		T124	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T46	13		T35	2		T222	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T4	2		T12	13		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T1	1		T11	6		T28	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T11	10		T45	3		T219	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T150	1		T14	1		T152	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T154	10		T163	17		T108	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T9	7		T74	12		T231	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T24	12		T227	6		T239	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17561	1			T5	128		T10	20		T50	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T246	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T91	11		T287	2		T246	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T6	12		T156	12		T253	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T238	13		T244	11		T230	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T28	17		T161	11		T244	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T214	2		T225	6		T261	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T150	10		T28	7		T32	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1208	1			T6	7		T7	8		T8	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T6	14		T161	11		T241	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T150	2		T146	14		T154	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T59	4		T257	11		T233	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T4	7		T46	11		T161	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	5		T11	11		T24	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T46	11		T222	11		T249	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T4	1		T45	11		T32	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T1	5		T11	3		T28	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T11	10		T45	4		T240	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T150	7		T156	13		T109	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T154	8		T111	12		T214	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T74	12		T231	11		T224	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T24	8		T231	10		T235	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T214	12		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T246	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T275	1		T109	8		T332	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T333	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T91	11		T164	1		T287	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T2	1		T220	14		T275	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T170	1		T60	2		T35	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T6	1		T60	1		T40	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T238	15		T230	12		T109	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T150	1		T156	18		T51	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T220	14		T238	4		T244	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T9	12		T123	1		T28	25
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T6	1		T7	2		T45	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T32	11		T152	9		T161	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1356	1			T3	3		T8	2		T44	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	1		T59	10		T74	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	1		T46	12		T14	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T1	1		T11	9		T24	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T4	11		T222	1		T241	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T4	2		T124	1		T24	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T1	1		T11	6		T46	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T12	13		T43	1		T45	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	409	1			T9	7		T150	1		T14	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T11	10		T45	3		T24	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17551	1			T5	128		T10	20		T50	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T109	8		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T333	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T91	11		T287	2		T319	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T256	9		T175	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T214	12		T248	9		T246	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T6	12		T253	10		T287	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T238	11		T230	16		T109	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T150	10		T156	12		T51	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T238	2		T244	11		T230	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T28	24		T161	11		T241	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T6	7		T7	8		T45	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T32	2		T161	11		T230	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1174	1			T8	26		T44	25		T150	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	14		T59	4		T233	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T46	11		T161	10		T155	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	5		T11	11		T24	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T4	7		T222	11		T241	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T4	1		T24	6		T32	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	5		T11	3		T46	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T45	11		T36	2		T240	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T150	7		T28	12		T74	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T11	10		T45	4		T24	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22552

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4022

1

T1

10

T4

8

T6

33