Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26574

1

T1

12

T2

2

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22695

1

T1

6

T3

3

T4

3

auto[ADC_CTRL_FILTER_COND_OUT]

3879

1

T1

6

T2

2

T4

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20540

1

T1

6

T4

21

T5

128

auto[1]

6034

1

T1

6

T2

2

T3

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22513

1

T1

12

T2

2

T3

3

auto[1]

4061

1

T4

11

T7

1

T9

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	327	1			T11	9		T14	4		T154	18
values[0]	48	1			T234	19		T298	10		T175	9
values[1]	505	1			T1	6		T179	2		T35	1
values[2]	659	1			T2	2		T4	18		T9	7
values[3]	836	1			T1	6		T6	15		T7	10
values[4]	748	1			T6	21		T9	12		T24	20
values[5]	693	1			T150	14		T91	22		T14	1
values[6]	612	1			T12	13		T170	1		T28	18
values[7]	660	1			T11	40		T43	1		T124	1
values[8]	683	1			T150	8		T170	1		T24	17
values[9]	3252	1			T3	3		T4	3		T8	28
minimum	17551	1			T5	128		T10	20		T50	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	484	1			T1	6		T2	1		T59	12
values[1]	809	1			T1	6		T2	1		T4	18
values[2]	631	1			T6	23		T7	10		T45	46
values[3]	801	1			T6	13		T9	12		T151	1
values[4]	727	1			T150	14		T91	22		T14	1
values[5]	502	1			T12	13		T124	1		T170	1
values[6]	2882	1			T3	3		T8	28		T11	40
values[7]	616	1			T150	8		T170	1		T24	17
values[8]	1203	1			T4	3		T46	23		T14	4
values[9]	138	1			T11	9		T194	26		T164	2
minimum	17781	1			T5	128		T10	20		T50	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22552

1

T1

2

T2

2

T3

3

auto[1]

4022

1

T1

10

T4

8

T6

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	6		T179	1		T238	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T2	1		T59	10		T179	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T9	1		T60	1		T220	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T1	6		T2	1		T4	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	9		T45	15		T24	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T6	23		T45	12		T46	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T6	13		T9	1		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T156	14		T251	13		T239	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T150	11		T91	12		T32	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T150	3		T14	1		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T12	1		T124	1		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T28	8		T151	1		T74	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1507	1			T3	3		T8	28		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T11	23		T46	12		T241	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T170	1		T24	7		T161	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T150	8		T162	1		T155	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T4	2		T46	12		T28	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	406	1			T14	4		T151	1		T154	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T11	4		T194	13		T164	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T164	1		T165	1		T254	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17469	1			T5	128		T10	20		T50	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T234	9		T167	15		T312	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T238	14		T233	12		T226	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T59	2		T221	15		T51	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	6		T60	1		T220	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T4	10		T28	13		T152	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	1		T45	6		T24	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T45	13		T46	17		T154	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T9	11		T152	11		T161	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T156	13		T239	9		T221	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T91	10		T32	13		T161	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T152	17		T227	5		T251	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T12	12		T32	10		T214	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T28	10		T74	11		T232	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	995	1			T189	12		T59	9		T266	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T11	17		T46	12		T223	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T24	10		T161	7		T228	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T162	10		T155	12		T156	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T4	1		T46	11		T28	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T154	9		T162	12		T166	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T11	5		T194	13		T163	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T254	10		T187	9		T103	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T74	1		T35	3		T49	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T234	10		T298	9		T175	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T11	4		T194	13		T164	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T14	4		T154	9		T267	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T259	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T234	9		T298	1		T175	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T1	6		T179	1		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T179	1		T257	12		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T9	1		T60	1		T220	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T2	2		T4	8		T123	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	9		T45	15		T24	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T1	6		T6	15		T45	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	13		T9	1		T24	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T6	8		T154	12		T219	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T150	11		T91	12		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T150	3		T14	1		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T12	1		T170	1		T32	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T28	8		T151	1		T74	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T43	1		T124	1		T59	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T11	23		T46	12		T223	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T170	1		T24	7		T161	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T150	8		T162	1		T155	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1521	1			T3	3		T4	2		T8	28
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	393	1			T151	1		T162	1		T164	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17425	1			T5	128		T10	20		T50	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T11	5		T194	13		T163	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T154	9		T267	4		T254	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T259	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T234	10		T298	9		T175	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T233	12		T230	14		T226	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T221	15		T51	17		T38	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	6		T60	1		T220	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T4	10		T59	2		T152	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	1		T45	6		T24	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T45	13		T46	17		T28	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T9	11		T24	11		T152	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T154	5		T156	13		T221	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T91	10		T161	2		T220	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T152	17		T227	5		T233	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T12	12		T32	23		T214	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T28	10		T74	11		T251	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T59	9		T155	15		T191	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T11	17		T46	12		T223	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T24	10		T161	7		T228	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T162	10		T155	12		T231	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	994	1			T4	1		T46	11		T28	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T162	12		T156	17		T166	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T74	1		T35	3		T49	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T1	1		T179	1		T238	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T2	1		T59	3		T179	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T9	7		T60	2		T220	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T1	1		T2	1		T4	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T7	2		T45	8		T24	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T6	2		T45	14		T46	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T6	1		T9	12		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T156	14		T251	1		T239	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T150	1		T91	11		T32	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T150	1		T14	1		T152	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T12	13		T124	1		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T28	11		T151	1		T74	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1341	1			T3	3		T8	2		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T11	19		T46	13		T241	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T170	1		T24	11		T161	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T150	1		T162	11		T155	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T4	2		T46	12		T28	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	440	1			T14	4		T151	1		T154	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T11	6		T194	14		T164	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T164	1		T165	1		T254	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17594	1			T5	128		T10	20		T50	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T234	11		T167	1		T312	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T1	5		T238	11		T233	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T59	9		T257	11		T51	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T241	15		T157	5		T249	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T1	5		T4	7		T28	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T7	8		T45	13		T24	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	21		T45	11		T46	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T6	12		T161	11		T214	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T156	13		T251	12		T240	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T150	10		T91	11		T32	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T150	2		T222	14		T109	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T32	2		T214	2		T260	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T28	7		T74	12		T54	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1161	1			T8	26		T44	25		T26	27
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	21		T46	11		T241	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T24	6		T161	11		T222	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T150	7		T155	11		T156	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T4	1		T46	11		T28	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T154	8		T222	9		T230	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T11	3		T194	12		T301	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T254	10		T187	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T255	9		T313	11		T92	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T234	8		T167	14		T175	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T11	6		T194	14		T164	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T14	4		T154	10		T267	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T259	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T234	11		T298	10		T175	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T1	1		T179	1		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T179	1		T257	1		T221	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T9	7		T60	2		T220	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T2	2		T4	11		T123	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T7	2		T45	8		T24	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T1	1		T6	1		T45	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T6	1		T9	12		T24	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T6	1		T154	6		T219	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T150	1		T91	11		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T150	1		T14	1		T152	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T12	13		T170	1		T32	25
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T28	11		T151	1		T74	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T43	1		T124	1		T59	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T11	19		T46	13		T223	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T170	1		T24	11		T161	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T150	1		T162	11		T155	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1332	1			T3	3		T4	2		T8	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	407	1			T151	1		T162	13		T164	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17551	1			T5	128		T10	20		T50	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T11	3		T194	12		T230	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T154	8		T254	9		T334	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T259	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T234	8		T175	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T1	5		T233	10		T230	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T257	11		T51	4		T38	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T238	11		T157	5		T323	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T4	7		T59	9		T238	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T7	8		T45	13		T24	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	5		T6	14		T45	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	12		T24	8		T161	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T6	7		T154	11		T156	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T150	10		T91	11		T161	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T150	2		T222	14		T109	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T32	15		T244	10		T214	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T28	7		T74	12		T263	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T59	4		T155	12		T260	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	21		T46	11		T231	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T24	6		T161	11		T222	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T150	7		T155	11		T241	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1183	1			T4	1		T8	26		T44	25
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T222	9		T156	12		T230	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22552

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4022

1

T1

10

T4

8

T6

33