Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T59	3		T179	1		T238	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T1	1		T2	1		T152	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T1	1		T9	7		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T2	1		T4	11		T28	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T7	2		T9	12		T45	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T6	2		T45	14		T46	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	1		T151	1		T152	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T156	14		T251	1		T239	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T150	1		T91	11		T32	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T150	1		T14	1		T152	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T12	13		T170	1		T155	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T151	1		T74	12		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1356	1			T3	3		T8	2		T11	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	10		T28	11		T241	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T170	1		T24	11		T35	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T150	1		T161	8		T162	24
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T4	2		T46	12		T28	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T14	4		T151	1		T74	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T11	6		T194	14		T165	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T164	1		T222	1		T230	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17552	1			T5	128		T10	20		T50	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T252	23		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T59	9		T238	11		T233	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	5		T234	8		T257	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T1	5		T24	14		T241	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T4	7		T28	17		T238	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T7	8		T45	13		T24	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	21		T45	11		T46	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T6	12		T260	2		T253	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T156	13		T251	12		T240	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T150	10		T91	11		T32	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T150	2		T222	14		T109	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T155	12		T214	2		T260	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T74	12		T233	8		T54	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1193	1			T8	26		T11	11		T44	25
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T11	10		T28	7		T241	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T24	6		T225	7		T261	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T150	7		T161	11		T155	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T4	1		T46	11		T28	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T154	8		T109	10		T224	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T11	3		T194	12		T262	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T222	9		T230	16		T120	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T252	20		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T164	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T250	8		T255	1		T93	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T234	11		T167	1		T256	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T59	3		T179	1		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	1		T179	1		T257	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T9	7		T123	1		T45	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T2	2		T4	11		T152	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	1		T7	2		T45	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T6	1		T45	14		T28	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T6	1		T9	12		T24	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T6	1		T46	18		T154	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T150	1		T91	11		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T150	1		T14	1		T152	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T12	13		T46	13		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T28	11		T151	1		T74	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T11	9		T124	1		T59	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T11	10		T223	11		T231	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T43	1		T170	1		T24	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T150	1		T161	8		T162	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1474	1			T3	3		T4	2		T8	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	462	1			T14	4		T151	1		T74	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17551	1			T5	128		T10	20		T50	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T255	9		T258	2		T259	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T234	8		T167	14		T256	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T59	9		T233	10		T230	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T1	5		T257	11		T51	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T45	9		T238	11		T157	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T4	7		T36	2		T238	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T1	5		T7	8		T45	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T6	14		T45	11		T28	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T6	12		T24	8		T253	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	7		T46	14		T154	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T150	10		T91	11		T161	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T150	2		T222	14		T109	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T46	11		T32	15		T244	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T28	7		T74	12		T263	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T11	11		T59	4		T155	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T11	10		T231	10		T233	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T24	6		T244	11		T225	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T150	7		T161	11		T155	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1282	1			T4	1		T8	26		T11	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T154	8		T222	9		T156	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22552

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4022

1

T1

10

T4

8

T6

33