Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26574

1

T1

12

T2

2

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22964

1

T1

6

T2

1

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3610

1

T1

6

T2

1

T4

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20671

1

T1

6

T4

21

T5

126

auto[1]

5903

1

T1

6

T2

2

T3

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22513

1

T1

12

T2

2

T3

3

auto[1]

4061

1

T4

11

T7

1

T9

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	414	1			T5	2		T12	2		T47	1
values[0]	41	1			T6	8		T226	21		T264	11
values[1]	882	1			T12	13		T124	1		T46	32
values[2]	2852	1			T3	3		T4	18		T8	28
values[3]	591	1			T2	1		T7	10		T9	12
values[4]	680	1			T11	20		T146	32		T60	24
values[5]	747	1			T6	13		T45	14		T35	1
values[6]	719	1			T1	6		T2	1		T43	1
values[7]	642	1			T4	3		T46	23		T150	11
values[8]	643	1			T11	9		T150	3		T32	13
values[9]	1196	1			T1	6		T6	15		T11	20
minimum	17167	1			T5	126		T10	20		T50	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1041	1			T6	8		T9	7		T12	13
values[1]	2758	1			T3	3		T4	18		T8	28
values[2]	705	1			T2	1		T7	10		T11	20
values[3]	679	1			T6	13		T9	12		T45	14
values[4]	734	1			T35	1		T222	10		T231	25
values[5]	712	1			T1	6		T2	1		T43	1
values[6]	682	1			T4	3		T24	20		T28	31
values[7]	674	1			T6	15		T11	9		T46	23
values[8]	794	1			T1	6		T45	7		T91	22
values[9]	224	1			T11	20		T151	1		T165	1
minimum	17571	1			T5	128		T10	20		T50	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22552

1

T1

2

T2

2

T3

3

auto[1]

4022

1

T1

10

T4

8

T6

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T6	8		T9	1		T12	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T151	1		T161	11		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1502	1			T3	3		T4	8		T8	28
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T170	1		T24	7		T111	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	9		T154	9		T227	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T2	1		T11	12		T74	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T9	1		T45	10		T146	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	13		T60	1		T218	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T231	12		T233	9		T109	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T35	1		T222	10		T107	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T2	1		T43	1		T45	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T1	6		T150	11		T24	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T24	9		T161	12		T194	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T4	2		T28	18		T32	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	15		T11	4		T46	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T152	1		T179	1		T220	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T1	6		T45	5		T91	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T165	1		T166	1		T239	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T165	1		T156	13		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T11	11		T151	1		T232	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17425	1			T5	128		T10	20		T50	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T265	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T9	6		T12	12		T46	29
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T161	2		T162	10		T231	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	933	1			T4	10		T189	12		T266	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T24	10		T253	9		T262	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	1		T154	9		T227	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T11	8		T60	10		T155	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T9	11		T45	4		T146	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T229	2		T267	4		T115	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T231	13		T233	11		T109	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T268	9		T262	13		T173	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T45	13		T28	2		T60	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T24	10		T230	14		T269	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T24	11		T161	13		T194	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	1		T28	13		T32	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T11	5		T46	11		T32	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T152	17		T220	15		T156	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T45	2		T91	10		T59	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T166	9		T239	9		T232	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T156	17		T51	13		T254	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T11	9		T232	10		T270	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T74	1		T35	3		T49	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T265	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	397	1			T5	2		T12	2		T47	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T6	8		T271	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T226	12		T264	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T12	1		T124	1		T46	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T151	1		T161	11		T241	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1536	1			T3	3		T4	8		T8	28
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T170	1		T24	7		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T7	9		T9	1		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T2	1		T74	1		T155	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T146	15		T161	12		T35	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T11	12		T60	14		T222	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T45	10		T37	1		T231	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T6	13		T35	1		T157	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T2	1		T43	1		T45	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T1	6		T24	15		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T46	12		T24	9		T179	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T4	2		T150	11		T28	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T11	4		T150	3		T32	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T59	10		T152	1		T220	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	344	1			T1	6		T6	15		T45	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T11	11		T151	1		T179	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17041	1			T5	126		T10	20		T50	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T156	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T226	9		T264	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	12		T46	17		T220	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T161	2		T231	12		T229	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	945	1			T4	10		T9	6		T46	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T24	10		T162	10		T249	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	1		T9	11		T154	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T155	12		T230	11		T214	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T146	17		T161	7		T35	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T11	8		T60	10		T262	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T45	4		T231	13		T233	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T229	2		T268	9		T267	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T45	13		T28	2		T60	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T24	10		T233	10		T230	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T46	11		T24	11		T161	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T4	1		T28	13		T32	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T11	5		T32	10		T59	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T59	2		T152	8		T220	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T45	2		T91	10		T74	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T11	9		T166	9		T239	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T74	1		T35	3		T49	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T6	1		T9	7		T12	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T151	1		T161	3		T162	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T3	3		T4	11		T8	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T170	1		T24	11		T111	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T7	2		T154	10		T227	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T2	1		T11	9		T74	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T9	12		T45	5		T146	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T6	1		T60	1		T218	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T231	14		T233	12		T109	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T35	1		T222	1		T107	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T2	1		T43	1		T45	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	1		T150	1		T24	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T24	12		T161	14		T194	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T4	2		T28	14		T32	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T6	1		T11	6		T46	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T152	18		T179	1		T220	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T1	1		T45	3		T91	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T165	1		T166	10		T239	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T165	1		T156	18		T51	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T11	10		T151	1		T232	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17551	1			T5	128		T10	20		T50	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T265	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T6	7		T46	25		T150	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T161	10		T241	15		T249	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1158	1			T4	7		T8	26		T44	25
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T24	6		T253	9		T262	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	8		T154	8		T155	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	11		T60	12		T155	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T45	9		T146	14		T161	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T6	12		T251	12		T157	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T231	11		T233	8		T109	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T222	9		T224	2		T268	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T45	11		T28	12		T233	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T1	5		T150	10		T24	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T24	8		T161	11		T194	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T4	1		T28	17		T32	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T6	14		T11	3		T46	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T156	13		T238	2		T15	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T1	5		T45	4		T91	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T38	2		T260	8		T253	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T156	12		T272	16		T254	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T11	10		T167	11		T246	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T265	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	402	1			T5	2		T12	2		T47	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T6	1		T271	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T226	10		T264	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T12	13		T124	1		T46	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T151	1		T161	3		T241	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T3	3		T4	11		T8	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T170	1		T24	11		T162	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	2		T9	12		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T2	1		T74	1		T155	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T146	18		T161	8		T35	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T11	9		T60	12		T222	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T45	5		T37	1		T231	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T6	1		T35	1		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T2	1		T43	1		T45	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	1		T24	11		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T46	12		T24	12		T179	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T4	2		T150	1		T28	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T11	6		T150	1		T32	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T59	3		T152	9		T220	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T1	1		T6	1		T45	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T11	10		T151	1		T179	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17167	1			T5	126		T10	20		T50	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T156	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T6	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T226	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T46	14		T150	7		T238	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T161	10		T241	15		T109	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1195	1			T4	7		T8	26		T44	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T24	6		T249	6		T255	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T7	8		T154	8		T155	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T155	11		T257	11		T230	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T146	14		T161	11		T241	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	11		T60	12		T222	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T45	9		T231	11		T233	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T6	12		T157	5		T268	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T45	11		T28	12		T230	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T1	5		T24	14		T230	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T46	11		T24	8		T161	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T4	1		T150	10		T28	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T11	3		T150	2		T32	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T59	9		T156	13		T238	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T1	5		T6	14		T45	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T11	10		T38	2		T260	20

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22552

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4022

1

T1

10

T4

8

T6

33