Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26574

1

T1

12

T2

2

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23058

1

T3

3

T4

21

T5

128

auto[ADC_CTRL_FILTER_COND_OUT]

3516

1

T1

12

T2

2

T6

28

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20747

1

T1

6

T2

1

T4

18

auto[1]

5827

1

T1

6

T2

1

T3

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22513

1

T1

12

T2

2

T3

3

auto[1]

4061

1

T4

11

T7

1

T9

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	19	1			T273	19		-	-		-	-
values[0]	43	1			T11	20		T32	13		T182	9
values[1]	693	1			T6	15		T150	11		T28	15
values[2]	864	1			T11	9		T45	25		T150	3
values[3]	736	1			T4	3		T11	20		T43	1
values[4]	2883	1			T3	3		T7	10		T8	28
values[5]	497	1			T1	6		T4	18		T45	7
values[6]	898	1			T1	6		T6	8		T45	14
values[7]	513	1			T124	1		T151	1		T74	1
values[8]	729	1			T2	1		T6	13		T46	32
values[9]	1148	1			T2	1		T9	19		T123	1
minimum	17551	1			T5	128		T10	20		T50	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	909	1			T6	15		T11	20		T28	15
values[1]	884	1			T11	9		T45	25		T150	14
values[2]	846	1			T4	3		T11	20		T43	1
values[3]	2626	1			T3	3		T7	10		T8	28
values[4]	631	1			T1	6		T4	18		T6	8
values[5]	785	1			T1	6		T45	14		T32	27
values[6]	615	1			T6	13		T124	1		T170	1
values[7]	781	1			T2	1		T9	7		T46	32
values[8]	756	1			T2	1		T9	12		T123	1
values[9]	187	1			T244	12		T15	11		T274	17
minimum	17554	1			T5	128		T10	20		T50	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22552

1

T1

2

T2

2

T3

3

auto[1]

4022

1

T1

10

T4

8

T6

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T11	12		T275	1		T111	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T6	15		T28	13		T32	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T45	12		T150	11		T24	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	4		T150	3		T28	26
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T4	2		T11	11		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T91	12		T14	1		T24	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1398	1			T3	3		T7	9		T8	28
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T12	1		T162	1		T234	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	8		T6	8		T45	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T1	6		T46	12		T24	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T32	14		T152	1		T155	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	6		T45	10		T59	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T74	1		T161	11		T35	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	13		T124	1		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T170	1		T29	1		T161	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T2	1		T9	1		T46	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T9	1		T179	1		T60	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T2	1		T123	1		T46	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T15	3		T276	21		T277	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T244	12		T274	9		T17	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17425	1			T5	128		T10	20		T50	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T224	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	8		T158	8		T262	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T28	2		T32	10		T220	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T45	13		T24	10		T74	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	5		T28	23		T60	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T4	1		T11	9		T156	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T91	10		T24	10		T146	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	897	1			T7	1		T189	12		T59	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	12		T162	10		T234	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T4	10		T45	2		T154	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T46	11		T24	11		T152	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T32	13		T152	11		T155	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T45	4		T59	9		T238	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T161	2		T191	18		T278	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T161	13		T227	5		T233	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T161	7		T220	13		T232	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T9	6		T46	17		T152	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T9	11		T60	1		T239	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T46	12		T166	9		T269	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T15	8		T277	11		T177	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T274	8		T115	3		T279	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T74	1		T35	3		T49	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T273	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T11	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T32	3		T182	9		T280	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T150	11		T275	1		T111	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	15		T28	13		T155	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T45	12		T24	7		T74	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T11	4		T150	3		T28	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T4	2		T11	11		T43	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T91	12		T14	1		T28	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1438	1			T3	3		T7	9		T8	28
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T12	1		T24	24		T146	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T4	8		T45	5		T59	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T1	6		T46	12		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T6	8		T150	8		T32	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T1	6		T45	10		T161	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T74	1		T161	11		T35	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T124	1		T151	1		T231	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T170	1		T29	1		T161	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T2	1		T6	13		T46	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T9	1		T179	1		T60	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T2	1		T9	1		T123	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17425	1			T5	128		T10	20		T50	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T273	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T11	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T32	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T262	13		T226	9		T250	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T28	2		T155	12		T156	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T45	13		T24	10		T74	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T11	5		T28	13		T60	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T4	1		T11	9		T240	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T91	10		T28	10		T35	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	907	1			T7	1		T189	12		T266	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T12	12		T24	21		T146	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T4	10		T45	2		T59	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T46	11		T59	9		T152	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T32	13		T152	11		T154	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T45	4		T161	13		T238	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T161	2		T268	10		T191	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T231	4		T229	2		T249	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T161	7		T220	13		T232	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T46	17		T152	17		T227	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T9	11		T60	1		T239	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T9	6		T46	12		T166	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T74	1		T35	3		T49	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T11	9		T275	1		T111	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T6	1		T28	3		T32	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T45	14		T150	1		T24	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T11	6		T150	1		T28	25
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T4	2		T11	10		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T91	11		T14	1		T24	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1217	1			T3	3		T7	2		T8	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T12	13		T162	11		T234	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	11		T6	1		T45	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	1		T46	12		T24	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T32	14		T152	12		T155	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T1	1		T45	5		T59	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T74	1		T161	3		T35	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T6	1		T124	1		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T170	1		T29	1		T161	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T2	1		T9	7		T46	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T9	12		T179	1		T60	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T2	1		T123	1		T46	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T15	10		T276	1		T277	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T244	1		T274	9		T17	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17551	1			T5	128		T10	20		T50	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T224	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T11	11		T262	19		T226	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T6	14		T28	12		T32	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T45	11		T150	10		T24	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T11	3		T150	2		T28	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T4	1		T11	10		T156	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T91	11		T24	14		T146	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1078	1			T7	8		T8	26		T44	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T234	8		T36	2		T230	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T4	7		T6	7		T45	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	5		T46	11		T24	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T32	13		T155	12		T109	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T1	5		T45	9		T59	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T161	10		T246	10		T276	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T6	12		T161	11		T249	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T161	11		T257	11		T225	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T46	14		T214	12		T281	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T233	10		T240	8		T109	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T46	11		T222	23		T241	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T15	1		T276	20		T277	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T244	11		T274	8		T115	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T224	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T273	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T11	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T32	11		T182	1		T280	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T150	1		T275	1		T111	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T6	1		T28	3		T155	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T45	14		T24	11		T74	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T11	6		T150	1		T28	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T4	2		T11	10		T43	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T91	11		T14	1		T28	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1227	1			T3	3		T7	2		T8	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T12	13		T24	23		T146	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T4	11		T45	3		T59	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T1	1		T46	12		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T6	1		T150	1		T32	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	1		T45	5		T161	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T74	1		T161	3		T35	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T124	1		T151	1		T231	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T170	1		T29	1		T161	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T2	1		T6	1		T46	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T9	12		T179	1		T60	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T2	1		T9	7		T123	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17551	1			T5	128		T10	20		T50	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T273	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T11	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T32	2		T182	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T150	10		T262	19		T226	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T6	14		T28	12		T155	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T45	11		T24	6		T74	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	3		T150	2		T28	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T4	1		T11	10		T240	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T91	11		T28	7		T241	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1118	1			T7	8		T8	26		T44	25
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T24	22		T146	14		T154	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T4	7		T45	4		T59	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T1	5		T46	11		T59	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T6	7		T150	7		T32	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	5		T45	9		T161	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T161	10		T268	10		T282	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T231	10		T249	6		T230	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T161	11		T257	11		T225	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	12		T46	14		T214	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T233	10		T240	8		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T46	11		T222	23		T241	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22552

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4022

1

T1

10

T4

8

T6

33