Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26574

1

T1

12

T2

2

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20926

1

T1

6

T2

1

T4

3

auto[ADC_CTRL_FILTER_COND_OUT]

5648

1

T1

6

T2

1

T3

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20629

1

T1

6

T2

1

T4

18

auto[1]

5945

1

T1

6

T2

1

T3

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22513

1

T1

12

T2

2

T3

3

auto[1]

4061

1

T4

11

T7

1

T9

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	5	1			T226	2		T283	3		-	-
values[0]	87	1			T6	15		T9	12		T40	11
values[1]	571	1			T4	18		T150	19		T152	12
values[2]	528	1			T7	10		T11	20		T45	14
values[3]	813	1			T6	8		T11	9		T32	27
values[4]	583	1			T4	3		T6	13		T11	20
values[5]	712	1			T2	1		T45	25		T24	25
values[6]	753	1			T9	7		T24	20		T28	15
values[7]	861	1			T1	12		T12	13		T170	1
values[8]	698	1			T123	1		T45	7		T46	23
values[9]	3412	1			T2	1		T3	3		T8	28
minimum	17551	1			T5	128		T10	20		T50	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	714	1			T4	18		T7	10		T9	12
values[1]	2921	1			T3	3		T8	28		T11	29
values[2]	624	1			T6	8		T11	20		T46	24
values[3]	681	1			T2	1		T6	13		T46	32
values[4]	601	1			T4	3		T45	25		T29	1
values[5]	831	1			T9	7		T24	20		T28	15
values[6]	870	1			T1	12		T12	13		T46	23
values[7]	584	1			T2	1		T43	1		T123	1
values[8]	896	1			T124	1		T151	1		T60	24
values[9]	265	1			T275	1		T229	8		T51	22
minimum	17587	1			T5	128		T6	15		T10	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22552

1

T1

2

T2

2

T3

3

auto[1]

4022

1

T1

10

T4

8

T6

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	9		T9	1		T150	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T4	8		T150	8		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T45	10		T91	12		T194	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1529	1			T3	3		T8	28		T11	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T6	8		T11	11		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T46	12		T59	10		T38	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T2	1		T6	13		T179	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T46	15		T24	15		T28	26
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T4	2		T32	3		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T45	12		T29	1		T74	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T24	9		T59	5		T227	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T9	1		T28	13		T146	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T1	6		T12	1		T46	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	6		T152	1		T35	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T123	1		T14	5		T24	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T2	1		T43	1		T45	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T124	1		T60	14		T155	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T151	1		T108	1		T245	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T275	1		T51	5		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T229	1		T284	1		T285	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17425	1			T5	128		T10	20		T50	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T6	15		T175	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	1		T9	11		T74	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T4	10		T152	11		T223	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T45	4		T91	10		T194	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1013	1			T11	13		T32	13		T189	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T11	9		T233	11		T225	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T46	12		T59	2		T38	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T154	9		T60	1		T161	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T46	17		T24	10		T28	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T4	1		T32	10		T157	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T45	13		T161	7		T220	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T24	11		T59	9		T227	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T9	6		T28	2		T146	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T12	12		T46	11		T224	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T152	17		T35	1		T238	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T24	10		T221	15		T286	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T45	2		T162	12		T109	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T60	10		T155	12		T234	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T245	7		T268	10		T287	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T51	17		T226	1		T288	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T229	7		T183	9		T289	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T74	1		T35	3		T49	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T175	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T226	1		T283	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T9	1		T182	19		T290	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T6	15		T40	6		T291	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T74	13		T275	1		T214	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T4	8		T150	19		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T7	9		T45	10		T150	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T11	12		T46	12		T251	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	8		T161	12		T194	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T11	4		T32	14		T59	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T4	2		T6	13		T11	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T46	15		T152	1		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	1		T32	3		T227	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T45	12		T24	15		T28	26
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T24	9		T59	5		T35	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T9	1		T28	13		T146	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T1	6		T12	1		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T1	6		T257	12		T251	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T123	1		T46	12		T14	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T45	5		T152	1		T35	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	432	1			T124	1		T151	1		T60	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1627	1			T2	1		T3	3		T8	28
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17425	1			T5	128		T10	20		T50	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T226	1		T283	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T9	11		T290	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T40	5		T291	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T74	11		T214	3		T39	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T4	10		T152	11		T223	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T7	1		T45	4		T91	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T11	8		T46	12		T251	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T161	13		T194	13		T220	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T11	5		T32	13		T59	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T4	1		T11	9		T154	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T46	17		T152	8		T230	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T32	10		T227	5		T162	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T45	13		T24	10		T28	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T24	11		T59	9		T232	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T9	6		T28	2		T146	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	12		T156	13		T240	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T238	14		T239	12		T233	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T46	11		T24	10		T224	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T45	2		T152	17		T35	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T60	10		T155	12		T234	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1053	1			T189	12		T266	13		T153	22
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T74	1		T35	3		T49	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	2		T9	12		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T4	11		T150	1		T152	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T45	5		T91	11		T194	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1338	1			T3	3		T8	2		T11	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T6	1		T11	10		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T46	13		T59	3		T38	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T2	1		T6	1		T179	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T46	18		T24	11		T28	25
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T4	2		T32	11		T157	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T45	14		T29	1		T74	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T24	12		T59	10		T227	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T9	7		T28	3		T146	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T1	1		T12	13		T46	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	1		T152	18		T35	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T123	1		T14	5		T24	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T2	1		T43	1		T45	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T124	1		T60	12		T155	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T151	1		T108	1		T245	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T275	1		T51	18		T226	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T229	8		T284	1		T285	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17551	1			T5	128		T10	20		T50	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T6	1		T175	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T7	8		T150	2		T74	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T4	7		T150	7		T109	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T45	9		T91	11		T194	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1204	1			T8	26		T11	14		T44	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T6	7		T11	10		T233	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T46	11		T59	9		T38	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T6	12		T154	8		T161	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T46	14		T24	14		T28	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T4	1		T32	2		T224	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T45	11		T161	11		T156	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T24	8		T59	4		T156	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T28	12		T146	14		T251	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T1	5		T46	11		T222	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	5		T257	11		T238	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T24	6		T160	12		T196	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T45	4		T109	10		T214	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T60	12		T155	11		T234	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T245	10		T268	10		T287	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T51	4		T288	9		T255	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T289	10		T292	7		T176	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T6	14		T175	10		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T226	2		T283	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T9	12		T182	1		T290	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T6	1		T40	7		T291	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T74	12		T275	1		T214	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T4	11		T150	2		T152	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T7	2		T45	5		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T11	9		T46	13		T251	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T6	1		T161	14		T194	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T11	6		T32	14		T59	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T4	2		T6	1		T11	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T46	18		T152	9		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T2	1		T32	11		T227	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T45	14		T24	11		T28	25
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T24	12		T59	10		T35	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T9	7		T28	3		T146	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T1	1		T12	13		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T1	1		T257	1		T251	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T123	1		T46	12		T14	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T45	3		T152	18		T35	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	384	1			T124	1		T151	1		T60	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1410	1			T2	1		T3	3		T8	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17551	1			T5	128		T10	20		T50	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T182	18		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T6	14		T40	4		T291	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T74	12		T214	2		T39	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T4	7		T150	17		T240	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T7	8		T45	9		T150	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T11	11		T46	11		T230	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T6	7		T161	11		T194	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T11	3		T32	13		T59	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T4	1		T6	12		T11	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T46	14		T222	11		T230	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T32	2		T155	12		T224	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T45	11		T24	14		T28	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T24	8		T59	4		T253	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T28	12		T146	14		T161	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T1	5		T222	9		T156	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	5		T257	11		T251	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T46	11		T24	6		T293	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T45	4		T244	11		T245	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T60	12		T155	11		T234	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1270	1			T8	26		T44	25		T26	27

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22552

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4022

1

T1

10

T4

8

T6

33