Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26574

1

T1

12

T2

2

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23019

1

T1

6

T2

2

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3555

1

T1

6

T4

18

T6

28

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20834

1

T1

6

T2

2

T4

21

auto[1]

5740

1

T1

6

T3

3

T6

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22513

1

T1

12

T2

2

T3

3

auto[1]

4061

1

T4

11

T7

1

T9

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	301	1			T7	10		T11	9		T24	25
values[0]	34	1			T294	23		T295	1		T101	10
values[1]	740	1			T4	18		T6	13		T43	1
values[2]	736	1			T46	79		T151	1		T60	2
values[3]	803	1			T1	6		T9	12		T150	8
values[4]	591	1			T124	1		T24	20		T179	1
values[5]	2756	1			T3	3		T8	28		T44	27
values[6]	654	1			T9	7		T150	11		T170	1
values[7]	828	1			T2	1		T6	15		T45	25
values[8]	753	1			T2	1		T4	3		T6	8
values[9]	827	1			T1	6		T11	20		T45	7
minimum	17551	1			T5	128		T10	20		T50	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	775	1			T4	18		T46	56		T28	18
values[1]	738	1			T9	12		T46	23		T91	22
values[2]	653	1			T1	6		T150	8		T170	1
values[3]	2716	1			T3	3		T8	28		T44	27
values[4]	713	1			T123	1		T28	31		T29	1
values[5]	626	1			T9	7		T45	25		T170	1
values[6]	841	1			T2	1		T6	15		T150	11
values[7]	791	1			T2	1		T4	3		T6	8
values[8]	871	1			T7	10		T11	9		T45	7
values[9]	44	1			T1	6		T246	12		T235	16
minimum	17806	1			T5	128		T6	13		T10	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22552

1

T1

2

T2

2

T3

3

auto[1]

4022

1

T1

10

T4

8

T6

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T28	8		T151	1		T220	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T4	8		T46	27		T151	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T9	1		T60	1		T155	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T46	12		T91	12		T60	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T150	8		T194	13		T239	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T1	6		T170	1		T74	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1447	1			T3	3		T8	28		T44	27
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T24	7		T227	1		T275	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T32	17		T152	1		T179	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T123	1		T28	18		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T45	12		T170	1		T28	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T9	1		T154	9		T165	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T2	1		T152	1		T275	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T6	15		T150	11		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T2	1		T4	2		T6	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T11	11		T12	1		T74	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T11	4		T151	1		T59	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T7	9		T45	5		T14	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T1	6		T246	12		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T235	8		T296	1		T185	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17497	1			T5	128		T10	20		T50	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T6	13		T232	1		T109	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T28	10		T220	13		T38	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T4	10		T46	29		T234	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T9	11		T60	1		T155	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T46	11		T91	10		T60	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T194	13		T239	12		T221	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T220	15		T162	12		T163	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	907	1			T45	4		T24	11		T189	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T24	10		T227	5		T230	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T32	23		T152	8		T251	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T28	13		T161	13		T155	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T45	13		T28	2		T146	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T9	6		T154	9		T158	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T152	11		T39	2		T245	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T152	17		T154	5		T238	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T4	1		T11	8		T238	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T11	9		T12	12		T74	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T11	5		T59	9		T239	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T7	1		T45	2		T24	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T235	8		T296	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T74	1		T35	3		T49	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T232	10		T109	11		T294	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T11	4		T59	5		T35	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T7	9		T24	15		T297	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T294	11		T295	1		T101	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T43	1		T28	8		T220	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T4	8		T6	13		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T151	1		T60	1		T155	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T46	39		T35	1		T234	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	1		T150	8		T156	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T1	6		T170	1		T91	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T124	1		T24	9		T194	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T179	1		T227	1		T275	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1542	1			T3	3		T8	28		T44	27
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T123	1		T24	7		T29	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T170	1		T152	1		T146	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T9	1		T150	11		T28	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T2	1		T45	12		T28	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T6	15		T152	1		T154	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T2	1		T4	2		T6	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T11	11		T12	1		T161	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	6		T11	12		T14	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T45	5		T14	1		T59	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17425	1			T5	128		T10	20		T50	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T11	5		T59	9		T288	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T7	1		T24	10		T40	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T294	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T28	10		T220	13		T38	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T4	10		T60	10		T232	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T60	1		T155	15		T40	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T46	40		T234	10		T156	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	11		T156	17		T239	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T91	10		T161	2		T35	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T24	11		T194	13		T231	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T227	5		T163	7		T230	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T45	4		T32	23		T189	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T24	10		T36	9		T240	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T152	8		T146	17		T230	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T9	6		T28	13		T154	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T45	13		T28	2		T233	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T152	17		T154	5		T221	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T4	1		T152	11		T238	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T11	9		T12	12		T161	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	8		T239	9		T230	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T45	2		T59	2		T74	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T74	1		T35	3		T49	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T28	11		T151	1		T220	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T4	11		T46	31		T151	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T9	12		T60	2		T155	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T46	12		T91	11		T60	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T150	1		T194	14		T239	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T1	1		T170	1		T74	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1235	1			T3	3		T8	2		T44	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T24	11		T227	6		T275	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T32	25		T152	9		T179	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T123	1		T28	14		T29	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T45	14		T170	1		T28	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T9	7		T154	10		T165	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T2	1		T152	12		T275	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T6	1		T150	1		T152	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T2	1		T4	2		T6	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T11	10		T12	13		T74	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T11	6		T151	1		T59	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T7	2		T45	3		T14	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T1	1		T246	1		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T235	9		T296	9		T185	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17606	1			T5	128		T10	20		T50	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T6	1		T232	11		T109	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T28	7		T38	2		T224	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T4	7		T46	25		T234	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T155	12		T156	12		T287	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T46	11		T91	11		T60	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T150	7		T194	12		T253	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T1	5		T51	4		T268	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1119	1			T8	26		T44	25		T45	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T24	6		T230	14		T260	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T32	15		T244	10		T233	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T28	17		T161	11		T155	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T45	11		T28	12		T146	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T154	8		T224	2		T287	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T39	2		T245	10		T226	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T6	14		T150	10		T154	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T4	1		T6	7		T11	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	10		T74	12		T161	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	3		T59	4		T230	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	8		T45	4		T24	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T1	5		T246	11		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T235	7		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T241	11		T214	9		T261	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T6	12		T109	10		T294	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T11	6		T59	10		T35	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T7	2		T24	11		T297	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T294	13		T295	1		T101	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T43	1		T28	11		T220	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T4	11		T6	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T151	1		T60	2		T155	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T46	43		T35	1		T234	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T9	12		T150	1		T156	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T1	1		T170	1		T91	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T124	1		T24	12		T194	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T179	1		T227	6		T275	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1306	1			T3	3		T8	2		T44	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T123	1		T24	11		T29	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T170	1		T152	9		T146	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T9	7		T150	1		T28	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T2	1		T45	14		T28	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T6	1		T152	18		T154	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	1		T4	2		T6	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T11	10		T12	13		T161	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T1	1		T11	9		T14	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T45	3		T14	1		T59	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17551	1			T5	128		T10	20		T50	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T11	3		T59	4		T167	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T7	8		T24	14		T40	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T294	10		T101	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T28	7		T241	11		T38	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	7		T6	12		T60	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T155	12		T287	2		T262	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T46	36		T234	8		T222	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T150	7		T156	12		T253	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T1	5		T91	11		T161	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T24	8		T194	12		T231	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T230	14		T260	12		T261	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1204	1			T8	26		T44	25		T45	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T24	6		T36	2		T157	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T146	14		T230	10		T111	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T150	10		T28	17		T154	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T45	11		T28	12		T233	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T6	14		T154	11		T249	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T4	1		T6	7		T150	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T11	10		T161	11		T251	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	5		T11	11		T230	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T45	4		T59	9		T74	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22552

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4022

1

T1

10

T4

8

T6

33