Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26574

1

T1

12

T2

2

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22925

1

T1

6

T2

1

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3649

1

T1

6

T2

1

T4

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20544

1

T1

12

T2

1

T4

21

auto[1]

6030

1

T2

1

T3

3

T6

28

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22513

1

T1

12

T2

2

T3

3

auto[1]

4061

1

T4

11

T7

1

T9

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	51	1			T146	32		T234	19		-	-
values[0]	66	1			T46	23		T170	1		T221	3
values[1]	445	1			T6	8		T227	6		T164	1
values[2]	699	1			T4	18		T7	10		T11	20
values[3]	695	1			T12	13		T43	1		T14	4
values[4]	594	1			T6	13		T9	12		T11	9
values[5]	729	1			T2	1		T150	11		T59	14
values[6]	932	1			T2	1		T45	14		T46	32
values[7]	708	1			T11	20		T123	1		T74	1
values[8]	2822	1			T3	3		T6	15		T8	28
values[9]	1282	1			T1	12		T4	3		T45	7
minimum	17551	1			T5	128		T10	20		T50	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	777	1			T4	18		T6	8		T45	25
values[1]	725	1			T7	10		T11	20		T12	13
values[2]	659	1			T11	9		T43	1		T14	4
values[3]	694	1			T2	1		T6	13		T150	11
values[4]	510	1			T9	12		T170	1		T59	14
values[5]	858	1			T2	1		T45	14		T46	32
values[6]	2903	1			T3	3		T6	15		T8	28
values[7]	714	1			T1	6		T4	3		T9	7
values[8]	978	1			T150	3		T91	22		T24	17
values[9]	197	1			T1	6		T179	1		T257	12
minimum	17559	1			T5	128		T10	20		T50	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22552

1

T1

2

T2

2

T3

3

auto[1]

4022

1

T1

10

T4

8

T6

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T4	8		T45	12		T46	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T6	8		T170	1		T164	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	9		T151	1		T275	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T11	11		T12	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T11	4		T43	1		T14	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T28	18		T151	1		T74	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T2	1		T6	13		T24	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T150	11		T60	1		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T9	1		T59	5		T161	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T170	1		T220	1		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T45	10		T150	8		T74	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T2	1		T46	15		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1591	1			T3	3		T6	15		T8	28
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T241	16		T251	1		T166	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T9	1		T45	5		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T1	6		T4	2		T46	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T29	1		T179	1		T146	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T150	3		T91	12		T24	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T1	6		T179	1		T180	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T257	12		T108	1		T303	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17433	1			T5	128		T10	20		T50	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T4	10		T45	13		T46	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T240	6		T269	10		T253	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T7	1		T231	12		T15	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T11	9		T12	12		T161	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T11	5		T28	10		T152	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T28	13		T74	11		T60	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T24	10		T28	2		T163	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T60	1		T156	17		T238	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T9	11		T59	9		T161	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T220	13		T162	12		T239	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T45	4		T229	2		T228	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T46	17		T152	11		T229	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	985	1			T11	8		T189	12		T266	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T251	11		T166	9		T239	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	6		T45	2		T24	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T4	1		T46	12		T59	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T146	17		T154	14		T162	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T91	10		T24	10		T32	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T232	6		T191	18		T304	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T303	1		T295	2		T247	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T74	1		T35	3		T49	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T146	15		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T234	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T46	12		T221	1		T305	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T170	1		T108	1		T306	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T227	1		T164	1		T222	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T6	8		T38	2		T269	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T4	8		T7	9		T45	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T11	11		T151	1		T60	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T43	1		T14	4		T28	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T12	1		T151	1		T60	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T6	13		T9	1		T11	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T170	1		T28	18		T74	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T2	1		T59	5		T161	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T150	11		T60	1		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T45	10		T150	8		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T2	1		T46	15		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T11	12		T123	1		T74	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T241	16		T251	1		T166	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1505	1			T3	3		T6	15		T8	28
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T14	1		T59	10		T220	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T1	6		T45	5		T124	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T1	6		T4	2		T46	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17425	1			T5	128		T10	20		T50	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T146	17		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T234	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T46	11		T221	2		T211	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T307	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T227	5		T238	3		T223	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T269	10		T253	11		T160	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T4	10		T7	1		T45	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T11	9		T240	6		T158	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T28	10		T36	9		T231	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T12	12		T60	10		T161	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T9	11		T11	5		T24	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T28	13		T74	11		T238	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T59	9		T161	2		T51	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T60	1		T162	12		T156	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T45	4		T229	2		T40	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T46	17		T152	11		T220	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T11	8		T228	2		T109	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T251	11		T166	9		T231	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	940	1			T9	6		T189	12		T266	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T59	2		T220	13		T155	27
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T45	2		T24	11		T154	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T4	1		T46	12		T91	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T74	1		T35	3		T49	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T4	11		T45	14		T46	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T6	1		T170	1		T164	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	2		T151	1		T275	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T11	10		T12	13		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	6		T43	1		T14	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T28	14		T151	1		T74	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T2	1		T6	1		T24	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T150	1		T60	2		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	12		T59	10		T161	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T170	1		T220	14		T162	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T45	5		T150	1		T74	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T2	1		T46	18		T152	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T3	3		T6	1		T8	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T241	1		T251	12		T166	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T9	7		T45	3		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T1	1		T4	2		T46	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T29	1		T179	1		T146	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T150	1		T91	11		T24	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T1	1		T179	1		T180	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T257	1		T108	1		T303	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17552	1			T5	128		T10	20		T50	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T4	7		T45	11		T46	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T6	7		T240	7		T253	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T7	8		T15	1		T287	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T11	10		T161	11		T230	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T11	3		T28	7		T36	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T28	17		T74	12		T60	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	12		T24	14		T28	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T150	10		T156	12		T238	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T59	4		T161	10		T244	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T281	8		T308	2		T34	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T45	9		T150	7		T109	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T46	14		T244	10		T38	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1259	1			T6	14		T8	26		T11	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T241	15		T231	10		T54	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T45	4		T24	8		T194	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T1	5		T4	1		T46	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T146	14		T154	19		T251	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T150	2		T91	11		T24	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T1	5		T224	2		T192	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T257	11		T303	1		T295	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T236	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T146	18		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T234	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T46	12		T221	3		T305	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T170	1		T108	1		T306	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T227	6		T164	1		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T6	1		T38	2		T269	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T4	11		T7	2		T45	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	10		T151	1		T60	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T43	1		T14	4		T28	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T12	13		T151	1		T60	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T6	1		T9	12		T11	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T170	1		T28	14		T74	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T2	1		T59	10		T161	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T150	1		T60	2		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T45	5		T150	1		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T2	1		T46	18		T152	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	9		T123	1		T74	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T241	1		T251	12		T166	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1274	1			T3	3		T6	1		T8	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T14	1		T59	3		T220	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	351	1			T1	1		T45	3		T124	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	407	1			T1	1		T4	2		T46	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17551	1			T5	128		T10	20		T50	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T146	14		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T234	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T46	11		T211	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T306	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T222	14		T238	2		T230	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T6	7		T253	10		T160	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T4	7		T7	8		T45	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T11	10		T240	7		T309	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T28	7		T36	2		T249	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T60	12		T161	11		T222	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T6	12		T11	3		T24	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T28	17		T74	12		T238	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T59	4		T161	10		T51	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T150	10		T156	12		T111	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T45	9		T150	7		T244	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T46	14		T38	2		T225	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	11		T109	10		T225	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T241	15		T244	10		T231	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1171	1			T6	14		T8	26		T44	25
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T59	9		T155	23		T260	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T1	5		T45	4		T24	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T1	5		T4	1		T46	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22552

1

T1

2

T2

2

T3

3

auto[1]

auto[0]

4022

1

T1

10

T4

8

T6

33