Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.77 99.07 96.67 100.00 100.00 98.83 98.33 91.51


Total test records in report: 919
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T344 /workspace/coverage/default/5.adc_ctrl_fsm_reset.1547231818 Jun 26 06:30:14 PM PDT 24 Jun 26 06:38:18 PM PDT 24 89182220025 ps
T793 /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1662851878 Jun 26 06:30:04 PM PDT 24 Jun 26 06:42:52 PM PDT 24 337242957368 ps
T794 /workspace/coverage/default/28.adc_ctrl_lowpower_counter.2065215441 Jun 26 06:31:10 PM PDT 24 Jun 26 06:31:43 PM PDT 24 26478802233 ps
T795 /workspace/coverage/default/48.adc_ctrl_filters_interrupt.314418278 Jun 26 06:36:39 PM PDT 24 Jun 26 06:42:14 PM PDT 24 486468417596 ps
T56 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3978878707 Jun 26 06:09:49 PM PDT 24 Jun 26 06:09:53 PM PDT 24 2683444918 ps
T57 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.752388117 Jun 26 06:09:52 PM PDT 24 Jun 26 06:10:09 PM PDT 24 4909432663 ps
T796 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2454262202 Jun 26 06:09:40 PM PDT 24 Jun 26 06:09:42 PM PDT 24 483011021 ps
T125 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2486417360 Jun 26 06:09:42 PM PDT 24 Jun 26 06:09:44 PM PDT 24 312560593 ps
T64 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1219154748 Jun 26 06:09:58 PM PDT 24 Jun 26 06:10:01 PM PDT 24 588214778 ps
T797 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.114467225 Jun 26 06:10:05 PM PDT 24 Jun 26 06:10:09 PM PDT 24 450404857 ps
T798 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2602971493 Jun 26 06:10:03 PM PDT 24 Jun 26 06:10:07 PM PDT 24 485535654 ps
T145 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1510421598 Jun 26 06:09:53 PM PDT 24 Jun 26 06:09:56 PM PDT 24 514227756 ps
T65 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3341818589 Jun 26 06:10:03 PM PDT 24 Jun 26 06:10:08 PM PDT 24 1356433134 ps
T799 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1102123700 Jun 26 06:09:46 PM PDT 24 Jun 26 06:09:49 PM PDT 24 375246594 ps
T800 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1497185065 Jun 26 06:10:08 PM PDT 24 Jun 26 06:10:12 PM PDT 24 518745013 ps
T801 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.270828204 Jun 26 06:10:05 PM PDT 24 Jun 26 06:10:09 PM PDT 24 472797379 ps
T58 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.4014342896 Jun 26 06:10:03 PM PDT 24 Jun 26 06:10:46 PM PDT 24 26225956009 ps
T66 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2217537496 Jun 26 06:09:33 PM PDT 24 Jun 26 06:09:36 PM PDT 24 509083706 ps
T79 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2420196649 Jun 26 06:10:07 PM PDT 24 Jun 26 06:10:11 PM PDT 24 457913193 ps
T802 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1524009541 Jun 26 06:10:07 PM PDT 24 Jun 26 06:10:11 PM PDT 24 334768609 ps
T126 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1071195780 Jun 26 06:09:37 PM PDT 24 Jun 26 06:09:39 PM PDT 24 689342595 ps
T141 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.904481313 Jun 26 06:09:48 PM PDT 24 Jun 26 06:09:51 PM PDT 24 534427304 ps
T803 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2102792962 Jun 26 06:10:09 PM PDT 24 Jun 26 06:10:14 PM PDT 24 480418265 ps
T127 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.691193794 Jun 26 06:10:07 PM PDT 24 Jun 26 06:10:12 PM PDT 24 564602093 ps
T804 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.892349866 Jun 26 06:09:54 PM PDT 24 Jun 26 06:09:56 PM PDT 24 309541692 ps
T61 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.592087744 Jun 26 06:09:38 PM PDT 24 Jun 26 06:09:45 PM PDT 24 10089064396 ps
T805 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.372930633 Jun 26 06:10:00 PM PDT 24 Jun 26 06:10:03 PM PDT 24 417080231 ps
T72 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2541784165 Jun 26 06:09:54 PM PDT 24 Jun 26 06:09:57 PM PDT 24 355037298 ps
T142 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3954026736 Jun 26 06:10:06 PM PDT 24 Jun 26 06:10:10 PM PDT 24 305812792 ps
T143 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3132814653 Jun 26 06:10:05 PM PDT 24 Jun 26 06:10:09 PM PDT 24 512834671 ps
T62 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3450593187 Jun 26 06:09:45 PM PDT 24 Jun 26 06:09:51 PM PDT 24 4686493555 ps
T70 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2769243764 Jun 26 06:10:06 PM PDT 24 Jun 26 06:10:10 PM PDT 24 382791797 ps
T78 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.565089852 Jun 26 06:09:52 PM PDT 24 Jun 26 06:09:55 PM PDT 24 461261343 ps
T71 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.970126387 Jun 26 06:09:38 PM PDT 24 Jun 26 06:09:42 PM PDT 24 513066766 ps
T63 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.4223066042 Jun 26 06:09:52 PM PDT 24 Jun 26 06:10:02 PM PDT 24 8582684236 ps
T77 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.4000782873 Jun 26 06:09:48 PM PDT 24 Jun 26 06:10:01 PM PDT 24 4160580593 ps
T73 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1264915870 Jun 26 06:09:54 PM PDT 24 Jun 26 06:09:59 PM PDT 24 386739041 ps
T806 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.4116237055 Jun 26 06:09:44 PM PDT 24 Jun 26 06:09:47 PM PDT 24 372082517 ps
T128 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2839713015 Jun 26 06:09:55 PM PDT 24 Jun 26 06:09:59 PM PDT 24 527870508 ps
T129 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2637287872 Jun 26 06:09:56 PM PDT 24 Jun 26 06:10:01 PM PDT 24 872086170 ps
T144 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.589129543 Jun 26 06:09:55 PM PDT 24 Jun 26 06:10:07 PM PDT 24 4589685987 ps
T807 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.961634425 Jun 26 06:10:02 PM PDT 24 Jun 26 06:10:04 PM PDT 24 363096081 ps
T808 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3307727065 Jun 26 06:09:57 PM PDT 24 Jun 26 06:10:01 PM PDT 24 560620549 ps
T130 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2086636502 Jun 26 06:09:57 PM PDT 24 Jun 26 06:10:00 PM PDT 24 522100408 ps
T809 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2300467413 Jun 26 06:10:03 PM PDT 24 Jun 26 06:10:06 PM PDT 24 446870987 ps
T810 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2863012808 Jun 26 06:09:59 PM PDT 24 Jun 26 06:10:02 PM PDT 24 521229088 ps
T811 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1610801970 Jun 26 06:10:00 PM PDT 24 Jun 26 06:10:04 PM PDT 24 528912152 ps
T812 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2096564145 Jun 26 06:10:07 PM PDT 24 Jun 26 06:10:12 PM PDT 24 318109003 ps
T813 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3351615076 Jun 26 06:10:12 PM PDT 24 Jun 26 06:10:17 PM PDT 24 465581260 ps
T335 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2527938998 Jun 26 06:09:36 PM PDT 24 Jun 26 06:09:41 PM PDT 24 4263122788 ps
T814 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3410228723 Jun 26 06:10:03 PM PDT 24 Jun 26 06:10:06 PM PDT 24 370770667 ps
T815 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1572409476 Jun 26 06:09:52 PM PDT 24 Jun 26 06:09:56 PM PDT 24 492455584 ps
T816 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.942810761 Jun 26 06:10:06 PM PDT 24 Jun 26 06:10:12 PM PDT 24 3887396334 ps
T817 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2224424374 Jun 26 06:09:49 PM PDT 24 Jun 26 06:09:56 PM PDT 24 4538903036 ps
T131 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1565321209 Jun 26 06:09:57 PM PDT 24 Jun 26 06:10:01 PM PDT 24 771649416 ps
T132 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2885605229 Jun 26 06:09:41 PM PDT 24 Jun 26 06:11:31 PM PDT 24 29169057935 ps
T818 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2428835875 Jun 26 06:09:46 PM PDT 24 Jun 26 06:09:54 PM PDT 24 4597591756 ps
T819 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.12384492 Jun 26 06:09:35 PM PDT 24 Jun 26 06:09:38 PM PDT 24 530113495 ps
T820 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2616215299 Jun 26 06:09:52 PM PDT 24 Jun 26 06:09:56 PM PDT 24 503421923 ps
T821 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2046420946 Jun 26 06:09:46 PM PDT 24 Jun 26 06:09:51 PM PDT 24 345596639 ps
T133 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1217170108 Jun 26 06:09:38 PM PDT 24 Jun 26 06:09:40 PM PDT 24 899570767 ps
T822 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3647864698 Jun 26 06:10:04 PM PDT 24 Jun 26 06:10:08 PM PDT 24 770347443 ps
T823 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3618711073 Jun 26 06:10:09 PM PDT 24 Jun 26 06:10:14 PM PDT 24 505132335 ps
T824 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.295287241 Jun 26 06:09:44 PM PDT 24 Jun 26 06:09:47 PM PDT 24 558064719 ps
T825 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1245584674 Jun 26 06:09:50 PM PDT 24 Jun 26 06:09:53 PM PDT 24 419602682 ps
T826 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.9613759 Jun 26 06:10:07 PM PDT 24 Jun 26 06:10:11 PM PDT 24 598170278 ps
T827 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.554670777 Jun 26 06:09:45 PM PDT 24 Jun 26 06:09:54 PM PDT 24 2370658223 ps
T828 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1694068444 Jun 26 06:09:50 PM PDT 24 Jun 26 06:09:58 PM PDT 24 4977621427 ps
T829 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2276024749 Jun 26 06:10:04 PM PDT 24 Jun 26 06:10:07 PM PDT 24 366008730 ps
T830 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3302369376 Jun 26 06:09:55 PM PDT 24 Jun 26 06:09:57 PM PDT 24 393103563 ps
T134 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3330702907 Jun 26 06:09:41 PM PDT 24 Jun 26 06:09:47 PM PDT 24 1115271019 ps
T831 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.24399898 Jun 26 06:09:51 PM PDT 24 Jun 26 06:09:54 PM PDT 24 521550278 ps
T336 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3170963825 Jun 26 06:09:49 PM PDT 24 Jun 26 06:09:55 PM PDT 24 4893391547 ps
T832 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2662753559 Jun 26 06:09:44 PM PDT 24 Jun 26 06:09:52 PM PDT 24 2255798997 ps
T833 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.364260750 Jun 26 06:09:36 PM PDT 24 Jun 26 06:09:48 PM PDT 24 4501423815 ps
T834 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1953871165 Jun 26 06:09:44 PM PDT 24 Jun 26 06:09:58 PM PDT 24 7602741539 ps
T835 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2844974587 Jun 26 06:09:44 PM PDT 24 Jun 26 06:09:57 PM PDT 24 2978939049 ps
T836 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1209580762 Jun 26 06:09:37 PM PDT 24 Jun 26 06:09:42 PM PDT 24 4807926830 ps
T837 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.816885946 Jun 26 06:10:01 PM PDT 24 Jun 26 06:10:07 PM PDT 24 1897127317 ps
T838 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3252393890 Jun 26 06:10:03 PM PDT 24 Jun 26 06:10:13 PM PDT 24 3998794581 ps
T839 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.861788592 Jun 26 06:10:01 PM PDT 24 Jun 26 06:10:05 PM PDT 24 431690546 ps
T840 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3861229676 Jun 26 06:09:42 PM PDT 24 Jun 26 06:09:45 PM PDT 24 778076780 ps
T841 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3940447482 Jun 26 06:09:51 PM PDT 24 Jun 26 06:09:55 PM PDT 24 437187944 ps
T842 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.103917489 Jun 26 06:10:10 PM PDT 24 Jun 26 06:10:15 PM PDT 24 343294129 ps
T843 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.493646786 Jun 26 06:09:58 PM PDT 24 Jun 26 06:10:02 PM PDT 24 529364000 ps
T135 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3381050311 Jun 26 06:09:56 PM PDT 24 Jun 26 06:10:33 PM PDT 24 52345820318 ps
T844 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.842325492 Jun 26 06:09:56 PM PDT 24 Jun 26 06:10:00 PM PDT 24 414460743 ps
T137 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3368878453 Jun 26 06:09:45 PM PDT 24 Jun 26 06:09:48 PM PDT 24 979631840 ps
T845 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3092951835 Jun 26 06:09:38 PM PDT 24 Jun 26 06:09:43 PM PDT 24 2827177715 ps
T846 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3791013321 Jun 26 06:09:47 PM PDT 24 Jun 26 06:09:55 PM PDT 24 539019177 ps
T847 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.4272590172 Jun 26 06:10:06 PM PDT 24 Jun 26 06:10:10 PM PDT 24 436513766 ps
T136 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3815417800 Jun 26 06:09:38 PM PDT 24 Jun 26 06:12:11 PM PDT 24 35467088968 ps
T848 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1819298688 Jun 26 06:10:06 PM PDT 24 Jun 26 06:10:11 PM PDT 24 470143798 ps
T849 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1890950691 Jun 26 06:09:44 PM PDT 24 Jun 26 06:09:49 PM PDT 24 440169065 ps
T850 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2741398847 Jun 26 06:10:02 PM PDT 24 Jun 26 06:10:05 PM PDT 24 535222670 ps
T851 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3687153822 Jun 26 06:10:01 PM PDT 24 Jun 26 06:10:04 PM PDT 24 397361335 ps
T852 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2217342952 Jun 26 06:09:45 PM PDT 24 Jun 26 06:09:48 PM PDT 24 488063851 ps
T853 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3414013486 Jun 26 06:09:45 PM PDT 24 Jun 26 06:09:49 PM PDT 24 522412388 ps
T80 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1326566717 Jun 26 06:10:02 PM PDT 24 Jun 26 06:10:24 PM PDT 24 8178658724 ps
T854 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.548489010 Jun 26 06:09:56 PM PDT 24 Jun 26 06:10:08 PM PDT 24 4104067496 ps
T855 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.751064667 Jun 26 06:10:07 PM PDT 24 Jun 26 06:10:11 PM PDT 24 401756835 ps
T856 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.264235467 Jun 26 06:09:45 PM PDT 24 Jun 26 06:09:48 PM PDT 24 510679080 ps
T857 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.217364238 Jun 26 06:09:39 PM PDT 24 Jun 26 06:09:46 PM PDT 24 2523049001 ps
T858 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1532323570 Jun 26 06:10:06 PM PDT 24 Jun 26 06:10:10 PM PDT 24 522503121 ps
T859 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3340271310 Jun 26 06:10:07 PM PDT 24 Jun 26 06:10:11 PM PDT 24 317228102 ps
T860 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3779900295 Jun 26 06:09:46 PM PDT 24 Jun 26 06:09:50 PM PDT 24 465595256 ps
T861 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2336996720 Jun 26 06:10:06 PM PDT 24 Jun 26 06:10:10 PM PDT 24 459028771 ps
T862 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.4042398024 Jun 26 06:10:04 PM PDT 24 Jun 26 06:10:07 PM PDT 24 347883684 ps
T863 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.942472337 Jun 26 06:09:45 PM PDT 24 Jun 26 06:09:49 PM PDT 24 520830766 ps
T864 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1456534383 Jun 26 06:10:03 PM PDT 24 Jun 26 06:10:15 PM PDT 24 4240000517 ps
T865 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3109987982 Jun 26 06:09:55 PM PDT 24 Jun 26 06:10:18 PM PDT 24 8242488378 ps
T138 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.865732051 Jun 26 06:09:57 PM PDT 24 Jun 26 06:10:01 PM PDT 24 432554095 ps
T866 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1916841340 Jun 26 06:10:01 PM PDT 24 Jun 26 06:10:05 PM PDT 24 463389867 ps
T867 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3998019269 Jun 26 06:10:01 PM PDT 24 Jun 26 06:10:04 PM PDT 24 401638769 ps
T868 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.612335330 Jun 26 06:09:43 PM PDT 24 Jun 26 06:09:47 PM PDT 24 743360267 ps
T869 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.900141818 Jun 26 06:10:07 PM PDT 24 Jun 26 06:10:11 PM PDT 24 445389592 ps
T870 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2329565854 Jun 26 06:09:37 PM PDT 24 Jun 26 06:09:39 PM PDT 24 453377187 ps
T139 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.4217809272 Jun 26 06:09:46 PM PDT 24 Jun 26 06:09:49 PM PDT 24 420357402 ps
T871 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1502321170 Jun 26 06:10:01 PM PDT 24 Jun 26 06:10:03 PM PDT 24 473823054 ps
T872 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.841961799 Jun 26 06:09:44 PM PDT 24 Jun 26 06:09:48 PM PDT 24 856919363 ps
T140 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1447186911 Jun 26 06:09:33 PM PDT 24 Jun 26 06:09:37 PM PDT 24 963410132 ps
T873 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.4215479100 Jun 26 06:10:02 PM PDT 24 Jun 26 06:10:11 PM PDT 24 8022525808 ps
T874 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.110663318 Jun 26 06:09:46 PM PDT 24 Jun 26 06:09:50 PM PDT 24 540402898 ps
T875 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1343922268 Jun 26 06:09:37 PM PDT 24 Jun 26 06:09:44 PM PDT 24 3615343090 ps
T876 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.66281754 Jun 26 06:09:44 PM PDT 24 Jun 26 06:09:48 PM PDT 24 357689703 ps
T877 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2117749702 Jun 26 06:10:06 PM PDT 24 Jun 26 06:10:10 PM PDT 24 545217654 ps
T878 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3545290849 Jun 26 06:10:00 PM PDT 24 Jun 26 06:10:08 PM PDT 24 2250335062 ps
T879 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2462338213 Jun 26 06:09:48 PM PDT 24 Jun 26 06:09:50 PM PDT 24 456226201 ps
T880 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1815116684 Jun 26 06:09:48 PM PDT 24 Jun 26 06:09:52 PM PDT 24 375920443 ps
T881 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1264674366 Jun 26 06:09:46 PM PDT 24 Jun 26 06:09:54 PM PDT 24 2402816158 ps
T882 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3622230470 Jun 26 06:09:48 PM PDT 24 Jun 26 06:09:51 PM PDT 24 374117557 ps
T883 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.4228544481 Jun 26 06:10:06 PM PDT 24 Jun 26 06:10:11 PM PDT 24 488257761 ps
T884 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3924631777 Jun 26 06:09:54 PM PDT 24 Jun 26 06:09:57 PM PDT 24 515635726 ps
T885 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2984618252 Jun 26 06:09:50 PM PDT 24 Jun 26 06:09:52 PM PDT 24 506981267 ps
T81 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.877572257 Jun 26 06:09:52 PM PDT 24 Jun 26 06:10:06 PM PDT 24 8708491929 ps
T886 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1970394060 Jun 26 06:09:58 PM PDT 24 Jun 26 06:10:04 PM PDT 24 715563644 ps
T887 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.469451362 Jun 26 06:10:08 PM PDT 24 Jun 26 06:10:13 PM PDT 24 303999400 ps
T888 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3801198873 Jun 26 06:09:53 PM PDT 24 Jun 26 06:10:02 PM PDT 24 8278278735 ps
T889 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2498076227 Jun 26 06:09:41 PM PDT 24 Jun 26 06:09:44 PM PDT 24 589629541 ps
T890 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3931357269 Jun 26 06:10:08 PM PDT 24 Jun 26 06:10:13 PM PDT 24 444553679 ps
T891 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2006171614 Jun 26 06:10:12 PM PDT 24 Jun 26 06:10:16 PM PDT 24 402145434 ps
T892 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.219355586 Jun 26 06:10:04 PM PDT 24 Jun 26 06:10:08 PM PDT 24 498641900 ps
T893 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.398586158 Jun 26 06:10:08 PM PDT 24 Jun 26 06:10:13 PM PDT 24 355554994 ps
T894 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3488527883 Jun 26 06:09:38 PM PDT 24 Jun 26 06:09:42 PM PDT 24 446648206 ps
T895 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1151151712 Jun 26 06:10:06 PM PDT 24 Jun 26 06:10:11 PM PDT 24 413815815 ps
T896 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3845671783 Jun 26 06:09:56 PM PDT 24 Jun 26 06:10:00 PM PDT 24 484830434 ps
T897 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2393271719 Jun 26 06:09:38 PM PDT 24 Jun 26 06:09:53 PM PDT 24 4445376606 ps
T898 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1645992590 Jun 26 06:09:41 PM PDT 24 Jun 26 06:09:45 PM PDT 24 869314531 ps
T899 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3645790336 Jun 26 06:09:54 PM PDT 24 Jun 26 06:09:57 PM PDT 24 2588389866 ps
T900 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3850595742 Jun 26 06:10:08 PM PDT 24 Jun 26 06:10:13 PM PDT 24 436513191 ps
T901 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1102130016 Jun 26 06:09:51 PM PDT 24 Jun 26 06:10:05 PM PDT 24 4346674638 ps
T902 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2178635357 Jun 26 06:10:05 PM PDT 24 Jun 26 06:10:08 PM PDT 24 370842680 ps
T903 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2046837965 Jun 26 06:09:51 PM PDT 24 Jun 26 06:09:54 PM PDT 24 462450064 ps
T904 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3255015127 Jun 26 06:10:08 PM PDT 24 Jun 26 06:10:13 PM PDT 24 506569648 ps
T905 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3317377630 Jun 26 06:10:04 PM PDT 24 Jun 26 06:10:09 PM PDT 24 558597026 ps
T906 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1020969043 Jun 26 06:09:48 PM PDT 24 Jun 26 06:09:54 PM PDT 24 2758502726 ps
T907 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.535413585 Jun 26 06:09:46 PM PDT 24 Jun 26 06:09:54 PM PDT 24 478538102 ps
T908 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1767569398 Jun 26 06:10:03 PM PDT 24 Jun 26 06:10:05 PM PDT 24 585078295 ps
T909 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2366446932 Jun 26 06:09:44 PM PDT 24 Jun 26 06:09:51 PM PDT 24 2524452919 ps
T910 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2115757195 Jun 26 06:10:02 PM PDT 24 Jun 26 06:10:11 PM PDT 24 8243279729 ps
T911 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2692946568 Jun 26 06:09:49 PM PDT 24 Jun 26 06:09:53 PM PDT 24 447878324 ps
T912 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3763554954 Jun 26 06:10:11 PM PDT 24 Jun 26 06:10:15 PM PDT 24 506769898 ps
T913 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2377665084 Jun 26 06:09:40 PM PDT 24 Jun 26 06:09:44 PM PDT 24 2368158396 ps
T914 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3111936865 Jun 26 06:10:06 PM PDT 24 Jun 26 06:10:10 PM PDT 24 483502444 ps
T915 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3525705134 Jun 26 06:09:51 PM PDT 24 Jun 26 06:09:57 PM PDT 24 4618769160 ps
T916 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2869853746 Jun 26 06:10:04 PM PDT 24 Jun 26 06:10:07 PM PDT 24 438319305 ps
T917 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2201964786 Jun 26 06:09:37 PM PDT 24 Jun 26 06:09:41 PM PDT 24 423782627 ps
T918 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1527395666 Jun 26 06:09:50 PM PDT 24 Jun 26 06:09:53 PM PDT 24 300342131 ps
T919 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3436941283 Jun 26 06:09:37 PM PDT 24 Jun 26 06:09:40 PM PDT 24 423310526 ps

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3882006826
Short name T4
Test name
Test status
Simulation time 354351622893 ps
CPU time 784.34 seconds
Started Jun 26 06:30:10 PM PDT 24
Finished Jun 26 06:43:16 PM PDT 24
Peak memory 201844 kb
Host smart-a49cd823-d9a7-4903-afc0-780e2a0d1b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882006826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3882006826
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.3789399251
Short name T12
Test name
Test status
Simulation time 239471823806 ps
CPU time 779.8 seconds
Started Jun 26 06:36:41 PM PDT 24
Finished Jun 26 06:50:02 PM PDT 24
Peak memory 218540 kb
Host smart-edab10d3-b7a3-4164-9d20-b733992fce8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789399251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.3789399251
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.4022397767
Short name T15
Test name
Test status
Simulation time 185038108135 ps
CPU time 151.82 seconds
Started Jun 26 06:30:53 PM PDT 24
Finished Jun 26 06:33:25 PM PDT 24
Peak memory 210528 kb
Host smart-2d9799cf-3d89-46ed-a4ba-f2a51a6f2be2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022397767 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.4022397767
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.2910313987
Short name T51
Test name
Test status
Simulation time 447894994775 ps
CPU time 1224.91 seconds
Started Jun 26 06:31:09 PM PDT 24
Finished Jun 26 06:51:35 PM PDT 24
Peak memory 202164 kb
Host smart-3a91eff4-b02b-4cef-b35b-b8d0500b5a79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910313987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.2910313987
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1269948249
Short name T11
Test name
Test status
Simulation time 489787293459 ps
CPU time 167.19 seconds
Started Jun 26 06:30:17 PM PDT 24
Finished Jun 26 06:33:07 PM PDT 24
Peak memory 201932 kb
Host smart-ef7f2ab9-ac77-4166-a9bb-85e5a7385df0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269948249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1269948249
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.3606702206
Short name T24
Test name
Test status
Simulation time 532482809826 ps
CPU time 287.63 seconds
Started Jun 26 06:30:51 PM PDT 24
Finished Jun 26 06:35:40 PM PDT 24
Peak memory 201940 kb
Host smart-bd3a75df-e6f1-47a0-9bca-2b88c92ebce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606702206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3606702206
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.800835236
Short name T161
Test name
Test status
Simulation time 511033275711 ps
CPU time 1163.4 seconds
Started Jun 26 06:30:09 PM PDT 24
Finished Jun 26 06:49:33 PM PDT 24
Peak memory 202072 kb
Host smart-b5e29670-e28f-4229-b501-e7233589fdfd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800835236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gatin
g.800835236
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1216316855
Short name T54
Test name
Test status
Simulation time 409642110162 ps
CPU time 443.12 seconds
Started Jun 26 06:31:40 PM PDT 24
Finished Jun 26 06:39:05 PM PDT 24
Peak memory 202244 kb
Host smart-6ebce3f3-f44b-4453-a570-e15039470691
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216316855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1216316855
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.763223369
Short name T46
Test name
Test status
Simulation time 496573775238 ps
CPU time 284.05 seconds
Started Jun 26 06:30:35 PM PDT 24
Finished Jun 26 06:35:23 PM PDT 24
Peak memory 201872 kb
Host smart-2ff18808-3501-4989-b725-df608e0d680c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763223369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati
ng.763223369
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.2655431032
Short name T150
Test name
Test status
Simulation time 569732568513 ps
CPU time 104.1 seconds
Started Jun 26 06:30:26 PM PDT 24
Finished Jun 26 06:32:16 PM PDT 24
Peak memory 201964 kb
Host smart-4518a8a7-3278-4ba1-81a2-781656aa7ca3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655431032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.2655431032
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.3431381547
Short name T230
Test name
Test status
Simulation time 498921045298 ps
CPU time 299.96 seconds
Started Jun 26 06:36:33 PM PDT 24
Finished Jun 26 06:41:47 PM PDT 24
Peak memory 201892 kb
Host smart-e8dc5a92-30d3-4354-8f14-9fb9a5a6ebbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431381547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3431381547
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.2796071268
Short name T224
Test name
Test status
Simulation time 520835272278 ps
CPU time 378.2 seconds
Started Jun 26 06:31:49 PM PDT 24
Finished Jun 26 06:38:08 PM PDT 24
Peak memory 201888 kb
Host smart-493660e9-83f4-4190-a4af-319e1c9f555d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796071268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.2796071268
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.592087744
Short name T61
Test name
Test status
Simulation time 10089064396 ps
CPU time 4.91 seconds
Started Jun 26 06:09:38 PM PDT 24
Finished Jun 26 06:09:45 PM PDT 24
Peak memory 201868 kb
Host smart-02f19c93-5cd1-443e-ab54-dfc59cd8a69c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592087744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_int
g_err.592087744
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.403230512
Short name T6
Test name
Test status
Simulation time 665139618435 ps
CPU time 1452.39 seconds
Started Jun 26 06:31:23 PM PDT 24
Finished Jun 26 06:55:37 PM PDT 24
Peak memory 201892 kb
Host smart-ee865a7b-0360-4bf6-b3bf-54a433f58a81
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403230512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_
wakeup.403230512
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.4109486498
Short name T45
Test name
Test status
Simulation time 487131039410 ps
CPU time 549.23 seconds
Started Jun 26 06:29:44 PM PDT 24
Finished Jun 26 06:38:57 PM PDT 24
Peak memory 201892 kb
Host smart-aa5b72d8-3335-43d7-96d5-1de231a9686d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109486498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.4109486498
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2522218158
Short name T76
Test name
Test status
Simulation time 342542167 ps
CPU time 0.8 seconds
Started Jun 26 06:31:38 PM PDT 24
Finished Jun 26 06:31:40 PM PDT 24
Peak memory 201612 kb
Host smart-52097baf-06e8-48a9-a467-41e9b9c9867e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522218158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2522218158
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2525298005
Short name T214
Test name
Test status
Simulation time 519796511557 ps
CPU time 1067.58 seconds
Started Jun 26 06:30:06 PM PDT 24
Finished Jun 26 06:47:56 PM PDT 24
Peak memory 201980 kb
Host smart-27a1b219-626f-4d88-a311-7222db50f8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525298005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2525298005
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.4014342896
Short name T58
Test name
Test status
Simulation time 26225956009 ps
CPU time 41.27 seconds
Started Jun 26 06:10:03 PM PDT 24
Finished Jun 26 06:10:46 PM PDT 24
Peak memory 201796 kb
Host smart-b1014356-6405-4ffd-ad4a-6bf57657b723
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014342896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.4014342896
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.1773604582
Short name T220
Test name
Test status
Simulation time 505211832140 ps
CPU time 347.5 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:42:39 PM PDT 24
Peak memory 201784 kb
Host smart-dabe377b-27d2-4c5e-9877-514e476673fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773604582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.1773604582
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3341818589
Short name T65
Test name
Test status
Simulation time 1356433134 ps
CPU time 3.11 seconds
Started Jun 26 06:10:03 PM PDT 24
Finished Jun 26 06:10:08 PM PDT 24
Peak memory 217856 kb
Host smart-fcd89dda-90d9-46d4-ba26-5241997aefa3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341818589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3341818589
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.3248971740
Short name T287
Test name
Test status
Simulation time 340014560346 ps
CPU time 390.35 seconds
Started Jun 26 06:30:53 PM PDT 24
Finished Jun 26 06:37:24 PM PDT 24
Peak memory 201892 kb
Host smart-03bb1940-1c87-4d0b-857b-ee8d65f29080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248971740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3248971740
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.1149549776
Short name T233
Test name
Test status
Simulation time 498108672979 ps
CPU time 505.79 seconds
Started Jun 26 06:31:04 PM PDT 24
Finished Jun 26 06:39:31 PM PDT 24
Peak memory 201896 kb
Host smart-5697cfe5-b0b0-469b-aae9-bd2ed7a3cbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149549776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1149549776
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.1064099840
Short name T7
Test name
Test status
Simulation time 257666883061 ps
CPU time 147.14 seconds
Started Jun 26 06:29:52 PM PDT 24
Finished Jun 26 06:32:20 PM PDT 24
Peak memory 201836 kb
Host smart-7990a4e7-1d5e-40f5-9b11-e72336b65dff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064099840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.1064099840
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.971697420
Short name T234
Test name
Test status
Simulation time 164255950728 ps
CPU time 346.64 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:42:38 PM PDT 24
Peak memory 201872 kb
Host smart-ea09fe0e-eaac-404b-b35b-2678a7a2bf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971697420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.971697420
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2601108745
Short name T235
Test name
Test status
Simulation time 332310692578 ps
CPU time 177.51 seconds
Started Jun 26 06:30:26 PM PDT 24
Finished Jun 26 06:33:29 PM PDT 24
Peak memory 201868 kb
Host smart-3511d40e-8850-403a-b00c-52199446f30e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601108745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2601108745
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.735225944
Short name T109
Test name
Test status
Simulation time 510839835762 ps
CPU time 1158.52 seconds
Started Jun 26 06:30:01 PM PDT 24
Finished Jun 26 06:49:22 PM PDT 24
Peak memory 201956 kb
Host smart-e8320d09-f89b-4050-b979-574fb397a34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735225944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.735225944
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1921017007
Short name T182
Test name
Test status
Simulation time 577422697985 ps
CPU time 292.38 seconds
Started Jun 26 06:29:44 PM PDT 24
Finished Jun 26 06:34:40 PM PDT 24
Peak memory 201872 kb
Host smart-1b153529-5175-4831-89d4-f945ae545d2f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921017007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1921017007
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.797284955
Short name T295
Test name
Test status
Simulation time 1319513514647 ps
CPU time 222.94 seconds
Started Jun 26 06:36:59 PM PDT 24
Finished Jun 26 06:41:06 PM PDT 24
Peak memory 212072 kb
Host smart-1c7783fa-ff02-4c3f-b3b6-bdf3a07898fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797284955 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.797284955
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.216794132
Short name T68
Test name
Test status
Simulation time 4127100787 ps
CPU time 10.06 seconds
Started Jun 26 06:29:48 PM PDT 24
Finished Jun 26 06:30:01 PM PDT 24
Peak memory 217076 kb
Host smart-015c005e-8108-46df-90f1-92c584d2d35d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216794132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.216794132
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.848072684
Short name T226
Test name
Test status
Simulation time 557961344132 ps
CPU time 216.68 seconds
Started Jun 26 06:30:08 PM PDT 24
Finished Jun 26 06:33:46 PM PDT 24
Peak memory 201780 kb
Host smart-20674450-2cd9-46cd-bfe0-253da753ebb8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848072684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gatin
g.848072684
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.554260214
Short name T16
Test name
Test status
Simulation time 37404999206 ps
CPU time 87.32 seconds
Started Jun 26 06:36:34 PM PDT 24
Finished Jun 26 06:38:16 PM PDT 24
Peak memory 210136 kb
Host smart-e4c6eb92-c9bf-4b6e-a752-a0201d6c2a40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554260214 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.554260214
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.871791800
Short name T211
Test name
Test status
Simulation time 443511082088 ps
CPU time 1398.57 seconds
Started Jun 26 06:30:07 PM PDT 24
Finished Jun 26 06:53:28 PM PDT 24
Peak memory 210440 kb
Host smart-25a2fb07-75c9-41b0-b163-ac09520355ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871791800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.871791800
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2132953864
Short name T156
Test name
Test status
Simulation time 349759938225 ps
CPU time 835.65 seconds
Started Jun 26 06:36:42 PM PDT 24
Finished Jun 26 06:51:01 PM PDT 24
Peak memory 201848 kb
Host smart-dcab97e2-3af8-429e-b66e-b77a8d1157db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132953864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2132953864
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.1578282980
Short name T246
Test name
Test status
Simulation time 535265540639 ps
CPU time 1301.02 seconds
Started Jun 26 06:30:18 PM PDT 24
Finished Jun 26 06:52:02 PM PDT 24
Peak memory 201880 kb
Host smart-7442b8d5-c124-4b7d-95fb-52e49c15dae4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578282980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.1578282980
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2970361887
Short name T8
Test name
Test status
Simulation time 398297622107 ps
CPU time 650.82 seconds
Started Jun 26 06:31:15 PM PDT 24
Finished Jun 26 06:42:08 PM PDT 24
Peak memory 201920 kb
Host smart-4c492c8e-81af-4369-84bb-de2945df710b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970361887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2970361887
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.3417291923
Short name T217
Test name
Test status
Simulation time 490438066952 ps
CPU time 537.13 seconds
Started Jun 26 06:36:46 PM PDT 24
Finished Jun 26 06:46:09 PM PDT 24
Peak memory 201880 kb
Host smart-b1d19aea-7234-47c7-b8c7-1408b28fbc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417291923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.3417291923
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2046420946
Short name T821
Test name
Test status
Simulation time 345596639 ps
CPU time 2.74 seconds
Started Jun 26 06:09:46 PM PDT 24
Finished Jun 26 06:09:51 PM PDT 24
Peak memory 201668 kb
Host smart-c6d72972-584c-4249-8b56-a7bdd0d35d0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046420946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2046420946
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.1761882505
Short name T175
Test name
Test status
Simulation time 540228705712 ps
CPU time 79.78 seconds
Started Jun 26 06:30:18 PM PDT 24
Finished Jun 26 06:31:41 PM PDT 24
Peak memory 201856 kb
Host smart-426aea5e-064a-4862-84c3-41380a6ef261
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761882505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.1761882505
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.2035630452
Short name T146
Test name
Test status
Simulation time 234811604900 ps
CPU time 503.47 seconds
Started Jun 26 06:30:25 PM PDT 24
Finished Jun 26 06:38:53 PM PDT 24
Peak memory 201868 kb
Host smart-7dfd252f-04a0-4b66-b20f-dbdfffa33715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035630452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2035630452
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.794581685
Short name T292
Test name
Test status
Simulation time 491249732102 ps
CPU time 645.87 seconds
Started Jun 26 06:30:11 PM PDT 24
Finished Jun 26 06:40:58 PM PDT 24
Peak memory 201928 kb
Host smart-f92214ff-2678-4cfa-9e72-3c436b72e9a8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794581685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gatin
g.794581685
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2825983048
Short name T253
Test name
Test status
Simulation time 336242634860 ps
CPU time 854.74 seconds
Started Jun 26 06:36:20 PM PDT 24
Finished Jun 26 06:50:37 PM PDT 24
Peak memory 201860 kb
Host smart-44324541-fddb-4811-a100-1353f9062f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825983048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2825983048
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.3568393704
Short name T259
Test name
Test status
Simulation time 513023551233 ps
CPU time 564.15 seconds
Started Jun 26 06:30:33 PM PDT 24
Finished Jun 26 06:40:02 PM PDT 24
Peak memory 201924 kb
Host smart-4ebb4e78-10a0-40c6-ae73-3ac18f732ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568393704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.3568393704
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.1766049275
Short name T170
Test name
Test status
Simulation time 328386963888 ps
CPU time 196.59 seconds
Started Jun 26 06:30:01 PM PDT 24
Finished Jun 26 06:33:19 PM PDT 24
Peak memory 201888 kb
Host smart-7c193574-c092-49e5-ae81-a53bccd01b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766049275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.1766049275
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3831936949
Short name T232
Test name
Test status
Simulation time 340128320165 ps
CPU time 759.57 seconds
Started Jun 26 06:30:05 PM PDT 24
Finished Jun 26 06:42:47 PM PDT 24
Peak memory 201952 kb
Host smart-e84d6660-1e2f-4562-8bba-9ca73f6a0eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831936949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3831936949
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.2398343992
Short name T167
Test name
Test status
Simulation time 543340210561 ps
CPU time 250.18 seconds
Started Jun 26 06:36:43 PM PDT 24
Finished Jun 26 06:41:18 PM PDT 24
Peak memory 201896 kb
Host smart-5b42ebdc-9d83-49ae-bf81-c11f8b390a82
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398343992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.2398343992
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2486417360
Short name T125
Test name
Test status
Simulation time 312560593 ps
CPU time 1.06 seconds
Started Jun 26 06:09:42 PM PDT 24
Finished Jun 26 06:09:44 PM PDT 24
Peak memory 201496 kb
Host smart-e3c0993a-3963-4553-bfd8-a3ec212cf32a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486417360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2486417360
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.3145763315
Short name T187
Test name
Test status
Simulation time 370600643825 ps
CPU time 53.25 seconds
Started Jun 26 06:30:34 PM PDT 24
Finished Jun 26 06:31:31 PM PDT 24
Peak memory 201820 kb
Host smart-e5c2bbae-936c-4680-9e54-1f22d016f62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145763315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3145763315
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.2258318333
Short name T155
Test name
Test status
Simulation time 329337647180 ps
CPU time 145.83 seconds
Started Jun 26 06:31:15 PM PDT 24
Finished Jun 26 06:33:42 PM PDT 24
Peak memory 201908 kb
Host smart-3fa8bd64-0f0f-4d0c-bdb4-46213abb7772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258318333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.2258318333
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3421651140
Short name T273
Test name
Test status
Simulation time 213367739585 ps
CPU time 206.47 seconds
Started Jun 26 06:31:22 PM PDT 24
Finished Jun 26 06:34:50 PM PDT 24
Peak memory 210596 kb
Host smart-29337bd5-3330-4337-9699-9112b52c10bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421651140 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.3421651140
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.2918277248
Short name T265
Test name
Test status
Simulation time 504084896337 ps
CPU time 327.22 seconds
Started Jun 26 06:31:39 PM PDT 24
Finished Jun 26 06:37:07 PM PDT 24
Peak memory 201864 kb
Host smart-a57abd53-e147-43fa-ace7-abadd36c6d7a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918277248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.2918277248
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.467358492
Short name T333
Test name
Test status
Simulation time 232005570754 ps
CPU time 500.84 seconds
Started Jun 26 06:30:21 PM PDT 24
Finished Jun 26 06:38:45 PM PDT 24
Peak memory 201876 kb
Host smart-4d1299cd-621b-470b-bdb8-95ebe911b831
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467358492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.
467358492
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.1258093304
Short name T231
Test name
Test status
Simulation time 522758387974 ps
CPU time 299.64 seconds
Started Jun 26 06:30:29 PM PDT 24
Finished Jun 26 06:35:34 PM PDT 24
Peak memory 201924 kb
Host smart-53b03aa7-9d3d-4d11-be99-0c15136ade78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258093304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1258093304
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3952827480
Short name T290
Test name
Test status
Simulation time 163844507543 ps
CPU time 331.45 seconds
Started Jun 26 06:30:19 PM PDT 24
Finished Jun 26 06:35:55 PM PDT 24
Peak memory 201920 kb
Host smart-b1ebae41-3115-497e-880c-25498933f6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952827480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3952827480
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3979870941
Short name T252
Test name
Test status
Simulation time 464830479901 ps
CPU time 172.7 seconds
Started Jun 26 06:30:30 PM PDT 24
Finished Jun 26 06:33:27 PM PDT 24
Peak memory 210132 kb
Host smart-dd68cb32-9d27-42fe-a7c6-7a978f92f17c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979870941 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.3979870941
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3733806883
Short name T247
Test name
Test status
Simulation time 531329688779 ps
CPU time 1129.04 seconds
Started Jun 26 06:30:05 PM PDT 24
Finished Jun 26 06:48:57 PM PDT 24
Peak memory 201908 kb
Host smart-27b2206a-eaee-4fb6-9b1b-7e7206c663fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733806883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3733806883
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.1261447522
Short name T500
Test name
Test status
Simulation time 132796651899 ps
CPU time 653.43 seconds
Started Jun 26 06:30:02 PM PDT 24
Finished Jun 26 06:40:57 PM PDT 24
Peak memory 202260 kb
Host smart-ffca05cc-b9fe-44e2-89ef-8527629e69ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261447522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1261447522
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2527938998
Short name T335
Test name
Test status
Simulation time 4263122788 ps
CPU time 4.17 seconds
Started Jun 26 06:09:36 PM PDT 24
Finished Jun 26 06:09:41 PM PDT 24
Peak memory 201836 kb
Host smart-88fb06d0-195b-4499-b84e-26ae9ecf9e3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527938998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2527938998
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2546723531
Short name T91
Test name
Test status
Simulation time 159422587868 ps
CPU time 97.45 seconds
Started Jun 26 06:30:03 PM PDT 24
Finished Jun 26 06:31:43 PM PDT 24
Peak memory 201772 kb
Host smart-a5565893-e253-4369-8322-cb8c6d3aedc5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546723531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2546723531
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.618274113
Short name T294
Test name
Test status
Simulation time 389228234227 ps
CPU time 390.48 seconds
Started Jun 26 06:30:02 PM PDT 24
Finished Jun 26 06:36:34 PM PDT 24
Peak memory 201884 kb
Host smart-e9096b6b-ece7-47df-be9e-6add39f778b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618274113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.618274113
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.1089740620
Short name T164
Test name
Test status
Simulation time 329516137588 ps
CPU time 741.62 seconds
Started Jun 26 06:30:48 PM PDT 24
Finished Jun 26 06:43:11 PM PDT 24
Peak memory 201924 kb
Host smart-6745ec04-f631-424b-9dda-e1d276ed25c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089740620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.1089740620
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2790593048
Short name T281
Test name
Test status
Simulation time 187346099589 ps
CPU time 391.72 seconds
Started Jun 26 06:30:43 PM PDT 24
Finished Jun 26 06:37:16 PM PDT 24
Peak memory 201832 kb
Host smart-fdaa2ba4-e8bd-40b1-859a-7090f5f0b7e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790593048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2790593048
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3539702413
Short name T291
Test name
Test status
Simulation time 375799171371 ps
CPU time 218.88 seconds
Started Jun 26 06:31:21 PM PDT 24
Finished Jun 26 06:35:01 PM PDT 24
Peak memory 201888 kb
Host smart-5c63253d-6345-491e-a5b4-defb4bbfb63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539702413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3539702413
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.3415143223
Short name T300
Test name
Test status
Simulation time 499877122484 ps
CPU time 583.76 seconds
Started Jun 26 06:30:04 PM PDT 24
Finished Jun 26 06:39:50 PM PDT 24
Peak memory 201872 kb
Host smart-5e98fe66-a05d-46b6-8ed4-94c1a8db5a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415143223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.3415143223
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2715372367
Short name T236
Test name
Test status
Simulation time 350108340261 ps
CPU time 791 seconds
Started Jun 26 06:30:04 PM PDT 24
Finished Jun 26 06:43:17 PM PDT 24
Peak memory 201904 kb
Host smart-a0837b30-a3f5-458f-b822-733f809afabf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715372367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2715372367
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2163873748
Short name T266
Test name
Test status
Simulation time 163097608756 ps
CPU time 390.11 seconds
Started Jun 26 06:30:14 PM PDT 24
Finished Jun 26 06:36:46 PM PDT 24
Peak memory 201860 kb
Host smart-065ad5af-3adb-41f1-a242-e0d30e9b400b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163873748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2163873748
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.4037035773
Short name T53
Test name
Test status
Simulation time 129427497014 ps
CPU time 491.15 seconds
Started Jun 26 06:30:16 PM PDT 24
Finished Jun 26 06:38:31 PM PDT 24
Peak memory 202248 kb
Host smart-81b335ad-aef6-4fbc-bb12-95cd2d2e9e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037035773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.4037035773
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.427740852
Short name T741
Test name
Test status
Simulation time 129284615893 ps
CPU time 457.32 seconds
Started Jun 26 06:30:38 PM PDT 24
Finished Jun 26 06:38:18 PM PDT 24
Peak memory 202204 kb
Host smart-304ce710-e0df-432f-b36f-59d511f16bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427740852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.427740852
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2073911329
Short name T342
Test name
Test status
Simulation time 107680860194 ps
CPU time 626.05 seconds
Started Jun 26 06:30:42 PM PDT 24
Finished Jun 26 06:41:09 PM PDT 24
Peak memory 202272 kb
Host smart-fc1eea36-1226-4e29-8f6a-da32bf7cc640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073911329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2073911329
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2154020932
Short name T310
Test name
Test status
Simulation time 489508773148 ps
CPU time 1038.07 seconds
Started Jun 26 06:31:39 PM PDT 24
Finished Jun 26 06:48:58 PM PDT 24
Peak memory 201960 kb
Host smart-2b243ef8-e592-4ecb-811d-d001b0b84ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154020932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2154020932
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.4276628116
Short name T158
Test name
Test status
Simulation time 503792635087 ps
CPU time 242.1 seconds
Started Jun 26 06:29:47 PM PDT 24
Finished Jun 26 06:33:53 PM PDT 24
Peak memory 201932 kb
Host smart-ef9e8e7a-c3c3-4c62-b0aa-d2c5391d29b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276628116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.4276628116
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2382522059
Short name T20
Test name
Test status
Simulation time 44273588471 ps
CPU time 50.56 seconds
Started Jun 26 06:30:20 PM PDT 24
Finished Jun 26 06:31:21 PM PDT 24
Peak memory 210220 kb
Host smart-22fbf260-de12-409f-88d6-a1ed16bdd864
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382522059 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2382522059
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2815083730
Short name T337
Test name
Test status
Simulation time 98634722235 ps
CPU time 120.4 seconds
Started Jun 26 06:30:23 PM PDT 24
Finished Jun 26 06:32:33 PM PDT 24
Peak memory 210448 kb
Host smart-6595b5a1-73e4-41de-9bd9-bfa9e01a77d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815083730 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.2815083730
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.3867525251
Short name T249
Test name
Test status
Simulation time 164766653486 ps
CPU time 399.46 seconds
Started Jun 26 06:30:25 PM PDT 24
Finished Jun 26 06:37:09 PM PDT 24
Peak memory 201888 kb
Host smart-bf5e4a17-32b6-4670-b7e9-d554b35534c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867525251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.3867525251
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.769199541
Short name T209
Test name
Test status
Simulation time 120680262690 ps
CPU time 338.08 seconds
Started Jun 26 06:30:25 PM PDT 24
Finished Jun 26 06:36:08 PM PDT 24
Peak memory 210560 kb
Host smart-79043a62-4032-48ce-9f58-ca3c4bc8b88e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769199541 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.769199541
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.1338837238
Short name T316
Test name
Test status
Simulation time 508350362804 ps
CPU time 1142.04 seconds
Started Jun 26 06:30:42 PM PDT 24
Finished Jun 26 06:49:45 PM PDT 24
Peak memory 201920 kb
Host smart-3cf32a56-ca41-4314-91d3-2f96cbe2163b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338837238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.1338837238
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.3132612573
Short name T32
Test name
Test status
Simulation time 337998415675 ps
CPU time 204.56 seconds
Started Jun 26 06:30:48 PM PDT 24
Finished Jun 26 06:34:14 PM PDT 24
Peak memory 201868 kb
Host smart-fbdb3319-6ceb-4841-acbf-4abb6677f7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132612573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.3132612573
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.2023088183
Short name T225
Test name
Test status
Simulation time 365466203813 ps
CPU time 901.42 seconds
Started Jun 26 06:31:22 PM PDT 24
Finished Jun 26 06:46:24 PM PDT 24
Peak memory 201940 kb
Host smart-f8fd2a25-6813-4dc8-a2dd-b34458577357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023088183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.2023088183
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.1727717331
Short name T307
Test name
Test status
Simulation time 489462363451 ps
CPU time 311.89 seconds
Started Jun 26 06:31:38 PM PDT 24
Finished Jun 26 06:36:51 PM PDT 24
Peak memory 201960 kb
Host smart-33ec4a18-9975-48a3-84ef-ca3f8093ae4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727717331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.1727717331
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1527609656
Short name T311
Test name
Test status
Simulation time 93192383315 ps
CPU time 49.6 seconds
Started Jun 26 06:36:29 PM PDT 24
Finished Jun 26 06:37:20 PM PDT 24
Peak memory 210224 kb
Host smart-d4090407-4054-4e8c-aecd-61c9b5567265
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527609656 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.1527609656
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3587276349
Short name T48
Test name
Test status
Simulation time 175397566173 ps
CPU time 475.92 seconds
Started Jun 26 06:30:03 PM PDT 24
Finished Jun 26 06:38:01 PM PDT 24
Peak memory 210584 kb
Host smart-94d4ba81-0e45-4743-8342-d4ce1151fb7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587276349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3587276349
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3811219148
Short name T210
Test name
Test status
Simulation time 102364664506 ps
CPU time 294.56 seconds
Started Jun 26 06:30:09 PM PDT 24
Finished Jun 26 06:35:05 PM PDT 24
Peak memory 202192 kb
Host smart-db9ee37b-d8b8-4f23-8ca2-15a7b522f4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811219148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3811219148
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2301419999
Short name T306
Test name
Test status
Simulation time 532029422991 ps
CPU time 1254.31 seconds
Started Jun 26 06:30:04 PM PDT 24
Finished Jun 26 06:51:01 PM PDT 24
Peak memory 201940 kb
Host smart-67c3e826-b2f8-4b01-b642-ca728d4a2a3c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301419999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2301419999
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1645992590
Short name T898
Test name
Test status
Simulation time 869314531 ps
CPU time 2.18 seconds
Started Jun 26 06:09:41 PM PDT 24
Finished Jun 26 06:09:45 PM PDT 24
Peak memory 201736 kb
Host smart-dd3879a3-643b-459d-bdc2-0575b786b153
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645992590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1645992590
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2885605229
Short name T132
Test name
Test status
Simulation time 29169057935 ps
CPU time 108.53 seconds
Started Jun 26 06:09:41 PM PDT 24
Finished Jun 26 06:11:31 PM PDT 24
Peak memory 201808 kb
Host smart-ed29b9c5-d275-4da3-aa63-35581bf9ed98
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885605229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.2885605229
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.612335330
Short name T868
Test name
Test status
Simulation time 743360267 ps
CPU time 2.5 seconds
Started Jun 26 06:09:43 PM PDT 24
Finished Jun 26 06:09:47 PM PDT 24
Peak memory 201524 kb
Host smart-8debbd4c-2f3e-4a37-a61f-b7785ba15da9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612335330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_re
set.612335330
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.535413585
Short name T907
Test name
Test status
Simulation time 478538102 ps
CPU time 1.45 seconds
Started Jun 26 06:09:46 PM PDT 24
Finished Jun 26 06:09:54 PM PDT 24
Peak memory 201584 kb
Host smart-15df25aa-ed44-439f-bd07-ab14ba3ae707
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535413585 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.535413585
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3436941283
Short name T919
Test name
Test status
Simulation time 423310526 ps
CPU time 1.63 seconds
Started Jun 26 06:09:37 PM PDT 24
Finished Jun 26 06:09:40 PM PDT 24
Peak memory 200572 kb
Host smart-47e14610-a26a-489e-b7a8-3c8d92c44978
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436941283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.3436941283
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1343922268
Short name T875
Test name
Test status
Simulation time 3615343090 ps
CPU time 5.33 seconds
Started Jun 26 06:09:37 PM PDT 24
Finished Jun 26 06:09:44 PM PDT 24
Peak memory 201800 kb
Host smart-7bfa2747-a1a4-4f61-826e-8aab85684196
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343922268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.1343922268
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.12384492
Short name T819
Test name
Test status
Simulation time 530113495 ps
CPU time 1.54 seconds
Started Jun 26 06:09:35 PM PDT 24
Finished Jun 26 06:09:38 PM PDT 24
Peak memory 201780 kb
Host smart-db37896f-606b-4ea1-a940-55964ade1f86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12384492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.12384492
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.364260750
Short name T833
Test name
Test status
Simulation time 4501423815 ps
CPU time 11.03 seconds
Started Jun 26 06:09:36 PM PDT 24
Finished Jun 26 06:09:48 PM PDT 24
Peak memory 201840 kb
Host smart-a8003844-f9ec-4703-8ef3-6c17635aea6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364260750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.364260750
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3861229676
Short name T840
Test name
Test status
Simulation time 778076780 ps
CPU time 2.69 seconds
Started Jun 26 06:09:42 PM PDT 24
Finished Jun 26 06:09:45 PM PDT 24
Peak memory 201684 kb
Host smart-a8bfbbf5-5d0a-4726-aa2b-91c3e655f1de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861229676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3861229676
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3815417800
Short name T136
Test name
Test status
Simulation time 35467088968 ps
CPU time 151.76 seconds
Started Jun 26 06:09:38 PM PDT 24
Finished Jun 26 06:12:11 PM PDT 24
Peak memory 201868 kb
Host smart-57c1da7b-0c42-43c0-a217-87abeedd772d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815417800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.3815417800
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1071195780
Short name T126
Test name
Test status
Simulation time 689342595 ps
CPU time 0.9 seconds
Started Jun 26 06:09:37 PM PDT 24
Finished Jun 26 06:09:39 PM PDT 24
Peak memory 201488 kb
Host smart-fa0d674a-c336-47d6-865c-2b06a71da179
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071195780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.1071195780
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2217537496
Short name T66
Test name
Test status
Simulation time 509083706 ps
CPU time 1.91 seconds
Started Jun 26 06:09:33 PM PDT 24
Finished Jun 26 06:09:36 PM PDT 24
Peak memory 201528 kb
Host smart-dfe71d78-964d-41de-b9e7-00a7c06e5f1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217537496 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.2217537496
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3488527883
Short name T894
Test name
Test status
Simulation time 446648206 ps
CPU time 1.82 seconds
Started Jun 26 06:09:38 PM PDT 24
Finished Jun 26 06:09:42 PM PDT 24
Peak memory 201500 kb
Host smart-1ef7456c-d409-4f10-a726-7b9d8b58bc40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488527883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.3488527883
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1102123700
Short name T799
Test name
Test status
Simulation time 375246594 ps
CPU time 1.42 seconds
Started Jun 26 06:09:46 PM PDT 24
Finished Jun 26 06:09:49 PM PDT 24
Peak memory 201452 kb
Host smart-ad0c3d59-b885-418e-8542-966cb1a0e813
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102123700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1102123700
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1209580762
Short name T836
Test name
Test status
Simulation time 4807926830 ps
CPU time 3.75 seconds
Started Jun 26 06:09:37 PM PDT 24
Finished Jun 26 06:09:42 PM PDT 24
Peak memory 201800 kb
Host smart-a72a90f8-bfc8-4bbc-8635-d7f432eda808
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209580762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.1209580762
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2201964786
Short name T917
Test name
Test status
Simulation time 423782627 ps
CPU time 3.11 seconds
Started Jun 26 06:09:37 PM PDT 24
Finished Jun 26 06:09:41 PM PDT 24
Peak memory 201796 kb
Host smart-f3b97a6e-2773-4009-82b7-90654a2d9b8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201964786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2201964786
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2692946568
Short name T911
Test name
Test status
Simulation time 447878324 ps
CPU time 1.94 seconds
Started Jun 26 06:09:49 PM PDT 24
Finished Jun 26 06:09:53 PM PDT 24
Peak memory 201512 kb
Host smart-09c7de5e-64c6-40c7-8515-ab00b0bcf9d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692946568 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.2692946568
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.295287241
Short name T824
Test name
Test status
Simulation time 558064719 ps
CPU time 1.06 seconds
Started Jun 26 06:09:44 PM PDT 24
Finished Jun 26 06:09:47 PM PDT 24
Peak memory 201528 kb
Host smart-e1d29048-f54c-49d7-8d31-99b5b26ca414
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295287241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.295287241
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.4116237055
Short name T806
Test name
Test status
Simulation time 372082517 ps
CPU time 0.84 seconds
Started Jun 26 06:09:44 PM PDT 24
Finished Jun 26 06:09:47 PM PDT 24
Peak memory 201456 kb
Host smart-3bba3b22-b5b4-4785-b51a-189fa139880e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116237055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.4116237055
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.554670777
Short name T827
Test name
Test status
Simulation time 2370658223 ps
CPU time 2.17 seconds
Started Jun 26 06:09:45 PM PDT 24
Finished Jun 26 06:09:54 PM PDT 24
Peak memory 201644 kb
Host smart-2719a966-76b6-4f51-a9ed-6252024269c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554670777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.554670777
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3779900295
Short name T860
Test name
Test status
Simulation time 465595256 ps
CPU time 1.67 seconds
Started Jun 26 06:09:46 PM PDT 24
Finished Jun 26 06:09:50 PM PDT 24
Peak memory 201768 kb
Host smart-e826bf9c-d258-44d6-9729-efa5b3303297
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779900295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.3779900295
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.4223066042
Short name T63
Test name
Test status
Simulation time 8582684236 ps
CPU time 7.9 seconds
Started Jun 26 06:09:52 PM PDT 24
Finished Jun 26 06:10:02 PM PDT 24
Peak memory 201876 kb
Host smart-68b8d577-4cff-419d-a9c3-7860e69c6a3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223066042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.4223066042
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2046837965
Short name T903
Test name
Test status
Simulation time 462450064 ps
CPU time 2.04 seconds
Started Jun 26 06:09:51 PM PDT 24
Finished Jun 26 06:09:54 PM PDT 24
Peak memory 201596 kb
Host smart-2795e840-34c5-4d67-993c-baf41a303368
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046837965 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2046837965
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.264235467
Short name T856
Test name
Test status
Simulation time 510679080 ps
CPU time 1.48 seconds
Started Jun 26 06:09:45 PM PDT 24
Finished Jun 26 06:09:48 PM PDT 24
Peak memory 201520 kb
Host smart-ae29ee61-2477-4f54-a5c4-6d5f724f0038
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264235467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.264235467
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1610801970
Short name T811
Test name
Test status
Simulation time 528912152 ps
CPU time 1.85 seconds
Started Jun 26 06:10:00 PM PDT 24
Finished Jun 26 06:10:04 PM PDT 24
Peak memory 201412 kb
Host smart-c6f2b076-4d53-41bb-a71a-5b6307980e33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610801970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.1610801970
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1264674366
Short name T881
Test name
Test status
Simulation time 2402816158 ps
CPU time 5.93 seconds
Started Jun 26 06:09:46 PM PDT 24
Finished Jun 26 06:09:54 PM PDT 24
Peak memory 201624 kb
Host smart-62c916c6-039e-453e-8a36-236da2b52094
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264674366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.1264674366
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3252393890
Short name T838
Test name
Test status
Simulation time 3998794581 ps
CPU time 7.45 seconds
Started Jun 26 06:10:03 PM PDT 24
Finished Jun 26 06:10:13 PM PDT 24
Peak memory 201848 kb
Host smart-9da5ede7-8c94-44ee-b36d-b99ea8f2125f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252393890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.3252393890
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1572409476
Short name T815
Test name
Test status
Simulation time 492455584 ps
CPU time 2.19 seconds
Started Jun 26 06:09:52 PM PDT 24
Finished Jun 26 06:09:56 PM PDT 24
Peak memory 201600 kb
Host smart-a3cecc0b-8fdc-445b-8684-0e7f94e517d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572409476 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.1572409476
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2984618252
Short name T885
Test name
Test status
Simulation time 506981267 ps
CPU time 1.02 seconds
Started Jun 26 06:09:50 PM PDT 24
Finished Jun 26 06:09:52 PM PDT 24
Peak memory 201520 kb
Host smart-cdc65917-48a6-4e18-8659-af8a7de8aa2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984618252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.2984618252
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.372930633
Short name T805
Test name
Test status
Simulation time 417080231 ps
CPU time 1.62 seconds
Started Jun 26 06:10:00 PM PDT 24
Finished Jun 26 06:10:03 PM PDT 24
Peak memory 201440 kb
Host smart-39600886-a0da-44c9-8c82-ecb24d134a74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372930633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.372930633
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2844974587
Short name T835
Test name
Test status
Simulation time 2978939049 ps
CPU time 11.76 seconds
Started Jun 26 06:09:44 PM PDT 24
Finished Jun 26 06:09:57 PM PDT 24
Peak memory 201600 kb
Host smart-0f42316a-126e-4f28-b330-9863bf2baefc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844974587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.2844974587
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.66281754
Short name T876
Test name
Test status
Simulation time 357689703 ps
CPU time 1.53 seconds
Started Jun 26 06:09:44 PM PDT 24
Finished Jun 26 06:09:48 PM PDT 24
Peak memory 201784 kb
Host smart-3c7179af-d9e6-4252-93e8-8a4c921465b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66281754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.66281754
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1102130016
Short name T901
Test name
Test status
Simulation time 4346674638 ps
CPU time 11.78 seconds
Started Jun 26 06:09:51 PM PDT 24
Finished Jun 26 06:10:05 PM PDT 24
Peak memory 201892 kb
Host smart-0ff30e3e-06b9-4f04-8da2-71a16247dd49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102130016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1102130016
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.110663318
Short name T874
Test name
Test status
Simulation time 540402898 ps
CPU time 1.14 seconds
Started Jun 26 06:09:46 PM PDT 24
Finished Jun 26 06:09:50 PM PDT 24
Peak memory 201516 kb
Host smart-9e627485-a1e0-4005-b6ca-c32a89337b42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110663318 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.110663318
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2086636502
Short name T130
Test name
Test status
Simulation time 522100408 ps
CPU time 0.9 seconds
Started Jun 26 06:09:57 PM PDT 24
Finished Jun 26 06:10:00 PM PDT 24
Peak memory 201540 kb
Host smart-4a9a682a-10ab-4104-94f2-8ac4a8a56286
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086636502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.2086636502
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3622230470
Short name T882
Test name
Test status
Simulation time 374117557 ps
CPU time 1.03 seconds
Started Jun 26 06:09:48 PM PDT 24
Finished Jun 26 06:09:51 PM PDT 24
Peak memory 201440 kb
Host smart-724df0d1-cf98-49ea-b9ad-5f4bf5e3c14e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622230470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3622230470
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3645790336
Short name T899
Test name
Test status
Simulation time 2588389866 ps
CPU time 1.95 seconds
Started Jun 26 06:09:54 PM PDT 24
Finished Jun 26 06:09:57 PM PDT 24
Peak memory 201664 kb
Host smart-45e1080b-c4f5-412e-afe3-3c973023974f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645790336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.3645790336
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1970394060
Short name T886
Test name
Test status
Simulation time 715563644 ps
CPU time 3.36 seconds
Started Jun 26 06:09:58 PM PDT 24
Finished Jun 26 06:10:04 PM PDT 24
Peak memory 201744 kb
Host smart-8fac8c5e-5716-4ba3-96ac-310b3b8ec517
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970394060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1970394060
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3450593187
Short name T62
Test name
Test status
Simulation time 4686493555 ps
CPU time 4.4 seconds
Started Jun 26 06:09:45 PM PDT 24
Finished Jun 26 06:09:51 PM PDT 24
Peak memory 201828 kb
Host smart-f2a7cea9-8c2e-4001-9a8e-5ea34423638c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450593187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3450593187
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3845671783
Short name T896
Test name
Test status
Simulation time 484830434 ps
CPU time 1.5 seconds
Started Jun 26 06:09:56 PM PDT 24
Finished Jun 26 06:10:00 PM PDT 24
Peak memory 201600 kb
Host smart-ff69f7e8-e264-4f81-803b-35ecfeba6946
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845671783 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3845671783
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1151151712
Short name T895
Test name
Test status
Simulation time 413815815 ps
CPU time 1.68 seconds
Started Jun 26 06:10:06 PM PDT 24
Finished Jun 26 06:10:11 PM PDT 24
Peak memory 201524 kb
Host smart-b0866315-b847-4378-9300-269f4da1086a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151151712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1151151712
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3924631777
Short name T884
Test name
Test status
Simulation time 515635726 ps
CPU time 1.89 seconds
Started Jun 26 06:09:54 PM PDT 24
Finished Jun 26 06:09:57 PM PDT 24
Peak memory 201468 kb
Host smart-947b7560-2586-494d-8d88-c2a68e4d814d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924631777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3924631777
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.752388117
Short name T57
Test name
Test status
Simulation time 4909432663 ps
CPU time 16.08 seconds
Started Jun 26 06:09:52 PM PDT 24
Finished Jun 26 06:10:09 PM PDT 24
Peak memory 201812 kb
Host smart-9c76eb9c-3916-4936-b079-edc91c433658
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752388117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_c
trl_same_csr_outstanding.752388117
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.24399898
Short name T831
Test name
Test status
Simulation time 521550278 ps
CPU time 1.56 seconds
Started Jun 26 06:09:51 PM PDT 24
Finished Jun 26 06:09:54 PM PDT 24
Peak memory 201804 kb
Host smart-04159ca3-8753-4800-bfaf-0831c34e4e4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24399898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.24399898
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1456534383
Short name T864
Test name
Test status
Simulation time 4240000517 ps
CPU time 9.74 seconds
Started Jun 26 06:10:03 PM PDT 24
Finished Jun 26 06:10:15 PM PDT 24
Peak memory 201868 kb
Host smart-d2f44f0a-e358-4a75-b142-ffee352429ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456534383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.1456534383
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3998019269
Short name T867
Test name
Test status
Simulation time 401638769 ps
CPU time 1.31 seconds
Started Jun 26 06:10:01 PM PDT 24
Finished Jun 26 06:10:04 PM PDT 24
Peak memory 201600 kb
Host smart-e4e7fb75-f42c-460d-8cc2-a3b5c0ac0280
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998019269 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3998019269
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.4217809272
Short name T139
Test name
Test status
Simulation time 420357402 ps
CPU time 0.97 seconds
Started Jun 26 06:09:46 PM PDT 24
Finished Jun 26 06:09:49 PM PDT 24
Peak memory 201528 kb
Host smart-0ded4d3c-688a-4efc-bc77-d7dab19a60fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217809272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.4217809272
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.493646786
Short name T843
Test name
Test status
Simulation time 529364000 ps
CPU time 1.92 seconds
Started Jun 26 06:09:58 PM PDT 24
Finished Jun 26 06:10:02 PM PDT 24
Peak memory 201456 kb
Host smart-ff163502-3027-4015-a6eb-edd5507c2be7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493646786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.493646786
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1694068444
Short name T828
Test name
Test status
Simulation time 4977621427 ps
CPU time 6.52 seconds
Started Jun 26 06:09:50 PM PDT 24
Finished Jun 26 06:09:58 PM PDT 24
Peak memory 201840 kb
Host smart-eacdeb87-25d9-41d5-8c82-63701a3d3183
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694068444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1694068444
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1815116684
Short name T880
Test name
Test status
Simulation time 375920443 ps
CPU time 2.36 seconds
Started Jun 26 06:09:48 PM PDT 24
Finished Jun 26 06:09:52 PM PDT 24
Peak memory 201800 kb
Host smart-f9291bca-7de1-4ab9-8334-32607e218b48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815116684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1815116684
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.4000782873
Short name T77
Test name
Test status
Simulation time 4160580593 ps
CPU time 11.51 seconds
Started Jun 26 06:09:48 PM PDT 24
Finished Jun 26 06:10:01 PM PDT 24
Peak memory 201836 kb
Host smart-a780e704-63a4-4a64-a2f1-b8b234b39f72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000782873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.4000782873
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.103917489
Short name T842
Test name
Test status
Simulation time 343294129 ps
CPU time 1.28 seconds
Started Jun 26 06:10:10 PM PDT 24
Finished Jun 26 06:10:15 PM PDT 24
Peak memory 201552 kb
Host smart-2951e49c-cd65-4329-8abb-17babe5b2f18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103917489 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.103917489
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1510421598
Short name T145
Test name
Test status
Simulation time 514227756 ps
CPU time 1.79 seconds
Started Jun 26 06:09:53 PM PDT 24
Finished Jun 26 06:09:56 PM PDT 24
Peak memory 201500 kb
Host smart-d08ccab5-f3e5-4583-828c-9f927ca51855
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510421598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.1510421598
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1527395666
Short name T918
Test name
Test status
Simulation time 300342131 ps
CPU time 1.33 seconds
Started Jun 26 06:09:50 PM PDT 24
Finished Jun 26 06:09:53 PM PDT 24
Peak memory 201424 kb
Host smart-1b576c0b-a33d-4585-9738-a2dac89f7ce1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527395666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1527395666
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3978878707
Short name T56
Test name
Test status
Simulation time 2683444918 ps
CPU time 2.07 seconds
Started Jun 26 06:09:49 PM PDT 24
Finished Jun 26 06:09:53 PM PDT 24
Peak memory 201648 kb
Host smart-903a78ba-0694-4218-87c3-b75f89498e7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978878707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.3978878707
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2541784165
Short name T72
Test name
Test status
Simulation time 355037298 ps
CPU time 1.75 seconds
Started Jun 26 06:09:54 PM PDT 24
Finished Jun 26 06:09:57 PM PDT 24
Peak memory 201808 kb
Host smart-b2632c1f-82e6-4e34-88be-2da2ad99f1cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541784165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2541784165
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3170963825
Short name T336
Test name
Test status
Simulation time 4893391547 ps
CPU time 4.54 seconds
Started Jun 26 06:09:49 PM PDT 24
Finished Jun 26 06:09:55 PM PDT 24
Peak memory 202064 kb
Host smart-8c2742f0-c5c8-45ff-b3a6-13d9fd2cdbd3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170963825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.3170963825
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3618711073
Short name T823
Test name
Test status
Simulation time 505132335 ps
CPU time 1.14 seconds
Started Jun 26 06:10:09 PM PDT 24
Finished Jun 26 06:10:14 PM PDT 24
Peak memory 201548 kb
Host smart-a1a14c3f-2657-4136-96d7-4228b56d1ab8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618711073 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3618711073
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.691193794
Short name T127
Test name
Test status
Simulation time 564602093 ps
CPU time 2 seconds
Started Jun 26 06:10:07 PM PDT 24
Finished Jun 26 06:10:12 PM PDT 24
Peak memory 201488 kb
Host smart-93fa093b-9c58-4ff6-bc0a-707c2fb1289d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691193794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.691193794
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.842325492
Short name T844
Test name
Test status
Simulation time 414460743 ps
CPU time 1.64 seconds
Started Jun 26 06:09:56 PM PDT 24
Finished Jun 26 06:10:00 PM PDT 24
Peak memory 201448 kb
Host smart-0ed1ddb3-5b80-4172-a31c-1c26c9e54be8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842325492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.842325492
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.589129543
Short name T144
Test name
Test status
Simulation time 4589685987 ps
CPU time 10.68 seconds
Started Jun 26 06:09:55 PM PDT 24
Finished Jun 26 06:10:07 PM PDT 24
Peak memory 201840 kb
Host smart-10955751-751c-4ce1-a83e-4145b219b90b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589129543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_c
trl_same_csr_outstanding.589129543
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3307727065
Short name T808
Test name
Test status
Simulation time 560620549 ps
CPU time 1.53 seconds
Started Jun 26 06:09:57 PM PDT 24
Finished Jun 26 06:10:01 PM PDT 24
Peak memory 201736 kb
Host smart-527373f0-f7aa-455e-a4e5-e34e95002f3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307727065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3307727065
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2115757195
Short name T910
Test name
Test status
Simulation time 8243279729 ps
CPU time 7.11 seconds
Started Jun 26 06:10:02 PM PDT 24
Finished Jun 26 06:10:11 PM PDT 24
Peak memory 201824 kb
Host smart-89743488-27a5-49cb-a95b-ed8630e59736
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115757195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.2115757195
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3940447482
Short name T841
Test name
Test status
Simulation time 437187944 ps
CPU time 1.71 seconds
Started Jun 26 06:09:51 PM PDT 24
Finished Jun 26 06:09:55 PM PDT 24
Peak memory 201584 kb
Host smart-6186cedf-f0da-438c-a7eb-0610787d2d83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940447482 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.3940447482
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3954026736
Short name T142
Test name
Test status
Simulation time 305812792 ps
CPU time 1.49 seconds
Started Jun 26 06:10:06 PM PDT 24
Finished Jun 26 06:10:10 PM PDT 24
Peak memory 201424 kb
Host smart-e2458909-8771-4a43-8f5a-7de9f2bd53b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954026736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3954026736
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1502321170
Short name T871
Test name
Test status
Simulation time 473823054 ps
CPU time 0.92 seconds
Started Jun 26 06:10:01 PM PDT 24
Finished Jun 26 06:10:03 PM PDT 24
Peak memory 201416 kb
Host smart-966366ef-c99a-4e01-843c-ec8027ff79f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502321170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.1502321170
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3545290849
Short name T878
Test name
Test status
Simulation time 2250335062 ps
CPU time 5.79 seconds
Started Jun 26 06:10:00 PM PDT 24
Finished Jun 26 06:10:08 PM PDT 24
Peak memory 201616 kb
Host smart-e65ce77a-46d7-4249-8450-4444bfbe8fc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545290849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.3545290849
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3317377630
Short name T905
Test name
Test status
Simulation time 558597026 ps
CPU time 3.11 seconds
Started Jun 26 06:10:04 PM PDT 24
Finished Jun 26 06:10:09 PM PDT 24
Peak memory 217984 kb
Host smart-5a2c281a-6484-4b44-89f5-3b5a738be5af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317377630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3317377630
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.877572257
Short name T81
Test name
Test status
Simulation time 8708491929 ps
CPU time 12.23 seconds
Started Jun 26 06:09:52 PM PDT 24
Finished Jun 26 06:10:06 PM PDT 24
Peak memory 201864 kb
Host smart-14206c6d-1ee5-49fa-a8e4-fe3310d4b1ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877572257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_in
tg_err.877572257
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2420196649
Short name T79
Test name
Test status
Simulation time 457913193 ps
CPU time 1.3 seconds
Started Jun 26 06:10:07 PM PDT 24
Finished Jun 26 06:10:11 PM PDT 24
Peak memory 201512 kb
Host smart-99eba1b2-c0a9-420f-8dfc-559455ccd524
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420196649 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2420196649
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2006171614
Short name T891
Test name
Test status
Simulation time 402145434 ps
CPU time 1.19 seconds
Started Jun 26 06:10:12 PM PDT 24
Finished Jun 26 06:10:16 PM PDT 24
Peak memory 201492 kb
Host smart-c203adfc-38c9-451d-a1df-2a24e9ee2ee5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006171614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2006171614
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.270828204
Short name T801
Test name
Test status
Simulation time 472797379 ps
CPU time 1.77 seconds
Started Jun 26 06:10:05 PM PDT 24
Finished Jun 26 06:10:09 PM PDT 24
Peak memory 201660 kb
Host smart-597152e8-4282-458a-9a18-a9789aa01e0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270828204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.270828204
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.942810761
Short name T816
Test name
Test status
Simulation time 3887396334 ps
CPU time 3.08 seconds
Started Jun 26 06:10:06 PM PDT 24
Finished Jun 26 06:10:12 PM PDT 24
Peak memory 201788 kb
Host smart-6d18caab-7894-47f5-966f-7481a609ac29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942810761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.942810761
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3351615076
Short name T813
Test name
Test status
Simulation time 465581260 ps
CPU time 2.13 seconds
Started Jun 26 06:10:12 PM PDT 24
Finished Jun 26 06:10:17 PM PDT 24
Peak memory 218052 kb
Host smart-97241ec7-ccb3-4e38-bc1f-75c42d77fbb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351615076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3351615076
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1326566717
Short name T80
Test name
Test status
Simulation time 8178658724 ps
CPU time 20.29 seconds
Started Jun 26 06:10:02 PM PDT 24
Finished Jun 26 06:10:24 PM PDT 24
Peak memory 201824 kb
Host smart-f6dd636e-8cc1-4215-9b4d-6b5095547224
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326566717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.1326566717
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2637287872
Short name T129
Test name
Test status
Simulation time 872086170 ps
CPU time 3.41 seconds
Started Jun 26 06:09:56 PM PDT 24
Finished Jun 26 06:10:01 PM PDT 24
Peak memory 201728 kb
Host smart-aef70a1c-4440-478e-a0d4-b2652cd20ff6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637287872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.2637287872
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2366446932
Short name T909
Test name
Test status
Simulation time 2524452919 ps
CPU time 5.33 seconds
Started Jun 26 06:09:44 PM PDT 24
Finished Jun 26 06:09:51 PM PDT 24
Peak memory 201864 kb
Host smart-e5756fd9-1bd4-4d7f-8661-94a1bc3e1cfa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366446932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2366446932
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1447186911
Short name T140
Test name
Test status
Simulation time 963410132 ps
CPU time 2.8 seconds
Started Jun 26 06:09:33 PM PDT 24
Finished Jun 26 06:09:37 PM PDT 24
Peak memory 201452 kb
Host smart-58de3c68-0733-4ddc-9515-7e689f90cead
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447186911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.1447186911
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2616215299
Short name T820
Test name
Test status
Simulation time 503421923 ps
CPU time 1.92 seconds
Started Jun 26 06:09:52 PM PDT 24
Finished Jun 26 06:09:56 PM PDT 24
Peak memory 201552 kb
Host smart-e6d45bde-7e38-4e06-a135-85e814c9e8c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616215299 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.2616215299
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2839713015
Short name T128
Test name
Test status
Simulation time 527870508 ps
CPU time 1.95 seconds
Started Jun 26 06:09:55 PM PDT 24
Finished Jun 26 06:09:59 PM PDT 24
Peak memory 201516 kb
Host smart-cccacebe-acb4-40a9-b1d6-ecb4f3a85a7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839713015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.2839713015
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2329565854
Short name T870
Test name
Test status
Simulation time 453377187 ps
CPU time 0.75 seconds
Started Jun 26 06:09:37 PM PDT 24
Finished Jun 26 06:09:39 PM PDT 24
Peak memory 200644 kb
Host smart-744bd75c-c19a-41f2-80d6-272e90131119
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329565854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2329565854
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2224424374
Short name T817
Test name
Test status
Simulation time 4538903036 ps
CPU time 5.26 seconds
Started Jun 26 06:09:49 PM PDT 24
Finished Jun 26 06:09:56 PM PDT 24
Peak memory 201844 kb
Host smart-205e24cf-742e-4cd5-8139-ec9bb886b57b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224424374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.2224424374
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.970126387
Short name T71
Test name
Test status
Simulation time 513066766 ps
CPU time 2.77 seconds
Started Jun 26 06:09:38 PM PDT 24
Finished Jun 26 06:09:42 PM PDT 24
Peak memory 210008 kb
Host smart-0b50299f-37df-4902-9428-8d3d58eda79d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970126387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.970126387
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2863012808
Short name T810
Test name
Test status
Simulation time 521229088 ps
CPU time 0.71 seconds
Started Jun 26 06:09:59 PM PDT 24
Finished Jun 26 06:10:02 PM PDT 24
Peak memory 201440 kb
Host smart-0cd946bc-6130-48e0-b96d-9f6f46c7c679
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863012808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2863012808
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3850595742
Short name T900
Test name
Test status
Simulation time 436513191 ps
CPU time 1.57 seconds
Started Jun 26 06:10:08 PM PDT 24
Finished Jun 26 06:10:13 PM PDT 24
Peak memory 201460 kb
Host smart-c28a6114-ec8c-4ae2-b4aa-492a23db5090
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850595742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.3850595742
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2602971493
Short name T798
Test name
Test status
Simulation time 485535654 ps
CPU time 1.8 seconds
Started Jun 26 06:10:03 PM PDT 24
Finished Jun 26 06:10:07 PM PDT 24
Peak memory 201452 kb
Host smart-5ae045e8-4377-4aaf-b765-2e573332b40e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602971493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2602971493
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1524009541
Short name T802
Test name
Test status
Simulation time 334768609 ps
CPU time 0.89 seconds
Started Jun 26 06:10:07 PM PDT 24
Finished Jun 26 06:10:11 PM PDT 24
Peak memory 201660 kb
Host smart-7b02e73b-1b1a-4abc-b0e2-3a104ece2781
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524009541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1524009541
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.469451362
Short name T887
Test name
Test status
Simulation time 303999400 ps
CPU time 0.98 seconds
Started Jun 26 06:10:08 PM PDT 24
Finished Jun 26 06:10:13 PM PDT 24
Peak memory 201460 kb
Host smart-765a5190-f16d-42e1-8c79-a293033c5568
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469451362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.469451362
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3340271310
Short name T859
Test name
Test status
Simulation time 317228102 ps
CPU time 0.76 seconds
Started Jun 26 06:10:07 PM PDT 24
Finished Jun 26 06:10:11 PM PDT 24
Peak memory 201440 kb
Host smart-5cb8a0d7-dedd-40a6-abb8-ad25175044bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340271310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.3340271310
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.114467225
Short name T797
Test name
Test status
Simulation time 450404857 ps
CPU time 1.22 seconds
Started Jun 26 06:10:05 PM PDT 24
Finished Jun 26 06:10:09 PM PDT 24
Peak memory 201452 kb
Host smart-89fe0493-2c8d-47db-91ee-a3acb85eba17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114467225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.114467225
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2300467413
Short name T809
Test name
Test status
Simulation time 446870987 ps
CPU time 0.89 seconds
Started Jun 26 06:10:03 PM PDT 24
Finished Jun 26 06:10:06 PM PDT 24
Peak memory 201324 kb
Host smart-ed5b85b1-e57e-4e71-9547-177e6e1aa681
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300467413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2300467413
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2102792962
Short name T803
Test name
Test status
Simulation time 480418265 ps
CPU time 0.72 seconds
Started Jun 26 06:10:09 PM PDT 24
Finished Jun 26 06:10:14 PM PDT 24
Peak memory 201376 kb
Host smart-147bd84f-5609-4de4-a4a0-8d32769acc08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102792962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2102792962
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.398586158
Short name T893
Test name
Test status
Simulation time 355554994 ps
CPU time 1.09 seconds
Started Jun 26 06:10:08 PM PDT 24
Finished Jun 26 06:10:13 PM PDT 24
Peak memory 201376 kb
Host smart-b886b463-4c5e-45f4-963f-4a60bd1213f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398586158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.398586158
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3330702907
Short name T134
Test name
Test status
Simulation time 1115271019 ps
CPU time 5.03 seconds
Started Jun 26 06:09:41 PM PDT 24
Finished Jun 26 06:09:47 PM PDT 24
Peak memory 201756 kb
Host smart-c31739a2-23e1-4549-b8d9-4f50ffdc5e91
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330702907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3330702907
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3381050311
Short name T135
Test name
Test status
Simulation time 52345820318 ps
CPU time 35.61 seconds
Started Jun 26 06:09:56 PM PDT 24
Finished Jun 26 06:10:33 PM PDT 24
Peak memory 201860 kb
Host smart-1a7cfc00-5989-434c-89fc-e47bbc58dccb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381050311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3381050311
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1217170108
Short name T133
Test name
Test status
Simulation time 899570767 ps
CPU time 0.97 seconds
Started Jun 26 06:09:38 PM PDT 24
Finished Jun 26 06:09:40 PM PDT 24
Peak memory 201452 kb
Host smart-1aa81244-1dbd-406c-b7ff-4441c8695279
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217170108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1217170108
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2498076227
Short name T889
Test name
Test status
Simulation time 589629541 ps
CPU time 1.66 seconds
Started Jun 26 06:09:41 PM PDT 24
Finished Jun 26 06:09:44 PM PDT 24
Peak memory 201560 kb
Host smart-59b44f5f-0eb8-49be-a27b-d5bf433d1aba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498076227 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.2498076227
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3302369376
Short name T830
Test name
Test status
Simulation time 393103563 ps
CPU time 1.14 seconds
Started Jun 26 06:09:55 PM PDT 24
Finished Jun 26 06:09:57 PM PDT 24
Peak memory 201512 kb
Host smart-919f9e97-a90f-4ca3-8d9f-23aba4547d6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302369376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3302369376
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1532323570
Short name T858
Test name
Test status
Simulation time 522503121 ps
CPU time 1.73 seconds
Started Jun 26 06:10:06 PM PDT 24
Finished Jun 26 06:10:10 PM PDT 24
Peak memory 201436 kb
Host smart-9a4a649a-4587-4af3-897d-5badcdde170d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532323570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.1532323570
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2377665084
Short name T913
Test name
Test status
Simulation time 2368158396 ps
CPU time 2.23 seconds
Started Jun 26 06:09:40 PM PDT 24
Finished Jun 26 06:09:44 PM PDT 24
Peak memory 201660 kb
Host smart-e2d275db-6cfe-4d9c-8e36-f5b0a793dedd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377665084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2377665084
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3647864698
Short name T822
Test name
Test status
Simulation time 770347443 ps
CPU time 1.82 seconds
Started Jun 26 06:10:04 PM PDT 24
Finished Jun 26 06:10:08 PM PDT 24
Peak memory 201796 kb
Host smart-88b8482b-f5d7-49a2-83cc-130b1905de1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647864698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3647864698
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2393271719
Short name T897
Test name
Test status
Simulation time 4445376606 ps
CPU time 12.44 seconds
Started Jun 26 06:09:38 PM PDT 24
Finished Jun 26 06:09:53 PM PDT 24
Peak memory 201752 kb
Host smart-f2583105-4337-47c2-b1f8-3640cbff9483
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393271719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.2393271719
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2276024749
Short name T829
Test name
Test status
Simulation time 366008730 ps
CPU time 1.37 seconds
Started Jun 26 06:10:04 PM PDT 24
Finished Jun 26 06:10:07 PM PDT 24
Peak memory 201416 kb
Host smart-8b3b55b6-7b03-4c16-a745-d7594242cee7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276024749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2276024749
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1819298688
Short name T848
Test name
Test status
Simulation time 470143798 ps
CPU time 1.7 seconds
Started Jun 26 06:10:06 PM PDT 24
Finished Jun 26 06:10:11 PM PDT 24
Peak memory 201408 kb
Host smart-f6642e0e-a171-48ad-9608-5c89dbd60675
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819298688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1819298688
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3763554954
Short name T912
Test name
Test status
Simulation time 506769898 ps
CPU time 1.38 seconds
Started Jun 26 06:10:11 PM PDT 24
Finished Jun 26 06:10:15 PM PDT 24
Peak memory 201392 kb
Host smart-72d8867e-6343-49f9-93b5-023535699784
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763554954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.3763554954
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3111936865
Short name T914
Test name
Test status
Simulation time 483502444 ps
CPU time 0.93 seconds
Started Jun 26 06:10:06 PM PDT 24
Finished Jun 26 06:10:10 PM PDT 24
Peak memory 201440 kb
Host smart-74efa1c1-983e-4ca3-a44a-5dac3130fb0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111936865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3111936865
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3255015127
Short name T904
Test name
Test status
Simulation time 506569648 ps
CPU time 0.93 seconds
Started Jun 26 06:10:08 PM PDT 24
Finished Jun 26 06:10:13 PM PDT 24
Peak memory 201444 kb
Host smart-bf5a3fda-48aa-485a-9a05-0b9517fa370a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255015127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3255015127
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1916841340
Short name T866
Test name
Test status
Simulation time 463389867 ps
CPU time 1.69 seconds
Started Jun 26 06:10:01 PM PDT 24
Finished Jun 26 06:10:05 PM PDT 24
Peak memory 201372 kb
Host smart-841ea56e-c97d-4a12-9b03-41e718c2dfe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916841340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1916841340
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2336996720
Short name T861
Test name
Test status
Simulation time 459028771 ps
CPU time 0.9 seconds
Started Jun 26 06:10:06 PM PDT 24
Finished Jun 26 06:10:10 PM PDT 24
Peak memory 201468 kb
Host smart-3250cc12-058a-434f-8325-878245a14fc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336996720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2336996720
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1497185065
Short name T800
Test name
Test status
Simulation time 518745013 ps
CPU time 1.03 seconds
Started Jun 26 06:10:08 PM PDT 24
Finished Jun 26 06:10:12 PM PDT 24
Peak memory 201368 kb
Host smart-3d6bfc20-2b14-45cf-993b-3f68ef8c1af0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497185065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.1497185065
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3931357269
Short name T890
Test name
Test status
Simulation time 444553679 ps
CPU time 0.75 seconds
Started Jun 26 06:10:08 PM PDT 24
Finished Jun 26 06:10:13 PM PDT 24
Peak memory 201428 kb
Host smart-b98dd1a6-fc0c-484d-93f3-0617986a8d43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931357269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3931357269
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2178635357
Short name T902
Test name
Test status
Simulation time 370842680 ps
CPU time 1.49 seconds
Started Jun 26 06:10:05 PM PDT 24
Finished Jun 26 06:10:08 PM PDT 24
Peak memory 201432 kb
Host smart-630fca83-57b8-4503-aaf6-e795127dab74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178635357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2178635357
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1565321209
Short name T131
Test name
Test status
Simulation time 771649416 ps
CPU time 1.85 seconds
Started Jun 26 06:09:57 PM PDT 24
Finished Jun 26 06:10:01 PM PDT 24
Peak memory 201704 kb
Host smart-1b21cdb0-c2de-4a92-a1e0-6a1ad2a3db11
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565321209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.1565321209
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3368878453
Short name T137
Test name
Test status
Simulation time 979631840 ps
CPU time 0.93 seconds
Started Jun 26 06:09:45 PM PDT 24
Finished Jun 26 06:09:48 PM PDT 24
Peak memory 201516 kb
Host smart-8db97057-b86f-4388-9e23-243c679a49ad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368878453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.3368878453
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1219154748
Short name T64
Test name
Test status
Simulation time 588214778 ps
CPU time 1.15 seconds
Started Jun 26 06:09:58 PM PDT 24
Finished Jun 26 06:10:01 PM PDT 24
Peak memory 201548 kb
Host smart-d972a5e7-cbba-4ec1-a0f1-6e6ede1f790b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219154748 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.1219154748
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2117749702
Short name T877
Test name
Test status
Simulation time 545217654 ps
CPU time 1.06 seconds
Started Jun 26 06:10:06 PM PDT 24
Finished Jun 26 06:10:10 PM PDT 24
Peak memory 201512 kb
Host smart-acb818e1-3d4a-4b56-b707-d685814bccf5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117749702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.2117749702
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3687153822
Short name T851
Test name
Test status
Simulation time 397361335 ps
CPU time 0.89 seconds
Started Jun 26 06:10:01 PM PDT 24
Finished Jun 26 06:10:04 PM PDT 24
Peak memory 201452 kb
Host smart-9449e7fb-df73-4166-8e23-ff331aa1f926
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687153822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3687153822
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1020969043
Short name T906
Test name
Test status
Simulation time 2758502726 ps
CPU time 5.1 seconds
Started Jun 26 06:09:48 PM PDT 24
Finished Jun 26 06:09:54 PM PDT 24
Peak memory 201648 kb
Host smart-9e92ebcd-fc83-451c-be68-9dc2f2cbd4ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020969043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1020969043
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1264915870
Short name T73
Test name
Test status
Simulation time 386739041 ps
CPU time 2.96 seconds
Started Jun 26 06:09:54 PM PDT 24
Finished Jun 26 06:09:59 PM PDT 24
Peak memory 218096 kb
Host smart-b3412bc0-b9c3-4704-8c50-4064861b1386
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264915870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1264915870
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3109987982
Short name T865
Test name
Test status
Simulation time 8242488378 ps
CPU time 21.05 seconds
Started Jun 26 06:09:55 PM PDT 24
Finished Jun 26 06:10:18 PM PDT 24
Peak memory 201824 kb
Host smart-e8e15c53-4dd2-48dd-a1de-a82c02c957b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109987982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3109987982
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.9613759
Short name T826
Test name
Test status
Simulation time 598170278 ps
CPU time 0.72 seconds
Started Jun 26 06:10:07 PM PDT 24
Finished Jun 26 06:10:11 PM PDT 24
Peak memory 201412 kb
Host smart-51a539b1-fc56-4b2d-bb34-779e4ecdb2d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9613759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.9613759
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2096564145
Short name T812
Test name
Test status
Simulation time 318109003 ps
CPU time 1.05 seconds
Started Jun 26 06:10:07 PM PDT 24
Finished Jun 26 06:10:12 PM PDT 24
Peak memory 201460 kb
Host smart-f4d70589-7c3c-4446-b906-5787f72a1b8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096564145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.2096564145
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.751064667
Short name T855
Test name
Test status
Simulation time 401756835 ps
CPU time 0.88 seconds
Started Jun 26 06:10:07 PM PDT 24
Finished Jun 26 06:10:11 PM PDT 24
Peak memory 201376 kb
Host smart-6beb71ed-9d79-401f-a52b-d1876cd469ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751064667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.751064667
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2741398847
Short name T850
Test name
Test status
Simulation time 535222670 ps
CPU time 1.08 seconds
Started Jun 26 06:10:02 PM PDT 24
Finished Jun 26 06:10:05 PM PDT 24
Peak memory 201448 kb
Host smart-73cb5952-35e2-4734-ab83-4b3728bff403
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741398847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2741398847
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.4042398024
Short name T862
Test name
Test status
Simulation time 347883684 ps
CPU time 0.75 seconds
Started Jun 26 06:10:04 PM PDT 24
Finished Jun 26 06:10:07 PM PDT 24
Peak memory 201364 kb
Host smart-6feb30bc-9505-46e2-9394-cb132422f7e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042398024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.4042398024
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.900141818
Short name T869
Test name
Test status
Simulation time 445389592 ps
CPU time 1.22 seconds
Started Jun 26 06:10:07 PM PDT 24
Finished Jun 26 06:10:11 PM PDT 24
Peak memory 201424 kb
Host smart-be0252f6-fc05-4354-9c94-951bd4e0c830
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900141818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.900141818
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.961634425
Short name T807
Test name
Test status
Simulation time 363096081 ps
CPU time 0.84 seconds
Started Jun 26 06:10:02 PM PDT 24
Finished Jun 26 06:10:04 PM PDT 24
Peak memory 201320 kb
Host smart-934e9a39-4f70-4e75-b5c8-9e4acdfe7ab5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961634425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.961634425
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.4272590172
Short name T847
Test name
Test status
Simulation time 436513766 ps
CPU time 1.59 seconds
Started Jun 26 06:10:06 PM PDT 24
Finished Jun 26 06:10:10 PM PDT 24
Peak memory 201428 kb
Host smart-c550523a-cb55-4847-8ed5-427eb2824b9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272590172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.4272590172
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3410228723
Short name T814
Test name
Test status
Simulation time 370770667 ps
CPU time 1.52 seconds
Started Jun 26 06:10:03 PM PDT 24
Finished Jun 26 06:10:06 PM PDT 24
Peak memory 201412 kb
Host smart-f6bb307f-0cf0-4095-a00c-8b004a84bcac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410228723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3410228723
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2869853746
Short name T916
Test name
Test status
Simulation time 438319305 ps
CPU time 1.13 seconds
Started Jun 26 06:10:04 PM PDT 24
Finished Jun 26 06:10:07 PM PDT 24
Peak memory 201464 kb
Host smart-fd6d0efc-c73c-4c7b-8e62-a1f9513b4d6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869853746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2869853746
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2462338213
Short name T879
Test name
Test status
Simulation time 456226201 ps
CPU time 1.13 seconds
Started Jun 26 06:09:48 PM PDT 24
Finished Jun 26 06:09:50 PM PDT 24
Peak memory 201548 kb
Host smart-06a80ed1-22d8-438a-83ed-a39533c6b416
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462338213 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.2462338213
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3132814653
Short name T143
Test name
Test status
Simulation time 512834671 ps
CPU time 1.32 seconds
Started Jun 26 06:10:05 PM PDT 24
Finished Jun 26 06:10:09 PM PDT 24
Peak memory 201488 kb
Host smart-3f426938-a670-4ddc-ad43-fafecfeaa168
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132814653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3132814653
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.892349866
Short name T804
Test name
Test status
Simulation time 309541692 ps
CPU time 0.78 seconds
Started Jun 26 06:09:54 PM PDT 24
Finished Jun 26 06:09:56 PM PDT 24
Peak memory 201436 kb
Host smart-ab3da63a-00a3-4cd8-bcca-0974cce0fdf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892349866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.892349866
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.217364238
Short name T857
Test name
Test status
Simulation time 2523049001 ps
CPU time 5.08 seconds
Started Jun 26 06:09:39 PM PDT 24
Finished Jun 26 06:09:46 PM PDT 24
Peak memory 201624 kb
Host smart-284b7a56-056f-4849-adac-16fdb780ae5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217364238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ct
rl_same_csr_outstanding.217364238
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.4215479100
Short name T873
Test name
Test status
Simulation time 8022525808 ps
CPU time 6.92 seconds
Started Jun 26 06:10:02 PM PDT 24
Finished Jun 26 06:10:11 PM PDT 24
Peak memory 201816 kb
Host smart-50658f13-d0e8-4991-ad3f-4196ae3c7dd3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215479100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.4215479100
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.219355586
Short name T892
Test name
Test status
Simulation time 498641900 ps
CPU time 1.85 seconds
Started Jun 26 06:10:04 PM PDT 24
Finished Jun 26 06:10:08 PM PDT 24
Peak memory 201572 kb
Host smart-dc39d037-f8f3-4973-93fd-91570ec7b8e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219355586 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.219355586
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.904481313
Short name T141
Test name
Test status
Simulation time 534427304 ps
CPU time 1.71 seconds
Started Jun 26 06:09:48 PM PDT 24
Finished Jun 26 06:09:51 PM PDT 24
Peak memory 201488 kb
Host smart-2f344c2e-672d-49cd-9922-66d4c5561e4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904481313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.904481313
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2454262202
Short name T796
Test name
Test status
Simulation time 483011021 ps
CPU time 0.91 seconds
Started Jun 26 06:09:40 PM PDT 24
Finished Jun 26 06:09:42 PM PDT 24
Peak memory 201464 kb
Host smart-123d9121-905b-4407-84a8-b8a298d2c03c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454262202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2454262202
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.816885946
Short name T837
Test name
Test status
Simulation time 1897127317 ps
CPU time 3.86 seconds
Started Jun 26 06:10:01 PM PDT 24
Finished Jun 26 06:10:07 PM PDT 24
Peak memory 201488 kb
Host smart-3e442cd9-c518-4b3c-9da2-c09c6baaa33b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816885946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ct
rl_same_csr_outstanding.816885946
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.861788592
Short name T839
Test name
Test status
Simulation time 431690546 ps
CPU time 2.37 seconds
Started Jun 26 06:10:01 PM PDT 24
Finished Jun 26 06:10:05 PM PDT 24
Peak memory 201824 kb
Host smart-b92d8ec8-0023-488a-a9e1-66bfcc015721
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861788592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.861788592
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3525705134
Short name T915
Test name
Test status
Simulation time 4618769160 ps
CPU time 4.33 seconds
Started Jun 26 06:09:51 PM PDT 24
Finished Jun 26 06:09:57 PM PDT 24
Peak memory 201892 kb
Host smart-e0f1ed5b-694c-4e6e-b731-b7c30617e5d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525705134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.3525705134
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.942472337
Short name T863
Test name
Test status
Simulation time 520830766 ps
CPU time 2.02 seconds
Started Jun 26 06:09:45 PM PDT 24
Finished Jun 26 06:09:49 PM PDT 24
Peak memory 201588 kb
Host smart-241d9837-803c-4405-ae4c-3bad7ff31664
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942472337 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.942472337
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.4228544481
Short name T883
Test name
Test status
Simulation time 488257761 ps
CPU time 1.84 seconds
Started Jun 26 06:10:06 PM PDT 24
Finished Jun 26 06:10:11 PM PDT 24
Peak memory 201524 kb
Host smart-285c64b7-43cb-40bb-9c00-f69c3aaf83f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228544481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.4228544481
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1767569398
Short name T908
Test name
Test status
Simulation time 585078295 ps
CPU time 0.86 seconds
Started Jun 26 06:10:03 PM PDT 24
Finished Jun 26 06:10:05 PM PDT 24
Peak memory 201416 kb
Host smart-336175b2-c296-4a87-ada0-3b7b6400c10b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767569398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1767569398
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3092951835
Short name T845
Test name
Test status
Simulation time 2827177715 ps
CPU time 3.13 seconds
Started Jun 26 06:09:38 PM PDT 24
Finished Jun 26 06:09:43 PM PDT 24
Peak memory 201860 kb
Host smart-7ae88af6-3e83-433b-a946-e0308dafda93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092951835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3092951835
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2769243764
Short name T70
Test name
Test status
Simulation time 382791797 ps
CPU time 1.71 seconds
Started Jun 26 06:10:06 PM PDT 24
Finished Jun 26 06:10:10 PM PDT 24
Peak memory 201776 kb
Host smart-10c54d45-cb4f-4bfd-9161-093de3bc40f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769243764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2769243764
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.548489010
Short name T854
Test name
Test status
Simulation time 4104067496 ps
CPU time 10.12 seconds
Started Jun 26 06:09:56 PM PDT 24
Finished Jun 26 06:10:08 PM PDT 24
Peak memory 201820 kb
Host smart-79df626e-11eb-4df6-ab0d-c9b91bb75fec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548489010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_int
g_err.548489010
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2217342952
Short name T852
Test name
Test status
Simulation time 488063851 ps
CPU time 1.39 seconds
Started Jun 26 06:09:45 PM PDT 24
Finished Jun 26 06:09:48 PM PDT 24
Peak memory 201548 kb
Host smart-495198e6-4174-4ac7-ac48-d99c230b0cbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217342952 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.2217342952
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1245584674
Short name T825
Test name
Test status
Simulation time 419602682 ps
CPU time 1.67 seconds
Started Jun 26 06:09:50 PM PDT 24
Finished Jun 26 06:09:53 PM PDT 24
Peak memory 201456 kb
Host smart-d3e60b09-7f03-43d4-99bc-25ac8c13d2ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245584674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.1245584674
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3414013486
Short name T853
Test name
Test status
Simulation time 522412388 ps
CPU time 1.76 seconds
Started Jun 26 06:09:45 PM PDT 24
Finished Jun 26 06:09:49 PM PDT 24
Peak memory 201412 kb
Host smart-1bdc824a-041b-4238-a48e-c334beed58a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414013486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3414013486
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2662753559
Short name T832
Test name
Test status
Simulation time 2255798997 ps
CPU time 5.68 seconds
Started Jun 26 06:09:44 PM PDT 24
Finished Jun 26 06:09:52 PM PDT 24
Peak memory 201632 kb
Host smart-de10c0b4-f05b-4006-8eee-c8644376e450
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662753559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2662753559
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.841961799
Short name T872
Test name
Test status
Simulation time 856919363 ps
CPU time 2.94 seconds
Started Jun 26 06:09:44 PM PDT 24
Finished Jun 26 06:09:48 PM PDT 24
Peak memory 201720 kb
Host smart-7f888ce3-73ec-4db0-b140-28cfa1adcd9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841961799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.841961799
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3801198873
Short name T888
Test name
Test status
Simulation time 8278278735 ps
CPU time 7.69 seconds
Started Jun 26 06:09:53 PM PDT 24
Finished Jun 26 06:10:02 PM PDT 24
Peak memory 201812 kb
Host smart-252136ae-9679-476a-a66b-5fbce75d84f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801198873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.3801198873
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.565089852
Short name T78
Test name
Test status
Simulation time 461261343 ps
CPU time 1.5 seconds
Started Jun 26 06:09:52 PM PDT 24
Finished Jun 26 06:09:55 PM PDT 24
Peak memory 201600 kb
Host smart-e619d8c8-71bd-45e0-a23e-2eb9cdd41a4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565089852 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.565089852
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.865732051
Short name T138
Test name
Test status
Simulation time 432554095 ps
CPU time 1.05 seconds
Started Jun 26 06:09:57 PM PDT 24
Finished Jun 26 06:10:01 PM PDT 24
Peak memory 201540 kb
Host smart-78e89a3d-63f1-436e-894c-807be522301b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865732051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.865732051
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3791013321
Short name T846
Test name
Test status
Simulation time 539019177 ps
CPU time 0.94 seconds
Started Jun 26 06:09:47 PM PDT 24
Finished Jun 26 06:09:55 PM PDT 24
Peak memory 201412 kb
Host smart-f738905d-3c4e-4951-8cbd-64e5d7cff29a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791013321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3791013321
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2428835875
Short name T818
Test name
Test status
Simulation time 4597591756 ps
CPU time 6.23 seconds
Started Jun 26 06:09:46 PM PDT 24
Finished Jun 26 06:09:54 PM PDT 24
Peak memory 201808 kb
Host smart-ab65a413-fcd8-4c38-86a5-edccbf59f92c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428835875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2428835875
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1890950691
Short name T849
Test name
Test status
Simulation time 440169065 ps
CPU time 3.22 seconds
Started Jun 26 06:09:44 PM PDT 24
Finished Jun 26 06:09:49 PM PDT 24
Peak memory 210004 kb
Host smart-5735eff6-2ebf-4c1e-8cea-9937bc7a21fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890950691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1890950691
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1953871165
Short name T834
Test name
Test status
Simulation time 7602741539 ps
CPU time 11.89 seconds
Started Jun 26 06:09:44 PM PDT 24
Finished Jun 26 06:09:58 PM PDT 24
Peak memory 201804 kb
Host smart-b52e5adf-72a4-421a-a9af-8feca28789d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953871165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.1953871165
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2458701299
Short name T359
Test name
Test status
Simulation time 353254645 ps
CPU time 1.43 seconds
Started Jun 26 06:30:01 PM PDT 24
Finished Jun 26 06:30:04 PM PDT 24
Peak memory 201640 kb
Host smart-d6d623fd-5a2a-40b5-9e27-4e8e276c5d54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458701299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2458701299
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3306202652
Short name T215
Test name
Test status
Simulation time 498385523950 ps
CPU time 274.38 seconds
Started Jun 26 06:29:47 PM PDT 24
Finished Jun 26 06:34:24 PM PDT 24
Peak memory 201932 kb
Host smart-125e9b3b-e0d1-4275-a483-7424fc327d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306202652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3306202652
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3027024851
Short name T705
Test name
Test status
Simulation time 322129416153 ps
CPU time 393.89 seconds
Started Jun 26 06:29:44 PM PDT 24
Finished Jun 26 06:36:21 PM PDT 24
Peak memory 201844 kb
Host smart-9deb76d2-d493-4d6f-bf41-d95259850ffa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027024851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.3027024851
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2307180388
Short name T285
Test name
Test status
Simulation time 491092209855 ps
CPU time 1098.03 seconds
Started Jun 26 06:29:45 PM PDT 24
Finished Jun 26 06:48:07 PM PDT 24
Peak memory 201936 kb
Host smart-4965ab2c-f439-4a9b-abb7-67947fe91bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307180388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2307180388
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3127412806
Short name T407
Test name
Test status
Simulation time 163356114409 ps
CPU time 371.57 seconds
Started Jun 26 06:29:45 PM PDT 24
Finished Jun 26 06:36:01 PM PDT 24
Peak memory 201868 kb
Host smart-9a6783de-a781-4d7a-9568-d34daf29525b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127412806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3127412806
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.420567002
Short name T538
Test name
Test status
Simulation time 193497449978 ps
CPU time 60.24 seconds
Started Jun 26 06:29:55 PM PDT 24
Finished Jun 26 06:30:56 PM PDT 24
Peak memory 201764 kb
Host smart-79027a2b-c90a-4ecc-b95d-b1750363671b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420567002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.a
dc_ctrl_filters_wakeup_fixed.420567002
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.55965040
Short name T636
Test name
Test status
Simulation time 74653895171 ps
CPU time 338.81 seconds
Started Jun 26 06:29:51 PM PDT 24
Finished Jun 26 06:35:31 PM PDT 24
Peak memory 202256 kb
Host smart-2cd612d6-ecfe-4a5d-a346-69df9d2d92c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55965040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.55965040
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3147161145
Short name T479
Test name
Test status
Simulation time 25228050021 ps
CPU time 13.84 seconds
Started Jun 26 06:29:47 PM PDT 24
Finished Jun 26 06:30:04 PM PDT 24
Peak memory 201684 kb
Host smart-6fbb90fc-bbd5-4c98-bd39-6bb2d2235c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147161145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3147161145
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.1022179491
Short name T358
Test name
Test status
Simulation time 3919105601 ps
CPU time 5.04 seconds
Started Jun 26 06:29:57 PM PDT 24
Finished Jun 26 06:30:04 PM PDT 24
Peak memory 201592 kb
Host smart-98495b18-6c0c-40f1-ac8b-3c0b17b8ae7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022179491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.1022179491
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1435302818
Short name T575
Test name
Test status
Simulation time 5729980210 ps
CPU time 3.87 seconds
Started Jun 26 06:29:45 PM PDT 24
Finished Jun 26 06:29:52 PM PDT 24
Peak memory 201676 kb
Host smart-d8f5e3b8-a510-40c1-8e5c-13fb5973c0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435302818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1435302818
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.780773131
Short name T594
Test name
Test status
Simulation time 6605973569 ps
CPU time 8.58 seconds
Started Jun 26 06:29:48 PM PDT 24
Finished Jun 26 06:29:59 PM PDT 24
Peak memory 201696 kb
Host smart-f62e5455-d99c-473d-b4c4-9aa3622baa6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780773131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.780773131
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3324608387
Short name T237
Test name
Test status
Simulation time 872565518958 ps
CPU time 583.95 seconds
Started Jun 26 06:29:59 PM PDT 24
Finished Jun 26 06:39:44 PM PDT 24
Peak memory 210516 kb
Host smart-e9a0fae4-b5f0-49e5-b46a-64139fae37c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324608387 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.3324608387
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.3954800083
Short name T735
Test name
Test status
Simulation time 469243523 ps
CPU time 1.57 seconds
Started Jun 26 06:29:57 PM PDT 24
Finished Jun 26 06:30:00 PM PDT 24
Peak memory 201604 kb
Host smart-d04b8a3f-3476-42db-82ee-5ead715353be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954800083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3954800083
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.1285875657
Short name T454
Test name
Test status
Simulation time 164745386383 ps
CPU time 49.74 seconds
Started Jun 26 06:29:59 PM PDT 24
Finished Jun 26 06:30:50 PM PDT 24
Peak memory 201912 kb
Host smart-78f9a2ef-9ff3-485b-8c2f-27e4610d1356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285875657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1285875657
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.4279079008
Short name T527
Test name
Test status
Simulation time 166926928448 ps
CPU time 41.49 seconds
Started Jun 26 06:29:58 PM PDT 24
Finished Jun 26 06:30:40 PM PDT 24
Peak memory 201868 kb
Host smart-8eb4bb44-46c7-4ff9-b09d-a68885eeb7ce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279079008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.4279079008
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2226217971
Short name T778
Test name
Test status
Simulation time 164045411891 ps
CPU time 97.51 seconds
Started Jun 26 06:30:00 PM PDT 24
Finished Jun 26 06:31:39 PM PDT 24
Peak memory 201892 kb
Host smart-fe1432ca-26f3-4df5-a074-0575967a4b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226217971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2226217971
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1450854330
Short name T436
Test name
Test status
Simulation time 489983321998 ps
CPU time 1172.3 seconds
Started Jun 26 06:30:05 PM PDT 24
Finished Jun 26 06:49:40 PM PDT 24
Peak memory 201852 kb
Host smart-70140676-7195-4cab-9ab6-8f713a5d52b7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450854330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1450854330
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1083322443
Short name T309
Test name
Test status
Simulation time 337851484497 ps
CPU time 776.53 seconds
Started Jun 26 06:29:55 PM PDT 24
Finished Jun 26 06:42:53 PM PDT 24
Peak memory 201940 kb
Host smart-2d674aa9-2a16-4c3d-a7cd-d38a954ecf75
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083322443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1083322443
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.723318485
Short name T367
Test name
Test status
Simulation time 201370035722 ps
CPU time 432.14 seconds
Started Jun 26 06:30:03 PM PDT 24
Finished Jun 26 06:37:17 PM PDT 24
Peak memory 201864 kb
Host smart-0550c7ba-c439-47cd-bba4-fae9a6c61d3a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723318485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.a
dc_ctrl_filters_wakeup_fixed.723318485
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2198728425
Short name T666
Test name
Test status
Simulation time 87431609599 ps
CPU time 356.77 seconds
Started Jun 26 06:30:04 PM PDT 24
Finished Jun 26 06:36:03 PM PDT 24
Peak memory 202188 kb
Host smart-e249005a-ec7c-403f-b62f-b65f1a00392b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198728425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2198728425
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.445920345
Short name T389
Test name
Test status
Simulation time 24313123212 ps
CPU time 9.67 seconds
Started Jun 26 06:29:49 PM PDT 24
Finished Jun 26 06:30:01 PM PDT 24
Peak memory 201692 kb
Host smart-25dde11b-a310-48f1-9b0f-1c391e4b311c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445920345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.445920345
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.3242132158
Short name T495
Test name
Test status
Simulation time 5149479015 ps
CPU time 4.05 seconds
Started Jun 26 06:29:47 PM PDT 24
Finished Jun 26 06:29:54 PM PDT 24
Peak memory 201688 kb
Host smart-c4894297-fe36-42d8-9166-6c98e9968c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242132158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3242132158
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.1100934855
Short name T82
Test name
Test status
Simulation time 8322258402 ps
CPU time 21.12 seconds
Started Jun 26 06:29:51 PM PDT 24
Finished Jun 26 06:30:13 PM PDT 24
Peak memory 218376 kb
Host smart-6c1687fb-6733-44f9-a0a0-98d4da052307
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100934855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1100934855
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.3443779349
Short name T440
Test name
Test status
Simulation time 5756163884 ps
CPU time 4.19 seconds
Started Jun 26 06:29:57 PM PDT 24
Finished Jun 26 06:30:03 PM PDT 24
Peak memory 201580 kb
Host smart-1e4e7c0e-51d1-41d8-bddf-e824e56200dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443779349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3443779349
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1244374596
Short name T280
Test name
Test status
Simulation time 325841845401 ps
CPU time 193.95 seconds
Started Jun 26 06:30:02 PM PDT 24
Finished Jun 26 06:33:17 PM PDT 24
Peak memory 201892 kb
Host smart-fe157c3a-29d8-41da-9ed2-425566c46682
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244374596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1244374596
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2133982908
Short name T756
Test name
Test status
Simulation time 36728222999 ps
CPU time 41.65 seconds
Started Jun 26 06:29:52 PM PDT 24
Finished Jun 26 06:30:35 PM PDT 24
Peak memory 210172 kb
Host smart-61bbeb23-f9d8-4adc-a7b3-9bca0664461e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133982908 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.2133982908
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.3023668972
Short name T699
Test name
Test status
Simulation time 337404742 ps
CPU time 0.84 seconds
Started Jun 26 06:30:18 PM PDT 24
Finished Jun 26 06:30:23 PM PDT 24
Peak memory 201608 kb
Host smart-1dac5196-e7d0-4fb2-a464-56461beaf228
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023668972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3023668972
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.4196299157
Short name T334
Test name
Test status
Simulation time 537815113018 ps
CPU time 205.88 seconds
Started Jun 26 06:30:18 PM PDT 24
Finished Jun 26 06:33:48 PM PDT 24
Peak memory 201932 kb
Host smart-41564798-47b9-40fa-9aba-7ba9e934f6f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196299157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.4196299157
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.344991943
Short name T593
Test name
Test status
Simulation time 498142443855 ps
CPU time 140.78 seconds
Started Jun 26 06:30:20 PM PDT 24
Finished Jun 26 06:32:45 PM PDT 24
Peak memory 201904 kb
Host smart-d3049b65-5487-4bfa-80e8-41510ed136bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344991943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.344991943
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.2985995146
Short name T669
Test name
Test status
Simulation time 486934406471 ps
CPU time 310.92 seconds
Started Jun 26 06:30:19 PM PDT 24
Finished Jun 26 06:35:34 PM PDT 24
Peak memory 201788 kb
Host smart-28dad484-7712-41af-aee0-3100e3a04a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985995146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2985995146
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1710576929
Short name T511
Test name
Test status
Simulation time 331558772872 ps
CPU time 240.19 seconds
Started Jun 26 06:30:19 PM PDT 24
Finished Jun 26 06:34:23 PM PDT 24
Peak memory 201880 kb
Host smart-702d172c-d5ef-4b27-b39b-1bba7876056e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710576929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.1710576929
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.2494163594
Short name T185
Test name
Test status
Simulation time 334173645457 ps
CPU time 83.09 seconds
Started Jun 26 06:30:17 PM PDT 24
Finished Jun 26 06:31:44 PM PDT 24
Peak memory 201952 kb
Host smart-a27febb8-00bd-496c-a601-28aa546d7c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494163594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2494163594
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.940135387
Short name T676
Test name
Test status
Simulation time 164029168119 ps
CPU time 202.88 seconds
Started Jun 26 06:30:23 PM PDT 24
Finished Jun 26 06:33:49 PM PDT 24
Peak memory 201804 kb
Host smart-a4ee0a54-9dfa-4d7f-ab5a-ca3d59bc5003
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=940135387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixe
d.940135387
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1064845437
Short name T192
Test name
Test status
Simulation time 371227871379 ps
CPU time 267.38 seconds
Started Jun 26 06:30:20 PM PDT 24
Finished Jun 26 06:34:52 PM PDT 24
Peak memory 201948 kb
Host smart-b126dc2f-9831-4739-a97d-f6c733b363f8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064845437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1064845437
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.119471879
Short name T665
Test name
Test status
Simulation time 388821615846 ps
CPU time 220 seconds
Started Jun 26 06:30:21 PM PDT 24
Finished Jun 26 06:34:04 PM PDT 24
Peak memory 201868 kb
Host smart-29ad89c6-8363-4565-af3f-5f960c62b3dd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119471879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.119471879
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.560652720
Short name T672
Test name
Test status
Simulation time 130081558740 ps
CPU time 679 seconds
Started Jun 26 06:30:22 PM PDT 24
Finished Jun 26 06:41:44 PM PDT 24
Peak memory 202176 kb
Host smart-751008af-fb06-4fe0-baa8-4dd8f1703124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560652720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.560652720
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.3190179418
Short name T637
Test name
Test status
Simulation time 44362683353 ps
CPU time 95.73 seconds
Started Jun 26 06:30:13 PM PDT 24
Finished Jun 26 06:31:50 PM PDT 24
Peak memory 201704 kb
Host smart-39481611-32e2-427f-8039-2a774efb90c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190179418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.3190179418
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.1426048029
Short name T382
Test name
Test status
Simulation time 3168692208 ps
CPU time 2.67 seconds
Started Jun 26 06:30:17 PM PDT 24
Finished Jun 26 06:30:23 PM PDT 24
Peak memory 201708 kb
Host smart-0fd299a6-a943-41b6-9f38-0201ebd4b1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426048029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.1426048029
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3203360191
Short name T767
Test name
Test status
Simulation time 5817856723 ps
CPU time 4.01 seconds
Started Jun 26 06:30:14 PM PDT 24
Finished Jun 26 06:30:19 PM PDT 24
Peak memory 201688 kb
Host smart-0519c66d-b353-4773-a551-95462717af0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203360191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3203360191
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.4248254639
Short name T639
Test name
Test status
Simulation time 169347270870 ps
CPU time 180.5 seconds
Started Jun 26 06:30:22 PM PDT 24
Finished Jun 26 06:33:26 PM PDT 24
Peak memory 201620 kb
Host smart-4bd34d56-0821-48af-b568-a24c7858bdc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248254639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.4248254639
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1961814067
Short name T668
Test name
Test status
Simulation time 37605417920 ps
CPU time 85.16 seconds
Started Jun 26 06:30:15 PM PDT 24
Finished Jun 26 06:31:42 PM PDT 24
Peak memory 210516 kb
Host smart-5c04d69b-8ff3-42ce-96b6-5e3727bf3092
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961814067 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1961814067
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.455127007
Short name T431
Test name
Test status
Simulation time 411786833 ps
CPU time 0.83 seconds
Started Jun 26 06:30:20 PM PDT 24
Finished Jun 26 06:30:25 PM PDT 24
Peak memory 201588 kb
Host smart-15dbcf81-f899-49bb-bf0a-5c9aaba4a283
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455127007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.455127007
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.560364502
Short name T216
Test name
Test status
Simulation time 489349439067 ps
CPU time 551.13 seconds
Started Jun 26 06:30:12 PM PDT 24
Finished Jun 26 06:39:25 PM PDT 24
Peak memory 201940 kb
Host smart-8c671e0e-2d82-40de-9ad3-93988c2d3f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560364502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.560364502
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.727010131
Short name T449
Test name
Test status
Simulation time 161723422087 ps
CPU time 185.76 seconds
Started Jun 26 06:30:20 PM PDT 24
Finished Jun 26 06:33:30 PM PDT 24
Peak memory 201872 kb
Host smart-54c222ac-8f47-4d0b-a125-15cb1a421901
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=727010131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrup
t_fixed.727010131
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.3175042789
Short name T418
Test name
Test status
Simulation time 160377840185 ps
CPU time 93.75 seconds
Started Jun 26 06:30:19 PM PDT 24
Finished Jun 26 06:31:56 PM PDT 24
Peak memory 201868 kb
Host smart-acf8512d-52dc-4fdd-82d2-148342136103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175042789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3175042789
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.4136170930
Short name T780
Test name
Test status
Simulation time 495942878058 ps
CPU time 1091.76 seconds
Started Jun 26 06:30:13 PM PDT 24
Finished Jun 26 06:48:27 PM PDT 24
Peak memory 201856 kb
Host smart-6f057b89-6476-408a-84ed-aabd536aa33a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136170930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.4136170930
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.4039136728
Short name T276
Test name
Test status
Simulation time 539732776457 ps
CPU time 1084.19 seconds
Started Jun 26 06:30:20 PM PDT 24
Finished Jun 26 06:48:29 PM PDT 24
Peak memory 201688 kb
Host smart-d385febd-b7ee-4a09-93ed-02f41a5de4e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039136728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.4039136728
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.2360899210
Short name T390
Test name
Test status
Simulation time 195976718348 ps
CPU time 106.07 seconds
Started Jun 26 06:30:15 PM PDT 24
Finished Jun 26 06:32:04 PM PDT 24
Peak memory 201924 kb
Host smart-a8ab55d4-b606-4c3c-ac9c-7be51b0a9ae3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360899210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.2360899210
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.2866754447
Short name T768
Test name
Test status
Simulation time 119623944602 ps
CPU time 411.29 seconds
Started Jun 26 06:30:17 PM PDT 24
Finished Jun 26 06:37:12 PM PDT 24
Peak memory 202264 kb
Host smart-3fe6478f-c675-474d-b7fe-27e7bdccead9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866754447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2866754447
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.1328984785
Short name T678
Test name
Test status
Simulation time 36808174590 ps
CPU time 28.78 seconds
Started Jun 26 06:30:20 PM PDT 24
Finished Jun 26 06:30:53 PM PDT 24
Peak memory 201688 kb
Host smart-4d5fe324-6ea3-475f-9b9d-7f032f015366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328984785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.1328984785
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.3313991304
Short name T121
Test name
Test status
Simulation time 5151657212 ps
CPU time 3.45 seconds
Started Jun 26 06:30:21 PM PDT 24
Finished Jun 26 06:30:28 PM PDT 24
Peak memory 201692 kb
Host smart-094ea2a8-0879-4f11-9b24-1b014285a341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313991304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.3313991304
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.399128318
Short name T388
Test name
Test status
Simulation time 5883012742 ps
CPU time 2.01 seconds
Started Jun 26 06:30:17 PM PDT 24
Finished Jun 26 06:30:22 PM PDT 24
Peak memory 201668 kb
Host smart-24e401a8-a0e6-49ab-88b0-a04788c0d14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399128318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.399128318
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.4008274073
Short name T545
Test name
Test status
Simulation time 47716242651 ps
CPU time 29.72 seconds
Started Jun 26 06:30:22 PM PDT 24
Finished Jun 26 06:30:55 PM PDT 24
Peak memory 201592 kb
Host smart-715c4b60-c2b0-4beb-a6f5-94baee42a2d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008274073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.4008274073
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3388173696
Short name T112
Test name
Test status
Simulation time 514924495 ps
CPU time 0.74 seconds
Started Jun 26 06:30:23 PM PDT 24
Finished Jun 26 06:30:28 PM PDT 24
Peak memory 201568 kb
Host smart-f68a8e35-5da7-4d62-be23-fb721dcb0955
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388173696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3388173696
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.3305555219
Short name T776
Test name
Test status
Simulation time 342144720653 ps
CPU time 411.91 seconds
Started Jun 26 06:30:22 PM PDT 24
Finished Jun 26 06:37:18 PM PDT 24
Peak memory 201796 kb
Host smart-5845429c-664c-47e3-876e-33971fd2f444
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305555219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.3305555219
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3265806286
Short name T603
Test name
Test status
Simulation time 329660514442 ps
CPU time 198.79 seconds
Started Jun 26 06:30:19 PM PDT 24
Finished Jun 26 06:33:41 PM PDT 24
Peak memory 201776 kb
Host smart-78041f3b-2eae-45cf-a8db-dc51571462b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265806286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3265806286
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.26189116
Short name T162
Test name
Test status
Simulation time 330756130601 ps
CPU time 110.43 seconds
Started Jun 26 06:30:13 PM PDT 24
Finished Jun 26 06:32:05 PM PDT 24
Peak memory 201952 kb
Host smart-38d654a1-18bc-4a9c-b09e-e02f2765c91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26189116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.26189116
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.321385365
Short name T482
Test name
Test status
Simulation time 334813794013 ps
CPU time 321.7 seconds
Started Jun 26 06:30:15 PM PDT 24
Finished Jun 26 06:35:38 PM PDT 24
Peak memory 201960 kb
Host smart-c96bd0a4-325f-4536-b79e-80d40f597d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321385365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.321385365
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2236906767
Short name T350
Test name
Test status
Simulation time 493799341919 ps
CPU time 1145.13 seconds
Started Jun 26 06:30:19 PM PDT 24
Finished Jun 26 06:49:28 PM PDT 24
Peak memory 201904 kb
Host smart-f46091a9-a41b-4fc9-931b-2135056acced
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236906767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2236906767
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.3804927214
Short name T317
Test name
Test status
Simulation time 169835986007 ps
CPU time 164.55 seconds
Started Jun 26 06:30:12 PM PDT 24
Finished Jun 26 06:32:58 PM PDT 24
Peak memory 201868 kb
Host smart-f19208a7-e941-4ad9-9195-70a2227cecf3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804927214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.3804927214
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3159645675
Short name T765
Test name
Test status
Simulation time 404364600044 ps
CPU time 853.26 seconds
Started Jun 26 06:30:14 PM PDT 24
Finished Jun 26 06:44:29 PM PDT 24
Peak memory 201872 kb
Host smart-a2946c96-c318-49f8-9b62-5aff0736dad1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159645675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.3159645675
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.3437153458
Short name T199
Test name
Test status
Simulation time 126005186599 ps
CPU time 444.36 seconds
Started Jun 26 06:30:12 PM PDT 24
Finished Jun 26 06:37:38 PM PDT 24
Peak memory 202224 kb
Host smart-53f303e6-6fd8-4ee7-93e9-08ea2b2900b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437153458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.3437153458
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.4093319306
Short name T557
Test name
Test status
Simulation time 28111740726 ps
CPU time 16.74 seconds
Started Jun 26 06:30:21 PM PDT 24
Finished Jun 26 06:30:42 PM PDT 24
Peak memory 201656 kb
Host smart-d094c621-7bdf-492f-9025-91c0dfac315f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093319306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.4093319306
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2392509767
Short name T598
Test name
Test status
Simulation time 4254954388 ps
CPU time 1.9 seconds
Started Jun 26 06:30:20 PM PDT 24
Finished Jun 26 06:30:26 PM PDT 24
Peak memory 201704 kb
Host smart-493ac257-1fa4-40a1-bc62-a6f45539f5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392509767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2392509767
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.1334681597
Short name T417
Test name
Test status
Simulation time 5738186253 ps
CPU time 2.45 seconds
Started Jun 26 06:30:12 PM PDT 24
Finished Jun 26 06:30:16 PM PDT 24
Peak memory 201628 kb
Host smart-b3ef4253-3c57-47fa-807c-68fd265369ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334681597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1334681597
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.712207445
Short name T55
Test name
Test status
Simulation time 8988886484 ps
CPU time 3.55 seconds
Started Jun 26 06:30:19 PM PDT 24
Finished Jun 26 06:30:27 PM PDT 24
Peak memory 201696 kb
Host smart-6f6e9f79-531a-4eb6-8705-28156bc15f7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712207445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.
712207445
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.4246266425
Short name T658
Test name
Test status
Simulation time 547731721 ps
CPU time 0.79 seconds
Started Jun 26 06:30:16 PM PDT 24
Finished Jun 26 06:30:19 PM PDT 24
Peak memory 201612 kb
Host smart-91487a12-48bf-4aff-aacf-00425149e4b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246266425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.4246266425
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.3438692155
Short name T718
Test name
Test status
Simulation time 185824907212 ps
CPU time 62.29 seconds
Started Jun 26 06:30:16 PM PDT 24
Finished Jun 26 06:31:22 PM PDT 24
Peak memory 201876 kb
Host smart-27519e34-183f-4bce-b69c-f6121ebe2272
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438692155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.3438692155
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.1367396574
Short name T640
Test name
Test status
Simulation time 158843286645 ps
CPU time 98.26 seconds
Started Jun 26 06:30:22 PM PDT 24
Finished Jun 26 06:32:04 PM PDT 24
Peak memory 201828 kb
Host smart-53c46f7c-9cdd-45da-9079-51ad99e42002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367396574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1367396574
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.4220456528
Short name T673
Test name
Test status
Simulation time 490178768866 ps
CPU time 1224.85 seconds
Started Jun 26 06:30:16 PM PDT 24
Finished Jun 26 06:50:44 PM PDT 24
Peak memory 201944 kb
Host smart-bfccff3a-94dc-4b18-b7ea-b42c033d6d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220456528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.4220456528
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2186845987
Short name T743
Test name
Test status
Simulation time 333608377287 ps
CPU time 53.98 seconds
Started Jun 26 06:30:16 PM PDT 24
Finished Jun 26 06:31:13 PM PDT 24
Peak memory 201860 kb
Host smart-20c377c2-730a-4dcd-ba1c-4e557ca78f55
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186845987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2186845987
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3462810111
Short name T518
Test name
Test status
Simulation time 327573990199 ps
CPU time 156.79 seconds
Started Jun 26 06:30:24 PM PDT 24
Finished Jun 26 06:33:05 PM PDT 24
Peak memory 201840 kb
Host smart-0bb535b1-be0c-4bd6-89c9-25e6aba7923e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462810111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3462810111
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3211265725
Short name T777
Test name
Test status
Simulation time 484244822399 ps
CPU time 269.86 seconds
Started Jun 26 06:30:25 PM PDT 24
Finished Jun 26 06:34:59 PM PDT 24
Peak memory 201788 kb
Host smart-777a6cb9-57af-4ece-bb75-3f70db184fde
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211265725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3211265725
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.1402735900
Short name T430
Test name
Test status
Simulation time 596783668054 ps
CPU time 647.08 seconds
Started Jun 26 06:30:24 PM PDT 24
Finished Jun 26 06:41:16 PM PDT 24
Peak memory 201716 kb
Host smart-1996a9d1-3dfa-459d-97bc-da86eae27acb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402735900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.1402735900
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.1612749557
Short name T516
Test name
Test status
Simulation time 41454044731 ps
CPU time 24.97 seconds
Started Jun 26 06:30:16 PM PDT 24
Finished Jun 26 06:30:44 PM PDT 24
Peak memory 201568 kb
Host smart-7bc4cf71-750d-48fd-b889-d052b8028a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612749557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.1612749557
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.4000514860
Short name T590
Test name
Test status
Simulation time 5618808167 ps
CPU time 3.71 seconds
Started Jun 26 06:30:17 PM PDT 24
Finished Jun 26 06:30:23 PM PDT 24
Peak memory 201668 kb
Host smart-b1bfad65-c9f9-4fcd-8670-33f84b10d806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000514860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.4000514860
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.1231385689
Short name T674
Test name
Test status
Simulation time 5751459390 ps
CPU time 13.21 seconds
Started Jun 26 06:30:19 PM PDT 24
Finished Jun 26 06:30:36 PM PDT 24
Peak memory 201660 kb
Host smart-716bb062-c184-41a9-b109-c66e28fbbb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231385689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.1231385689
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1719814735
Short name T541
Test name
Test status
Simulation time 179164554119 ps
CPU time 471.65 seconds
Started Jun 26 06:30:19 PM PDT 24
Finished Jun 26 06:38:21 PM PDT 24
Peak memory 210520 kb
Host smart-d89d14f6-bcab-4a2a-8bd3-c1a13cb14358
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719814735 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.1719814735
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.819748101
Short name T370
Test name
Test status
Simulation time 505867283 ps
CPU time 0.91 seconds
Started Jun 26 06:30:30 PM PDT 24
Finished Jun 26 06:30:36 PM PDT 24
Peak memory 201532 kb
Host smart-f61efa5c-c0cb-4d4a-9a8d-e5b508fce5a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819748101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.819748101
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2525054017
Short name T289
Test name
Test status
Simulation time 511798168674 ps
CPU time 262.64 seconds
Started Jun 26 06:30:21 PM PDT 24
Finished Jun 26 06:34:48 PM PDT 24
Peak memory 201880 kb
Host smart-60c3c5cb-fa59-437c-b6c8-f4e58b7a1806
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525054017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2525054017
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.2563460945
Short name T219
Test name
Test status
Simulation time 329014053051 ps
CPU time 399.13 seconds
Started Jun 26 06:30:20 PM PDT 24
Finished Jun 26 06:37:02 PM PDT 24
Peak memory 202096 kb
Host smart-3264cc1a-38e7-439f-8ca5-7de8fa2f79c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563460945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2563460945
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.608574627
Short name T607
Test name
Test status
Simulation time 163243645825 ps
CPU time 351.44 seconds
Started Jun 26 06:30:19 PM PDT 24
Finished Jun 26 06:36:15 PM PDT 24
Peak memory 201820 kb
Host smart-6ba5760f-d3c4-494c-bab2-c7148b30f784
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=608574627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrup
t_fixed.608574627
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1291732820
Short name T599
Test name
Test status
Simulation time 336280160242 ps
CPU time 129.82 seconds
Started Jun 26 06:30:20 PM PDT 24
Finished Jun 26 06:32:34 PM PDT 24
Peak memory 201932 kb
Host smart-11722e76-6d8b-4243-8658-037e8903d0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291732820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1291732820
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.1243359896
Short name T548
Test name
Test status
Simulation time 166485644430 ps
CPU time 369.49 seconds
Started Jun 26 06:30:21 PM PDT 24
Finished Jun 26 06:36:34 PM PDT 24
Peak memory 201832 kb
Host smart-7c128f15-2eae-4097-98ac-da9b432066f0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243359896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.1243359896
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.98961833
Short name T257
Test name
Test status
Simulation time 161331379390 ps
CPU time 91.31 seconds
Started Jun 26 06:30:23 PM PDT 24
Finished Jun 26 06:31:58 PM PDT 24
Peak memory 201884 kb
Host smart-bd9c4775-42fc-4d4e-81a7-686e76d12bbc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98961833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_w
akeup.98961833
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2079223215
Short name T114
Test name
Test status
Simulation time 390238721040 ps
CPU time 230.8 seconds
Started Jun 26 06:30:22 PM PDT 24
Finished Jun 26 06:34:17 PM PDT 24
Peak memory 201856 kb
Host smart-f8b26dc6-887d-4f0e-a3e3-1a4eee14f5bf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079223215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.2079223215
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1743136003
Short name T203
Test name
Test status
Simulation time 82654756256 ps
CPU time 307.74 seconds
Started Jun 26 06:30:27 PM PDT 24
Finished Jun 26 06:35:40 PM PDT 24
Peak memory 202152 kb
Host smart-4e59465d-333d-44ef-a240-b4ace80bde0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743136003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1743136003
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.420337603
Short name T531
Test name
Test status
Simulation time 32886599900 ps
CPU time 19.8 seconds
Started Jun 26 06:30:21 PM PDT 24
Finished Jun 26 06:30:45 PM PDT 24
Peak memory 201676 kb
Host smart-d9753d2e-561a-40cc-9d72-4c6fedcc76f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420337603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.420337603
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.2846401813
Short name T416
Test name
Test status
Simulation time 5180942292 ps
CPU time 3.23 seconds
Started Jun 26 06:30:19 PM PDT 24
Finished Jun 26 06:30:25 PM PDT 24
Peak memory 201680 kb
Host smart-eb1c13bf-7d85-4278-a518-125a037d4f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846401813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2846401813
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.398679041
Short name T394
Test name
Test status
Simulation time 6040571462 ps
CPU time 4.67 seconds
Started Jun 26 06:30:19 PM PDT 24
Finished Jun 26 06:30:28 PM PDT 24
Peak memory 201664 kb
Host smart-ee1ddfc2-d86c-4961-86b0-8ee3e6270bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398679041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.398679041
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3261154913
Short name T157
Test name
Test status
Simulation time 360810031111 ps
CPU time 241.18 seconds
Started Jun 26 06:30:26 PM PDT 24
Finished Jun 26 06:34:33 PM PDT 24
Peak memory 201944 kb
Host smart-d9f6fd0c-bede-4900-8dae-da2c89a976d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261154913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3261154913
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1733918428
Short name T38
Test name
Test status
Simulation time 63295750496 ps
CPU time 166.3 seconds
Started Jun 26 06:30:29 PM PDT 24
Finished Jun 26 06:33:20 PM PDT 24
Peak memory 210480 kb
Host smart-abf7be65-de21-47ce-a20d-265976b59689
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733918428 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.1733918428
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.3004040019
Short name T383
Test name
Test status
Simulation time 380507544 ps
CPU time 0.81 seconds
Started Jun 26 06:30:26 PM PDT 24
Finished Jun 26 06:30:32 PM PDT 24
Peak memory 201628 kb
Host smart-e3daf40b-6df6-4ffa-9583-c1349a175455
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004040019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.3004040019
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.769477332
Short name T462
Test name
Test status
Simulation time 490415552235 ps
CPU time 1132.34 seconds
Started Jun 26 06:30:17 PM PDT 24
Finished Jun 26 06:49:13 PM PDT 24
Peak memory 201868 kb
Host smart-5b1d42c4-482d-44bb-91f9-7b4e96811777
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=769477332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrup
t_fixed.769477332
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.119807547
Short name T197
Test name
Test status
Simulation time 164426822722 ps
CPU time 367.67 seconds
Started Jun 26 06:30:23 PM PDT 24
Finished Jun 26 06:36:34 PM PDT 24
Peak memory 201880 kb
Host smart-d217f8de-d3ee-477a-ad94-137cd774f763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119807547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.119807547
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.408528182
Short name T770
Test name
Test status
Simulation time 322930259255 ps
CPU time 349.82 seconds
Started Jun 26 06:30:26 PM PDT 24
Finished Jun 26 06:36:20 PM PDT 24
Peak memory 201884 kb
Host smart-e49df7c6-166a-4b4a-a1cc-465e20c0a945
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=408528182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixe
d.408528182
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.2984087041
Short name T181
Test name
Test status
Simulation time 510385016044 ps
CPU time 337.16 seconds
Started Jun 26 06:30:20 PM PDT 24
Finished Jun 26 06:36:01 PM PDT 24
Peak memory 201928 kb
Host smart-33f9adf9-2f9b-4ef7-a57e-9c0e05125322
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984087041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.2984087041
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2461298830
Short name T172
Test name
Test status
Simulation time 616736854490 ps
CPU time 278.99 seconds
Started Jun 26 06:30:25 PM PDT 24
Finished Jun 26 06:35:09 PM PDT 24
Peak memory 201848 kb
Host smart-cb455ea6-1533-4827-b21e-bb480449795c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461298830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.2461298830
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.2623411799
Short name T734
Test name
Test status
Simulation time 108898009546 ps
CPU time 374.3 seconds
Started Jun 26 06:30:29 PM PDT 24
Finished Jun 26 06:36:48 PM PDT 24
Peak memory 202156 kb
Host smart-274af380-eeb1-43a4-a6f6-4f2f5416e1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623411799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.2623411799
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3086050754
Short name T403
Test name
Test status
Simulation time 38899671306 ps
CPU time 83.57 seconds
Started Jun 26 06:30:25 PM PDT 24
Finished Jun 26 06:31:54 PM PDT 24
Peak memory 201680 kb
Host smart-33f3b2fe-b685-4b03-82dd-3ea334522f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086050754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3086050754
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.2284315714
Short name T552
Test name
Test status
Simulation time 4000844597 ps
CPU time 4.91 seconds
Started Jun 26 06:30:23 PM PDT 24
Finished Jun 26 06:30:32 PM PDT 24
Peak memory 201624 kb
Host smart-fb473422-50e2-4cef-84a8-14c5f5051eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284315714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.2284315714
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.179745418
Short name T366
Test name
Test status
Simulation time 6089189647 ps
CPU time 7.79 seconds
Started Jun 26 06:30:26 PM PDT 24
Finished Jun 26 06:30:39 PM PDT 24
Peak memory 201624 kb
Host smart-5078543b-ec72-4cbd-99d9-adad5daba308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179745418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.179745418
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2285925315
Short name T5
Test name
Test status
Simulation time 71938354634 ps
CPU time 275.07 seconds
Started Jun 26 06:30:24 PM PDT 24
Finished Jun 26 06:35:04 PM PDT 24
Peak memory 202236 kb
Host smart-1371f51f-cb3d-4e89-9718-374adeed62ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285925315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2285925315
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.4092815575
Short name T120
Test name
Test status
Simulation time 117144560119 ps
CPU time 132.35 seconds
Started Jun 26 06:30:21 PM PDT 24
Finished Jun 26 06:32:37 PM PDT 24
Peak memory 210264 kb
Host smart-aa0cd2a5-087c-4b83-ba40-c698cbb25e3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092815575 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.4092815575
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.559005107
Short name T687
Test name
Test status
Simulation time 470037538 ps
CPU time 1.2 seconds
Started Jun 26 06:30:25 PM PDT 24
Finished Jun 26 06:30:35 PM PDT 24
Peak memory 201568 kb
Host smart-9690989d-ff1c-4e70-bc4d-e982f6e5d139
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559005107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.559005107
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1907634743
Short name T609
Test name
Test status
Simulation time 162033376115 ps
CPU time 351.05 seconds
Started Jun 26 06:30:19 PM PDT 24
Finished Jun 26 06:36:14 PM PDT 24
Peak memory 201940 kb
Host smart-0697733b-fe0b-4a0b-bae7-c6a0c05fd24b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907634743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1907634743
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.2252098784
Short name T101
Test name
Test status
Simulation time 343906020073 ps
CPU time 62.39 seconds
Started Jun 26 06:30:27 PM PDT 24
Finished Jun 26 06:31:35 PM PDT 24
Peak memory 201900 kb
Host smart-48a48b6f-da36-4759-9273-afe4d85847a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252098784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.2252098784
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.2133283233
Short name T191
Test name
Test status
Simulation time 491529486911 ps
CPU time 293.11 seconds
Started Jun 26 06:30:26 PM PDT 24
Finished Jun 26 06:35:24 PM PDT 24
Peak memory 201880 kb
Host smart-deff01b1-e083-4fdb-a1bc-ed68524ef946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133283233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2133283233
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3696576677
Short name T368
Test name
Test status
Simulation time 494393535126 ps
CPU time 836.67 seconds
Started Jun 26 06:30:26 PM PDT 24
Finished Jun 26 06:44:28 PM PDT 24
Peak memory 201840 kb
Host smart-0ff82cce-adc5-4edb-812c-2cf091538b42
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696576677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.3696576677
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2173507724
Short name T510
Test name
Test status
Simulation time 494354739074 ps
CPU time 286.55 seconds
Started Jun 26 06:30:26 PM PDT 24
Finished Jun 26 06:35:18 PM PDT 24
Peak memory 201972 kb
Host smart-401ff3a1-5f38-492f-bb2d-23d5ac60e092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173507724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2173507724
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.3081863611
Short name T411
Test name
Test status
Simulation time 167083347671 ps
CPU time 351.86 seconds
Started Jun 26 06:30:25 PM PDT 24
Finished Jun 26 06:36:20 PM PDT 24
Peak memory 201848 kb
Host smart-39be767c-c5af-4cb8-9b9c-c9c401ffc840
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081863611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.3081863611
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.701874165
Short name T452
Test name
Test status
Simulation time 196133582449 ps
CPU time 461.39 seconds
Started Jun 26 06:30:27 PM PDT 24
Finished Jun 26 06:38:13 PM PDT 24
Peak memory 201860 kb
Host smart-4aad5ae1-44ae-4b94-a12d-27ea5db973cc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701874165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
adc_ctrl_filters_wakeup_fixed.701874165
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.4053669546
Short name T204
Test name
Test status
Simulation time 101509377464 ps
CPU time 472.03 seconds
Started Jun 26 06:30:29 PM PDT 24
Finished Jun 26 06:38:26 PM PDT 24
Peak memory 202212 kb
Host smart-425f91ad-55c2-4cb9-a137-46b7a0a41f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053669546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.4053669546
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.566620126
Short name T625
Test name
Test status
Simulation time 41612110852 ps
CPU time 88.24 seconds
Started Jun 26 06:30:27 PM PDT 24
Finished Jun 26 06:32:01 PM PDT 24
Peak memory 201708 kb
Host smart-feac5353-b295-42b9-9541-4367f75d2003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566620126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.566620126
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.1877570644
Short name T684
Test name
Test status
Simulation time 4062914889 ps
CPU time 10.94 seconds
Started Jun 26 06:30:21 PM PDT 24
Finished Jun 26 06:30:36 PM PDT 24
Peak memory 201688 kb
Host smart-68bc6060-723c-4901-ab11-a055da7fba23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877570644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.1877570644
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.1149612049
Short name T651
Test name
Test status
Simulation time 5674899320 ps
CPU time 13.15 seconds
Started Jun 26 06:30:26 PM PDT 24
Finished Jun 26 06:30:44 PM PDT 24
Peak memory 201700 kb
Host smart-04548540-0c7e-482c-b725-b70be08f7e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149612049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1149612049
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.3206704167
Short name T74
Test name
Test status
Simulation time 326686787165 ps
CPU time 182.89 seconds
Started Jun 26 06:30:27 PM PDT 24
Finished Jun 26 06:33:35 PM PDT 24
Peak memory 201868 kb
Host smart-16ad603a-33ab-4b73-b837-eb008577a81a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206704167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.3206704167
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.513867373
Short name T314
Test name
Test status
Simulation time 22092027260 ps
CPU time 48.19 seconds
Started Jun 26 06:30:31 PM PDT 24
Finished Jun 26 06:31:24 PM PDT 24
Peak memory 211796 kb
Host smart-c352f2dc-12c1-4652-83f4-3d3051f2ffd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513867373 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.513867373
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2719932518
Short name T415
Test name
Test status
Simulation time 446112722 ps
CPU time 0.87 seconds
Started Jun 26 06:30:28 PM PDT 24
Finished Jun 26 06:30:34 PM PDT 24
Peak memory 201560 kb
Host smart-40daa5ba-611c-4a14-aaaf-7091e5dcccf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719932518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2719932518
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.2532740763
Short name T59
Test name
Test status
Simulation time 333610719622 ps
CPU time 164.12 seconds
Started Jun 26 06:30:20 PM PDT 24
Finished Jun 26 06:33:09 PM PDT 24
Peak memory 201852 kb
Host smart-92ff1074-4043-4e82-855f-32c95434fbc5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532740763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.2532740763
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.402723504
Short name T183
Test name
Test status
Simulation time 502023830762 ps
CPU time 144.95 seconds
Started Jun 26 06:30:40 PM PDT 24
Finished Jun 26 06:33:07 PM PDT 24
Peak memory 201816 kb
Host smart-11615ec6-bbf2-48ba-ac9c-02b91db1b4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402723504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.402723504
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.4195815411
Short name T646
Test name
Test status
Simulation time 489202007609 ps
CPU time 303.77 seconds
Started Jun 26 06:30:25 PM PDT 24
Finished Jun 26 06:35:33 PM PDT 24
Peak memory 201824 kb
Host smart-5a85cd76-e959-4e7c-86d3-b424fa724fe4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195815411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.4195815411
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2244158005
Short name T565
Test name
Test status
Simulation time 501035117818 ps
CPU time 1055.18 seconds
Started Jun 26 06:30:34 PM PDT 24
Finished Jun 26 06:48:13 PM PDT 24
Peak memory 201844 kb
Host smart-e597faa8-1e12-4327-bc19-d9dd709e7655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244158005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2244158005
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.920565783
Short name T484
Test name
Test status
Simulation time 161711336591 ps
CPU time 376.57 seconds
Started Jun 26 06:30:28 PM PDT 24
Finished Jun 26 06:36:50 PM PDT 24
Peak memory 201884 kb
Host smart-d180108e-9092-4314-aca2-b251d1f4de57
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=920565783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.920565783
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.3106525331
Short name T703
Test name
Test status
Simulation time 354737733149 ps
CPU time 384.08 seconds
Started Jun 26 06:30:23 PM PDT 24
Finished Jun 26 06:36:51 PM PDT 24
Peak memory 201884 kb
Host smart-87f67564-e75e-4902-a5b9-3342cda2bd5e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106525331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.3106525331
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.614319333
Short name T595
Test name
Test status
Simulation time 611057782296 ps
CPU time 754.28 seconds
Started Jun 26 06:30:27 PM PDT 24
Finished Jun 26 06:43:06 PM PDT 24
Peak memory 201856 kb
Host smart-f3868418-0202-41a0-9f03-585ff43818cc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614319333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
adc_ctrl_filters_wakeup_fixed.614319333
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2698827372
Short name T578
Test name
Test status
Simulation time 97612129839 ps
CPU time 436.95 seconds
Started Jun 26 06:30:22 PM PDT 24
Finished Jun 26 06:37:43 PM PDT 24
Peak memory 202272 kb
Host smart-b6fa0b37-544e-47e7-a2d9-761bfc987356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698827372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2698827372
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.425946973
Short name T425
Test name
Test status
Simulation time 27182243580 ps
CPU time 13.56 seconds
Started Jun 26 06:30:24 PM PDT 24
Finished Jun 26 06:30:42 PM PDT 24
Peak memory 201660 kb
Host smart-1f13a4bc-24c3-41af-b39b-4c6aa1d7df29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425946973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.425946973
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1308465887
Short name T356
Test name
Test status
Simulation time 2875102290 ps
CPU time 3.2 seconds
Started Jun 26 06:30:29 PM PDT 24
Finished Jun 26 06:30:37 PM PDT 24
Peak memory 201616 kb
Host smart-e25e653c-b9c8-4e30-999c-05fe6d4901d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308465887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1308465887
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1888516014
Short name T423
Test name
Test status
Simulation time 5970487731 ps
CPU time 3.97 seconds
Started Jun 26 06:30:26 PM PDT 24
Finished Jun 26 06:30:35 PM PDT 24
Peak memory 201676 kb
Host smart-e8c0feda-8255-4610-a458-9ae2ed0d51cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888516014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1888516014
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2407104218
Short name T49
Test name
Test status
Simulation time 119043757624 ps
CPU time 311.61 seconds
Started Jun 26 06:30:23 PM PDT 24
Finished Jun 26 06:35:38 PM PDT 24
Peak memory 210396 kb
Host smart-c511343f-95e1-48dc-bfad-0c9acb9d96a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407104218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2407104218
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.869311711
Short name T106
Test name
Test status
Simulation time 499359322 ps
CPU time 0.86 seconds
Started Jun 26 06:30:44 PM PDT 24
Finished Jun 26 06:30:46 PM PDT 24
Peak memory 201620 kb
Host smart-310b481c-9c7f-44df-9cfb-d534acdc0670
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869311711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.869311711
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2056413282
Short name T274
Test name
Test status
Simulation time 168821173381 ps
CPU time 99.61 seconds
Started Jun 26 06:30:24 PM PDT 24
Finished Jun 26 06:32:07 PM PDT 24
Peak memory 201868 kb
Host smart-90915a0f-496f-4a66-b384-0a62ec9b67c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056413282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2056413282
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.3117328913
Short name T441
Test name
Test status
Simulation time 161700969234 ps
CPU time 370.65 seconds
Started Jun 26 06:30:24 PM PDT 24
Finished Jun 26 06:36:39 PM PDT 24
Peak memory 202092 kb
Host smart-b188928a-b3f7-4a59-8b94-f512fcc8cd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117328913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.3117328913
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.4169026689
Short name T381
Test name
Test status
Simulation time 333077310276 ps
CPU time 636.82 seconds
Started Jun 26 06:30:48 PM PDT 24
Finished Jun 26 06:41:26 PM PDT 24
Peak memory 201800 kb
Host smart-6febb317-afbc-4346-92de-543dc0527192
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169026689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.4169026689
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.3348631049
Short name T483
Test name
Test status
Simulation time 322679626758 ps
CPU time 726.25 seconds
Started Jun 26 06:30:30 PM PDT 24
Finished Jun 26 06:42:41 PM PDT 24
Peak memory 201884 kb
Host smart-55930c27-076f-47cd-a7bf-b066abb2ed6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348631049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.3348631049
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.650153679
Short name T635
Test name
Test status
Simulation time 489886250982 ps
CPU time 1144.85 seconds
Started Jun 26 06:30:27 PM PDT 24
Finished Jun 26 06:49:42 PM PDT 24
Peak memory 201896 kb
Host smart-35edfb82-8138-41af-bdba-80b9f12816a9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=650153679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixe
d.650153679
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.4249298070
Short name T222
Test name
Test status
Simulation time 538341667185 ps
CPU time 1181.06 seconds
Started Jun 26 06:30:27 PM PDT 24
Finished Jun 26 06:50:17 PM PDT 24
Peak memory 201980 kb
Host smart-89fc5864-47f5-452c-8d16-72a61beb26cc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249298070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.4249298070
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2213267456
Short name T659
Test name
Test status
Simulation time 208204786184 ps
CPU time 114.4 seconds
Started Jun 26 06:30:28 PM PDT 24
Finished Jun 26 06:32:28 PM PDT 24
Peak memory 201788 kb
Host smart-1af27847-977c-4df8-84b3-5cf812740ac5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213267456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2213267456
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1755382064
Short name T208
Test name
Test status
Simulation time 75627407960 ps
CPU time 288.16 seconds
Started Jun 26 06:30:33 PM PDT 24
Finished Jun 26 06:35:25 PM PDT 24
Peak memory 202468 kb
Host smart-70aa3d10-84c3-4d0a-9176-9b81fda18dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755382064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1755382064
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3918350305
Short name T769
Test name
Test status
Simulation time 27177153008 ps
CPU time 41.2 seconds
Started Jun 26 06:30:44 PM PDT 24
Finished Jun 26 06:31:26 PM PDT 24
Peak memory 201676 kb
Host smart-6ccc90f7-828c-489a-9cee-5905ce9e2ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918350305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3918350305
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.1152131271
Short name T95
Test name
Test status
Simulation time 5327118628 ps
CPU time 4.68 seconds
Started Jun 26 06:30:26 PM PDT 24
Finished Jun 26 06:30:35 PM PDT 24
Peak memory 201644 kb
Host smart-2a956e18-b546-431a-8f9c-98fb9b70ac9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152131271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1152131271
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.406930422
Short name T762
Test name
Test status
Simulation time 5681813450 ps
CPU time 3.7 seconds
Started Jun 26 06:30:24 PM PDT 24
Finished Jun 26 06:30:31 PM PDT 24
Peak memory 201672 kb
Host smart-7c2a10d3-c79f-4a69-af30-cb7126f88f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406930422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.406930422
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.4211557682
Short name T324
Test name
Test status
Simulation time 475261984532 ps
CPU time 595.12 seconds
Started Jun 26 06:30:28 PM PDT 24
Finished Jun 26 06:40:28 PM PDT 24
Peak memory 212904 kb
Host smart-d29c04b3-7a33-4e83-a192-3fceb72dc641
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211557682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.4211557682
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.3950624402
Short name T568
Test name
Test status
Simulation time 322779302 ps
CPU time 0.8 seconds
Started Jun 26 06:30:28 PM PDT 24
Finished Jun 26 06:30:34 PM PDT 24
Peak memory 201632 kb
Host smart-e561aa71-5fc9-4c17-a82e-1f9281bae177
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950624402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3950624402
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.1946516165
Short name T304
Test name
Test status
Simulation time 342136650852 ps
CPU time 183.42 seconds
Started Jun 26 06:30:28 PM PDT 24
Finished Jun 26 06:33:37 PM PDT 24
Peak memory 201880 kb
Host smart-98131c78-3a63-4159-8db9-da4c5a4bdf20
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946516165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.1946516165
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.375488816
Short name T166
Test name
Test status
Simulation time 161313241731 ps
CPU time 369.11 seconds
Started Jun 26 06:30:36 PM PDT 24
Finished Jun 26 06:36:49 PM PDT 24
Peak memory 201876 kb
Host smart-667ebc7d-c226-498e-86f9-8fc779153330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375488816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.375488816
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2001605618
Short name T551
Test name
Test status
Simulation time 320547018723 ps
CPU time 190.52 seconds
Started Jun 26 06:30:29 PM PDT 24
Finished Jun 26 06:33:44 PM PDT 24
Peak memory 201836 kb
Host smart-a3a744fb-9d76-4295-b130-a65b840d28ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001605618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.2001605618
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.2040823145
Short name T447
Test name
Test status
Simulation time 170054685543 ps
CPU time 206.74 seconds
Started Jun 26 06:30:28 PM PDT 24
Finished Jun 26 06:34:00 PM PDT 24
Peak memory 201660 kb
Host smart-63b2d2d2-5c8c-4b2b-bce2-c5cd44cc4447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040823145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.2040823145
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.2078695224
Short name T171
Test name
Test status
Simulation time 338132838697 ps
CPU time 217.38 seconds
Started Jun 26 06:30:43 PM PDT 24
Finished Jun 26 06:34:22 PM PDT 24
Peak memory 201860 kb
Host smart-959b3a7c-c0e1-4fa0-9105-e366ab0feb8e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078695224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.2078695224
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3796170762
Short name T745
Test name
Test status
Simulation time 168255435101 ps
CPU time 99.61 seconds
Started Jun 26 06:30:36 PM PDT 24
Finished Jun 26 06:32:19 PM PDT 24
Peak memory 201908 kb
Host smart-d2cc1307-6c73-4a7b-8c70-a475def93953
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796170762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3796170762
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.67955332
Short name T554
Test name
Test status
Simulation time 204170844905 ps
CPU time 483.71 seconds
Started Jun 26 06:30:45 PM PDT 24
Finished Jun 26 06:38:50 PM PDT 24
Peak memory 201868 kb
Host smart-a909923d-1326-4e7f-ac30-6466e516f677
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67955332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.a
dc_ctrl_filters_wakeup_fixed.67955332
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.1547270729
Short name T751
Test name
Test status
Simulation time 131301507168 ps
CPU time 643.26 seconds
Started Jun 26 06:30:29 PM PDT 24
Finished Jun 26 06:41:18 PM PDT 24
Peak memory 202200 kb
Host smart-d4cd8f45-ba98-4450-9f48-3362202b1bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547270729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1547270729
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.3118568642
Short name T533
Test name
Test status
Simulation time 29114448945 ps
CPU time 14.71 seconds
Started Jun 26 06:30:41 PM PDT 24
Finished Jun 26 06:30:57 PM PDT 24
Peak memory 201708 kb
Host smart-a137c187-5259-4e4d-9f18-4c5aa246a219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118568642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.3118568642
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.4254812743
Short name T408
Test name
Test status
Simulation time 4456048659 ps
CPU time 2.95 seconds
Started Jun 26 06:30:27 PM PDT 24
Finished Jun 26 06:30:35 PM PDT 24
Peak memory 201672 kb
Host smart-f1306449-2a48-49a5-8382-5c994de27db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254812743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.4254812743
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.3799850223
Short name T406
Test name
Test status
Simulation time 5988699278 ps
CPU time 13.76 seconds
Started Jun 26 06:30:28 PM PDT 24
Finished Jun 26 06:30:47 PM PDT 24
Peak memory 201676 kb
Host smart-e06690a0-d5cb-487f-b943-045e195a04b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799850223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3799850223
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.2880314319
Short name T176
Test name
Test status
Simulation time 489374747705 ps
CPU time 592.51 seconds
Started Jun 26 06:30:28 PM PDT 24
Finished Jun 26 06:40:25 PM PDT 24
Peak memory 201884 kb
Host smart-42cf28e6-3c9a-4832-8811-f09fa4353f2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880314319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.2880314319
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.289774986
Short name T258
Test name
Test status
Simulation time 594047411706 ps
CPU time 398.38 seconds
Started Jun 26 06:30:43 PM PDT 24
Finished Jun 26 06:37:22 PM PDT 24
Peak memory 210572 kb
Host smart-1d93c21c-8a4f-4cc2-ac6c-7c4622180d5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289774986 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.289774986
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.3727571082
Short name T354
Test name
Test status
Simulation time 397235075 ps
CPU time 1.51 seconds
Started Jun 26 06:30:14 PM PDT 24
Finished Jun 26 06:30:18 PM PDT 24
Peak memory 201608 kb
Host smart-81a94721-8023-464e-b359-9190dc9f557a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727571082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3727571082
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2201964646
Short name T9
Test name
Test status
Simulation time 327259823161 ps
CPU time 92.47 seconds
Started Jun 26 06:29:47 PM PDT 24
Finished Jun 26 06:31:22 PM PDT 24
Peak memory 201932 kb
Host smart-91f19ef9-14de-4e7a-8f10-b2eeb5bf0476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201964646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2201964646
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1869832320
Short name T472
Test name
Test status
Simulation time 496880597841 ps
CPU time 547.75 seconds
Started Jun 26 06:30:02 PM PDT 24
Finished Jun 26 06:39:11 PM PDT 24
Peak memory 201872 kb
Host smart-38ac1333-43ba-470d-ba1e-bd41a3db1859
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869832320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1869832320
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.694878174
Short name T284
Test name
Test status
Simulation time 488632424593 ps
CPU time 1096.43 seconds
Started Jun 26 06:30:11 PM PDT 24
Finished Jun 26 06:48:29 PM PDT 24
Peak memory 201888 kb
Host smart-001d0c79-f0ff-4d50-b858-0035851f71b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694878174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.694878174
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1662851878
Short name T793
Test name
Test status
Simulation time 337242957368 ps
CPU time 766.33 seconds
Started Jun 26 06:30:04 PM PDT 24
Finished Jun 26 06:42:52 PM PDT 24
Peak memory 201884 kb
Host smart-ca7cdb7a-b9ed-4217-9010-71d2b210c810
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662851878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.1662851878
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.2513338776
Short name T302
Test name
Test status
Simulation time 187467027909 ps
CPU time 103.96 seconds
Started Jun 26 06:30:05 PM PDT 24
Finished Jun 26 06:31:52 PM PDT 24
Peak memory 201904 kb
Host smart-5bf6e229-8ac8-4295-8798-18ee8c1a0fb4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513338776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.2513338776
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.764627903
Short name T731
Test name
Test status
Simulation time 596769814980 ps
CPU time 1372.41 seconds
Started Jun 26 06:29:44 PM PDT 24
Finished Jun 26 06:52:40 PM PDT 24
Peak memory 201864 kb
Host smart-e92ef396-267c-4858-b35c-9ba23b1f8161
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764627903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a
dc_ctrl_filters_wakeup_fixed.764627903
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1269305665
Short name T205
Test name
Test status
Simulation time 135489601924 ps
CPU time 471.21 seconds
Started Jun 26 06:30:07 PM PDT 24
Finished Jun 26 06:38:00 PM PDT 24
Peak memory 202200 kb
Host smart-8be80ac7-1b66-4479-a808-316ddc7fef95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269305665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1269305665
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.88789550
Short name T25
Test name
Test status
Simulation time 30718448541 ps
CPU time 17.75 seconds
Started Jun 26 06:30:17 PM PDT 24
Finished Jun 26 06:30:38 PM PDT 24
Peak memory 201664 kb
Host smart-5d453e33-0038-48bd-87a4-f91f1c5f024f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88789550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.88789550
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.364509585
Short name T380
Test name
Test status
Simulation time 3273400263 ps
CPU time 4.38 seconds
Started Jun 26 06:30:10 PM PDT 24
Finished Jun 26 06:30:16 PM PDT 24
Peak memory 201688 kb
Host smart-2919c526-7492-4b4e-86f2-b8ef666500c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364509585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.364509585
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.464412512
Short name T69
Test name
Test status
Simulation time 4111248981 ps
CPU time 10.61 seconds
Started Jun 26 06:30:14 PM PDT 24
Finished Jun 26 06:30:26 PM PDT 24
Peak memory 217108 kb
Host smart-08c79bfb-b0de-4a38-b3a8-0a9e9c8007e4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464412512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.464412512
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2542306244
Short name T86
Test name
Test status
Simulation time 5639519867 ps
CPU time 4.09 seconds
Started Jun 26 06:30:07 PM PDT 24
Finished Jun 26 06:30:13 PM PDT 24
Peak memory 201660 kb
Host smart-894953b8-5745-4522-8a6c-89c204ea7ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542306244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2542306244
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.954156751
Short name T37
Test name
Test status
Simulation time 12496123417 ps
CPU time 30.07 seconds
Started Jun 26 06:30:02 PM PDT 24
Finished Jun 26 06:30:33 PM PDT 24
Peak memory 202048 kb
Host smart-208f1303-ce66-4920-98cc-edfeb6bb1029
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954156751 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.954156751
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.541145720
Short name T422
Test name
Test status
Simulation time 362611488 ps
CPU time 0.85 seconds
Started Jun 26 06:30:28 PM PDT 24
Finished Jun 26 06:30:34 PM PDT 24
Peak memory 201436 kb
Host smart-e87790ff-b4be-48a1-964d-a977d065cd4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541145720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.541145720
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2076021394
Short name T177
Test name
Test status
Simulation time 508182347804 ps
CPU time 778.39 seconds
Started Jun 26 06:30:30 PM PDT 24
Finished Jun 26 06:43:33 PM PDT 24
Peak memory 202092 kb
Host smart-dd571b38-4bf3-41e7-8d26-028e4434fee1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076021394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2076021394
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.1561164814
Short name T485
Test name
Test status
Simulation time 164017184222 ps
CPU time 358.32 seconds
Started Jun 26 06:30:27 PM PDT 24
Finished Jun 26 06:36:31 PM PDT 24
Peak memory 201860 kb
Host smart-5bd9b620-2a02-4a9d-a65c-d81e9e2a0cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561164814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.1561164814
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.2079157895
Short name T98
Test name
Test status
Simulation time 328363890588 ps
CPU time 762.54 seconds
Started Jun 26 06:30:29 PM PDT 24
Finished Jun 26 06:43:16 PM PDT 24
Peak memory 201888 kb
Host smart-8ca6f1a8-315b-4c0f-9035-5fa679c53fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079157895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.2079157895
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.269731546
Short name T409
Test name
Test status
Simulation time 332288749606 ps
CPU time 358.81 seconds
Started Jun 26 06:30:37 PM PDT 24
Finished Jun 26 06:36:39 PM PDT 24
Peak memory 201860 kb
Host smart-8d84fe38-9269-4810-bff0-b50a1b9b456f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=269731546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrup
t_fixed.269731546
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.407494592
Short name T275
Test name
Test status
Simulation time 486273306740 ps
CPU time 1129.04 seconds
Started Jun 26 06:30:28 PM PDT 24
Finished Jun 26 06:49:22 PM PDT 24
Peak memory 201844 kb
Host smart-dd353524-3ee2-4ccb-b4d9-0ae54ebf8f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407494592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.407494592
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.930429529
Short name T664
Test name
Test status
Simulation time 496238815239 ps
CPU time 998.16 seconds
Started Jun 26 06:30:33 PM PDT 24
Finished Jun 26 06:47:15 PM PDT 24
Peak memory 201928 kb
Host smart-ef09949b-40c8-481f-ad10-7bdef2fd433a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=930429529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixe
d.930429529
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.207255622
Short name T729
Test name
Test status
Simulation time 182388853645 ps
CPU time 90.66 seconds
Started Jun 26 06:30:34 PM PDT 24
Finished Jun 26 06:32:09 PM PDT 24
Peak memory 201940 kb
Host smart-353ff53b-94a4-4237-a019-994288dfff38
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207255622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_
wakeup.207255622
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.528214321
Short name T783
Test name
Test status
Simulation time 392409795604 ps
CPU time 464.09 seconds
Started Jun 26 06:30:38 PM PDT 24
Finished Jun 26 06:38:25 PM PDT 24
Peak memory 201860 kb
Host smart-19e23753-4ab2-4ed7-87be-373469244fa5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528214321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
adc_ctrl_filters_wakeup_fixed.528214321
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.1727810836
Short name T202
Test name
Test status
Simulation time 126650596777 ps
CPU time 387.56 seconds
Started Jun 26 06:30:48 PM PDT 24
Finished Jun 26 06:37:17 PM PDT 24
Peak memory 202164 kb
Host smart-845c00fb-310a-42ae-8492-293bc2fed700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727810836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1727810836
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.2310708391
Short name T567
Test name
Test status
Simulation time 43655793735 ps
CPU time 96.04 seconds
Started Jun 26 06:30:42 PM PDT 24
Finished Jun 26 06:32:19 PM PDT 24
Peak memory 201704 kb
Host smart-a68a00bd-bbdc-4990-ae8b-ad5dbcf7f8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310708391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2310708391
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1103586600
Short name T655
Test name
Test status
Simulation time 2915667573 ps
CPU time 2.19 seconds
Started Jun 26 06:30:41 PM PDT 24
Finished Jun 26 06:30:45 PM PDT 24
Peak memory 201684 kb
Host smart-83f9bf5a-b579-49be-b3c2-21ad8c48e3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103586600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1103586600
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1168487585
Short name T686
Test name
Test status
Simulation time 5682857220 ps
CPU time 3.66 seconds
Started Jun 26 06:30:39 PM PDT 24
Finished Jun 26 06:30:45 PM PDT 24
Peak memory 201692 kb
Host smart-7e110774-19cd-4453-bdd4-90af5992040a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168487585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1168487585
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.454769015
Short name T591
Test name
Test status
Simulation time 123432368721 ps
CPU time 656.44 seconds
Started Jun 26 06:30:29 PM PDT 24
Finished Jun 26 06:41:31 PM PDT 24
Peak memory 210444 kb
Host smart-8c9b4b3e-e97b-4a3d-9604-ee8a4e686eac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454769015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.
454769015
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2303747490
Short name T19
Test name
Test status
Simulation time 34688212231 ps
CPU time 81.49 seconds
Started Jun 26 06:30:34 PM PDT 24
Finished Jun 26 06:31:59 PM PDT 24
Peak memory 218112 kb
Host smart-75f1bbc5-48d0-4b76-9b3e-e3d66c79b254
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303747490 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2303747490
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1685443975
Short name T536
Test name
Test status
Simulation time 558830708 ps
CPU time 0.87 seconds
Started Jun 26 06:30:34 PM PDT 24
Finished Jun 26 06:30:39 PM PDT 24
Peak memory 201628 kb
Host smart-8975b931-ab24-47a0-bdd0-5f9d597b313f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685443975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1685443975
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2842229537
Short name T160
Test name
Test status
Simulation time 344232959950 ps
CPU time 758.96 seconds
Started Jun 26 06:30:38 PM PDT 24
Finished Jun 26 06:43:20 PM PDT 24
Peak memory 201876 kb
Host smart-ffe09b38-9d4c-422b-8c08-21aa0bc96e1c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842229537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2842229537
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.2793873215
Short name T303
Test name
Test status
Simulation time 238956647440 ps
CPU time 133.95 seconds
Started Jun 26 06:30:33 PM PDT 24
Finished Jun 26 06:32:51 PM PDT 24
Peak memory 201900 kb
Host smart-82208b4f-481a-44ba-b7bd-8bee515e00fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793873215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2793873215
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.847590814
Short name T218
Test name
Test status
Simulation time 167922312773 ps
CPU time 207.22 seconds
Started Jun 26 06:30:33 PM PDT 24
Finished Jun 26 06:34:05 PM PDT 24
Peak memory 201936 kb
Host smart-cbf6d980-d55d-435d-a394-cfd33c1de83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847590814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.847590814
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2158867842
Short name T489
Test name
Test status
Simulation time 492109032490 ps
CPU time 235.43 seconds
Started Jun 26 06:30:30 PM PDT 24
Finished Jun 26 06:34:30 PM PDT 24
Peak memory 201820 kb
Host smart-7c2ed2c9-aa93-4e4f-a8c2-cb108b903e49
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158867842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.2158867842
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.3560586464
Short name T100
Test name
Test status
Simulation time 167773432680 ps
CPU time 64.45 seconds
Started Jun 26 06:30:28 PM PDT 24
Finished Jun 26 06:31:38 PM PDT 24
Peak memory 201908 kb
Host smart-e9a75147-39c5-41c6-9c45-aad28499a1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560586464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.3560586464
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2667344322
Short name T559
Test name
Test status
Simulation time 495492301482 ps
CPU time 1071.83 seconds
Started Jun 26 06:30:28 PM PDT 24
Finished Jun 26 06:48:25 PM PDT 24
Peak memory 201868 kb
Host smart-1a3bda29-06b7-4bf2-8160-040f39c424fe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667344322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2667344322
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.840086074
Short name T97
Test name
Test status
Simulation time 509306917251 ps
CPU time 278.81 seconds
Started Jun 26 06:30:38 PM PDT 24
Finished Jun 26 06:35:20 PM PDT 24
Peak memory 201932 kb
Host smart-eea853f5-3afe-4b2e-813d-9852fec637ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840086074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.840086074
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1415471873
Short name T771
Test name
Test status
Simulation time 403419001503 ps
CPU time 232 seconds
Started Jun 26 06:30:30 PM PDT 24
Finished Jun 26 06:34:27 PM PDT 24
Peak memory 201848 kb
Host smart-0e4a9db3-6403-44ef-a94a-fef55bd9cf46
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415471873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.1415471873
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.2915491727
Short name T742
Test name
Test status
Simulation time 93794295916 ps
CPU time 305.86 seconds
Started Jun 26 06:30:37 PM PDT 24
Finished Jun 26 06:35:46 PM PDT 24
Peak memory 202208 kb
Host smart-62a24ae0-8225-492d-8f17-8719825bd37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915491727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2915491727
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.4072613868
Short name T555
Test name
Test status
Simulation time 24444308637 ps
CPU time 49.38 seconds
Started Jun 26 06:30:34 PM PDT 24
Finished Jun 26 06:31:27 PM PDT 24
Peak memory 201620 kb
Host smart-c8c8c37a-d88e-42aa-80be-905196e2a73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072613868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.4072613868
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.1776785096
Short name T397
Test name
Test status
Simulation time 5673978057 ps
CPU time 13.98 seconds
Started Jun 26 06:30:39 PM PDT 24
Finished Jun 26 06:30:55 PM PDT 24
Peak memory 201652 kb
Host smart-aed21e62-4504-46e3-a6c5-bd9721b039ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776785096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.1776785096
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.394648380
Short name T148
Test name
Test status
Simulation time 6216968634 ps
CPU time 1.92 seconds
Started Jun 26 06:30:48 PM PDT 24
Finished Jun 26 06:30:51 PM PDT 24
Peak memory 201656 kb
Host smart-07369b0d-0859-4e75-a7fd-866b9c389e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394648380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.394648380
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.2889173372
Short name T339
Test name
Test status
Simulation time 275428344989 ps
CPU time 477.9 seconds
Started Jun 26 06:30:34 PM PDT 24
Finished Jun 26 06:38:36 PM PDT 24
Peak memory 210380 kb
Host smart-dcf7a671-9325-4197-834f-a166cc087ef1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889173372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.2889173372
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2810123752
Short name T736
Test name
Test status
Simulation time 16495998586 ps
CPU time 36.62 seconds
Started Jun 26 06:30:29 PM PDT 24
Finished Jun 26 06:31:10 PM PDT 24
Peak memory 210172 kb
Host smart-bda81831-1a30-440f-8769-1378eb65ba2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810123752 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2810123752
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.1124943704
Short name T414
Test name
Test status
Simulation time 506987076 ps
CPU time 0.96 seconds
Started Jun 26 06:30:34 PM PDT 24
Finished Jun 26 06:30:39 PM PDT 24
Peak memory 201628 kb
Host smart-49780e62-430d-448b-b5da-9479626d0831
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124943704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.1124943704
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3675115256
Short name T330
Test name
Test status
Simulation time 497115263851 ps
CPU time 186.34 seconds
Started Jun 26 06:30:36 PM PDT 24
Finished Jun 26 06:33:46 PM PDT 24
Peak memory 201888 kb
Host smart-ef90b51d-f40e-4467-9cf0-dc2ab500de0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675115256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3675115256
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.3474909536
Short name T401
Test name
Test status
Simulation time 489212570927 ps
CPU time 301.16 seconds
Started Jun 26 06:30:36 PM PDT 24
Finished Jun 26 06:35:40 PM PDT 24
Peak memory 201828 kb
Host smart-6860e9a8-b4c4-48ee-afd5-6af7273ec4c7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474909536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.3474909536
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.175438549
Short name T420
Test name
Test status
Simulation time 162996713931 ps
CPU time 78.4 seconds
Started Jun 26 06:30:48 PM PDT 24
Finished Jun 26 06:32:07 PM PDT 24
Peak memory 201972 kb
Host smart-44b024fe-1231-443b-a913-f4e13d34ed6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175438549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.175438549
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.34955173
Short name T685
Test name
Test status
Simulation time 325969773729 ps
CPU time 396.12 seconds
Started Jun 26 06:30:47 PM PDT 24
Finished Jun 26 06:37:24 PM PDT 24
Peak memory 201924 kb
Host smart-a5cf4d93-45ec-4db2-812c-bd4c10ca744b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=34955173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixed
.34955173
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2052412095
Short name T272
Test name
Test status
Simulation time 558938768235 ps
CPU time 381.46 seconds
Started Jun 26 06:30:39 PM PDT 24
Finished Jun 26 06:37:03 PM PDT 24
Peak memory 201856 kb
Host smart-4b2a3725-e277-4574-b4bc-e9aff5dab6b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052412095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2052412095
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2739145365
Short name T692
Test name
Test status
Simulation time 612101182846 ps
CPU time 715.08 seconds
Started Jun 26 06:30:36 PM PDT 24
Finished Jun 26 06:42:34 PM PDT 24
Peak memory 201904 kb
Host smart-b0e5e12f-25c2-4329-a903-f785a1903aa8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739145365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.2739145365
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.293606364
Short name T89
Test name
Test status
Simulation time 73973474287 ps
CPU time 378.48 seconds
Started Jun 26 06:30:44 PM PDT 24
Finished Jun 26 06:37:04 PM PDT 24
Peak memory 202224 kb
Host smart-6155d7e9-7907-4856-a23c-e7f46704d236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293606364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.293606364
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.217855685
Short name T584
Test name
Test status
Simulation time 23710492895 ps
CPU time 48.97 seconds
Started Jun 26 06:30:38 PM PDT 24
Finished Jun 26 06:31:30 PM PDT 24
Peak memory 201680 kb
Host smart-a7a196ea-3780-413d-a58f-43f58edd90e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217855685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.217855685
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.515956631
Short name T671
Test name
Test status
Simulation time 3551140853 ps
CPU time 7.99 seconds
Started Jun 26 06:30:35 PM PDT 24
Finished Jun 26 06:30:46 PM PDT 24
Peak memory 201680 kb
Host smart-d52e8ae4-8f9b-413b-b4f5-adc6ce72c67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515956631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.515956631
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3905280722
Short name T374
Test name
Test status
Simulation time 5814230942 ps
CPU time 3.08 seconds
Started Jun 26 06:30:35 PM PDT 24
Finished Jun 26 06:30:42 PM PDT 24
Peak memory 201680 kb
Host smart-4b7e4af5-54b0-42f3-abbc-c21dfe10c1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905280722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3905280722
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.1164047264
Short name T784
Test name
Test status
Simulation time 171734580265 ps
CPU time 771.88 seconds
Started Jun 26 06:30:37 PM PDT 24
Finished Jun 26 06:43:33 PM PDT 24
Peak memory 210372 kb
Host smart-3fab6554-a10c-4963-8145-50c7dd850029
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164047264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.1164047264
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.886220005
Short name T608
Test name
Test status
Simulation time 550749063 ps
CPU time 0.73 seconds
Started Jun 26 06:30:51 PM PDT 24
Finished Jun 26 06:30:53 PM PDT 24
Peak memory 201608 kb
Host smart-f5a0b07c-f377-4827-b619-6c4390fd29da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886220005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.886220005
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3125415516
Short name T749
Test name
Test status
Simulation time 326449147194 ps
CPU time 385.21 seconds
Started Jun 26 06:30:38 PM PDT 24
Finished Jun 26 06:37:07 PM PDT 24
Peak memory 201836 kb
Host smart-f4269988-e08a-47bf-9f8b-d206d63820e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125415516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3125415516
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.4246385478
Short name T613
Test name
Test status
Simulation time 163085106372 ps
CPU time 375.39 seconds
Started Jun 26 06:30:35 PM PDT 24
Finished Jun 26 06:36:54 PM PDT 24
Peak memory 201756 kb
Host smart-ec9c51af-b61e-488d-a946-bfa29d8a2b4f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246385478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.4246385478
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.498153701
Short name T90
Test name
Test status
Simulation time 322796002755 ps
CPU time 352.66 seconds
Started Jun 26 06:30:44 PM PDT 24
Finished Jun 26 06:36:38 PM PDT 24
Peak memory 201824 kb
Host smart-9bced3b3-55c2-432f-94c2-56f985f3c443
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=498153701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixe
d.498153701
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.3414027611
Short name T618
Test name
Test status
Simulation time 530564159044 ps
CPU time 253.25 seconds
Started Jun 26 06:30:37 PM PDT 24
Finished Jun 26 06:34:54 PM PDT 24
Peak memory 201872 kb
Host smart-32433061-8428-4617-843f-30a3151212b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414027611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.3414027611
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.2369040933
Short name T465
Test name
Test status
Simulation time 196202539518 ps
CPU time 433.94 seconds
Started Jun 26 06:30:37 PM PDT 24
Finished Jun 26 06:37:55 PM PDT 24
Peak memory 201852 kb
Host smart-f2aff50e-554c-4ca6-8866-fce806ad2d3d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369040933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.2369040933
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.564692694
Short name T469
Test name
Test status
Simulation time 31294760439 ps
CPU time 70.88 seconds
Started Jun 26 06:30:37 PM PDT 24
Finished Jun 26 06:31:52 PM PDT 24
Peak memory 201672 kb
Host smart-c73bcdbf-31e3-4450-a4c1-c83a76866282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564692694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.564692694
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.2468304699
Short name T429
Test name
Test status
Simulation time 4244921127 ps
CPU time 2.44 seconds
Started Jun 26 06:30:37 PM PDT 24
Finished Jun 26 06:30:43 PM PDT 24
Peak memory 201656 kb
Host smart-dc17f930-c581-4c40-903e-e77eb777e7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468304699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.2468304699
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.2562270032
Short name T448
Test name
Test status
Simulation time 6101315623 ps
CPU time 3.8 seconds
Started Jun 26 06:30:37 PM PDT 24
Finished Jun 26 06:30:45 PM PDT 24
Peak memory 201660 kb
Host smart-8c182fc2-acdb-40cf-84c3-0bfa74b97709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562270032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.2562270032
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.2636234373
Short name T174
Test name
Test status
Simulation time 178794764985 ps
CPU time 388.72 seconds
Started Jun 26 06:30:39 PM PDT 24
Finished Jun 26 06:37:10 PM PDT 24
Peak memory 201876 kb
Host smart-8c9ed340-272e-4e33-b4ae-30c7dae2cd37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636234373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.2636234373
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2207201641
Short name T763
Test name
Test status
Simulation time 223906386554 ps
CPU time 163.74 seconds
Started Jun 26 06:30:48 PM PDT 24
Finished Jun 26 06:33:33 PM PDT 24
Peak memory 218360 kb
Host smart-008fac6a-7cbe-4e6c-bbc9-b810230f6bf9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207201641 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.2207201641
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.1779524826
Short name T726
Test name
Test status
Simulation time 386561888 ps
CPU time 1.47 seconds
Started Jun 26 06:30:48 PM PDT 24
Finished Jun 26 06:30:51 PM PDT 24
Peak memory 201640 kb
Host smart-9113a7cf-2f99-4184-8ba1-c741717ddf7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779524826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1779524826
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1261239977
Short name T723
Test name
Test status
Simulation time 503957377757 ps
CPU time 301.91 seconds
Started Jun 26 06:30:48 PM PDT 24
Finished Jun 26 06:35:51 PM PDT 24
Peak memory 201792 kb
Host smart-61eb4e9f-e127-4357-967c-1f67f78c3d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261239977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1261239977
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.40644397
Short name T788
Test name
Test status
Simulation time 164925768789 ps
CPU time 320.73 seconds
Started Jun 26 06:30:50 PM PDT 24
Finished Jun 26 06:36:12 PM PDT 24
Peak memory 201944 kb
Host smart-2cc2446d-1f06-4305-a16b-d594e10a5a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40644397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.40644397
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.577295135
Short name T556
Test name
Test status
Simulation time 167749789641 ps
CPU time 357.74 seconds
Started Jun 26 06:30:49 PM PDT 24
Finished Jun 26 06:36:48 PM PDT 24
Peak memory 201840 kb
Host smart-891d9b99-752c-44df-85d3-1949523168a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=577295135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.577295135
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.1688286283
Short name T701
Test name
Test status
Simulation time 164175977053 ps
CPU time 143.72 seconds
Started Jun 26 06:30:37 PM PDT 24
Finished Jun 26 06:33:04 PM PDT 24
Peak memory 201960 kb
Host smart-f624a87b-b731-4810-80b2-968fccbba15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688286283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.1688286283
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.3985147256
Short name T195
Test name
Test status
Simulation time 487573792806 ps
CPU time 279.82 seconds
Started Jun 26 06:30:49 PM PDT 24
Finished Jun 26 06:35:30 PM PDT 24
Peak memory 201832 kb
Host smart-38df1048-eb59-4cb1-8732-5e9840670930
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985147256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.3985147256
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.2834352766
Short name T508
Test name
Test status
Simulation time 181396519988 ps
CPU time 430.84 seconds
Started Jun 26 06:30:54 PM PDT 24
Finished Jun 26 06:38:05 PM PDT 24
Peak memory 201880 kb
Host smart-20cf3269-5527-4c56-abe0-ff7902790396
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834352766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.2834352766
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.2753293498
Short name T564
Test name
Test status
Simulation time 206492794685 ps
CPU time 465.57 seconds
Started Jun 26 06:30:48 PM PDT 24
Finished Jun 26 06:38:35 PM PDT 24
Peak memory 202100 kb
Host smart-a7dae0a0-3eef-45a8-9bf7-4a59c8fa7258
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753293498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.2753293498
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.4038736466
Short name T385
Test name
Test status
Simulation time 73589811018 ps
CPU time 295.14 seconds
Started Jun 26 06:30:43 PM PDT 24
Finished Jun 26 06:35:39 PM PDT 24
Peak memory 202204 kb
Host smart-1209fa13-03d7-4601-9620-6ff3e87ffefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038736466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.4038736466
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.3107559027
Short name T662
Test name
Test status
Simulation time 26319941100 ps
CPU time 28.98 seconds
Started Jun 26 06:30:39 PM PDT 24
Finished Jun 26 06:31:11 PM PDT 24
Peak memory 201628 kb
Host smart-dc37c604-fc21-4622-a3b4-a162088a9b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107559027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.3107559027
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.3681886311
Short name T781
Test name
Test status
Simulation time 4024316463 ps
CPU time 9.3 seconds
Started Jun 26 06:30:50 PM PDT 24
Finished Jun 26 06:31:00 PM PDT 24
Peak memory 201588 kb
Host smart-1e87f869-35eb-477a-a5c8-74a1d2371ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681886311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.3681886311
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2879951754
Short name T480
Test name
Test status
Simulation time 5930858817 ps
CPU time 15.42 seconds
Started Jun 26 06:30:36 PM PDT 24
Finished Jun 26 06:30:54 PM PDT 24
Peak memory 201684 kb
Host smart-8032adc6-ccee-461b-8549-067c0fc693ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879951754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2879951754
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.2350135494
Short name T700
Test name
Test status
Simulation time 301164948785 ps
CPU time 1101.98 seconds
Started Jun 26 06:30:54 PM PDT 24
Finished Jun 26 06:49:17 PM PDT 24
Peak memory 211964 kb
Host smart-fd581cc9-9ed6-4777-9ac4-d68a9efc0a3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350135494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.2350135494
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.4120332296
Short name T714
Test name
Test status
Simulation time 100038981999 ps
CPU time 189.81 seconds
Started Jun 26 06:30:46 PM PDT 24
Finished Jun 26 06:33:56 PM PDT 24
Peak memory 210264 kb
Host smart-d94c4955-e572-46c5-b9f7-6caa17e7b6d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120332296 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.4120332296
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.448052856
Short name T750
Test name
Test status
Simulation time 324263453 ps
CPU time 1.3 seconds
Started Jun 26 06:30:52 PM PDT 24
Finished Jun 26 06:30:54 PM PDT 24
Peak memory 201604 kb
Host smart-da7e7e06-da85-4acc-8ec0-7672208bd132
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448052856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.448052856
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3215748865
Short name T322
Test name
Test status
Simulation time 587568544649 ps
CPU time 358.01 seconds
Started Jun 26 06:30:50 PM PDT 24
Finished Jun 26 06:36:49 PM PDT 24
Peak memory 201848 kb
Host smart-9199092f-9477-4315-87b4-f3e41a2f15b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215748865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3215748865
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3152577050
Short name T650
Test name
Test status
Simulation time 165515976346 ps
CPU time 368.68 seconds
Started Jun 26 06:30:43 PM PDT 24
Finished Jun 26 06:36:53 PM PDT 24
Peak memory 201956 kb
Host smart-c8e085f3-f98a-42ec-bd04-e310e31db5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152577050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3152577050
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.423699563
Short name T499
Test name
Test status
Simulation time 330623843542 ps
CPU time 405.09 seconds
Started Jun 26 06:30:50 PM PDT 24
Finished Jun 26 06:37:36 PM PDT 24
Peak memory 201940 kb
Host smart-8aa6b6f6-2013-40d5-a646-306804bbb98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423699563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.423699563
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.2402365317
Short name T87
Test name
Test status
Simulation time 490823050634 ps
CPU time 289.57 seconds
Started Jun 26 06:30:47 PM PDT 24
Finished Jun 26 06:35:38 PM PDT 24
Peak memory 201856 kb
Host smart-0ee69cc4-723a-47e7-a53b-563dcadcf759
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402365317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.2402365317
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2292372470
Short name T107
Test name
Test status
Simulation time 328028931558 ps
CPU time 769.12 seconds
Started Jun 26 06:30:52 PM PDT 24
Finished Jun 26 06:43:42 PM PDT 24
Peak memory 201880 kb
Host smart-663b5f59-a786-4d4e-afa9-efec3051b0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292372470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2292372470
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.960815368
Short name T539
Test name
Test status
Simulation time 480437001024 ps
CPU time 265.38 seconds
Started Jun 26 06:30:46 PM PDT 24
Finished Jun 26 06:35:12 PM PDT 24
Peak memory 201932 kb
Host smart-18922225-5954-4c41-9182-4bc3824d0e22
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=960815368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixe
d.960815368
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.13687635
Short name T475
Test name
Test status
Simulation time 177153487840 ps
CPU time 102.78 seconds
Started Jun 26 06:30:41 PM PDT 24
Finished Jun 26 06:32:26 PM PDT 24
Peak memory 201876 kb
Host smart-0a65cfb6-bcfb-4c93-82f0-163b38d578fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13687635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_w
akeup.13687635
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.269444197
Short name T641
Test name
Test status
Simulation time 416208607712 ps
CPU time 971.68 seconds
Started Jun 26 06:30:51 PM PDT 24
Finished Jun 26 06:47:03 PM PDT 24
Peak memory 201892 kb
Host smart-2c7272f9-ee8c-4b74-a989-827170b8382b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269444197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.269444197
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.2623050703
Short name T362
Test name
Test status
Simulation time 31632349038 ps
CPU time 66.98 seconds
Started Jun 26 06:30:55 PM PDT 24
Finished Jun 26 06:32:03 PM PDT 24
Peak memory 201676 kb
Host smart-190ae288-e416-4859-b55c-a77e56768976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623050703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2623050703
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1554429245
Short name T481
Test name
Test status
Simulation time 3522873716 ps
CPU time 1.22 seconds
Started Jun 26 06:30:50 PM PDT 24
Finished Jun 26 06:30:52 PM PDT 24
Peak memory 201680 kb
Host smart-94980b63-a539-418c-830f-248052f28f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554429245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1554429245
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3729827588
Short name T505
Test name
Test status
Simulation time 6070703556 ps
CPU time 3.78 seconds
Started Jun 26 06:30:49 PM PDT 24
Finished Jun 26 06:30:54 PM PDT 24
Peak memory 201688 kb
Host smart-a0ad5a11-e62a-4471-b79a-44afcec94374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729827588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3729827588
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.301545105
Short name T297
Test name
Test status
Simulation time 331872658720 ps
CPU time 180.53 seconds
Started Jun 26 06:31:08 PM PDT 24
Finished Jun 26 06:34:09 PM PDT 24
Peak memory 201812 kb
Host smart-0ceb9c94-5187-4d6d-8d92-d32d3b0f94c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301545105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.
301545105
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2804096185
Short name T41
Test name
Test status
Simulation time 251667637487 ps
CPU time 406.75 seconds
Started Jun 26 06:30:49 PM PDT 24
Finished Jun 26 06:37:36 PM PDT 24
Peak memory 217932 kb
Host smart-76f13b4b-ab74-476f-90b6-dc996800a754
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804096185 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.2804096185
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1622636252
Short name T361
Test name
Test status
Simulation time 422384488 ps
CPU time 1.63 seconds
Started Jun 26 06:31:12 PM PDT 24
Finished Jun 26 06:31:15 PM PDT 24
Peak memory 201516 kb
Host smart-9cd38cba-3eb9-4239-a05a-9ca811e5cd6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622636252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1622636252
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.868574513
Short name T28
Test name
Test status
Simulation time 495194120831 ps
CPU time 314.24 seconds
Started Jun 26 06:31:09 PM PDT 24
Finished Jun 26 06:36:24 PM PDT 24
Peak memory 201824 kb
Host smart-06a595fc-0ca9-4062-85bb-4727351111ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868574513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gati
ng.868574513
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.4128008047
Short name T159
Test name
Test status
Simulation time 502644180832 ps
CPU time 546.81 seconds
Started Jun 26 06:30:52 PM PDT 24
Finished Jun 26 06:40:00 PM PDT 24
Peak memory 201860 kb
Host smart-5ab22f62-dfa2-462b-955d-f16ef7c15e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128008047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.4128008047
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.193028214
Short name T153
Test name
Test status
Simulation time 493618473387 ps
CPU time 77.13 seconds
Started Jun 26 06:30:51 PM PDT 24
Finished Jun 26 06:32:09 PM PDT 24
Peak memory 201852 kb
Host smart-15657242-549d-4c75-9420-4ebafa01ccdd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=193028214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrup
t_fixed.193028214
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3626603746
Short name T570
Test name
Test status
Simulation time 333686144831 ps
CPU time 190.47 seconds
Started Jun 26 06:30:57 PM PDT 24
Finished Jun 26 06:34:08 PM PDT 24
Peak memory 201864 kb
Host smart-477653ee-60f9-4bb6-8f4a-b0e220f37cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626603746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3626603746
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.1015553873
Short name T31
Test name
Test status
Simulation time 498569188220 ps
CPU time 282.04 seconds
Started Jun 26 06:30:55 PM PDT 24
Finished Jun 26 06:35:38 PM PDT 24
Peak memory 201852 kb
Host smart-62193a7c-a161-461c-93f5-75338952a1e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015553873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.1015553873
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2218611713
Short name T519
Test name
Test status
Simulation time 183631813700 ps
CPU time 200.28 seconds
Started Jun 26 06:30:52 PM PDT 24
Finished Jun 26 06:34:14 PM PDT 24
Peak memory 202084 kb
Host smart-4c1818eb-cdc8-4aa1-b60e-da1308957896
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218611713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2218611713
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.1930523973
Short name T530
Test name
Test status
Simulation time 595724773924 ps
CPU time 293.98 seconds
Started Jun 26 06:30:53 PM PDT 24
Finished Jun 26 06:35:48 PM PDT 24
Peak memory 202064 kb
Host smart-e413a9f1-80be-4da5-86c6-91a629edaad1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930523973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.1930523973
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.1381039075
Short name T509
Test name
Test status
Simulation time 100507550397 ps
CPU time 520.84 seconds
Started Jun 26 06:30:57 PM PDT 24
Finished Jun 26 06:39:38 PM PDT 24
Peak memory 202224 kb
Host smart-f7be22ad-acce-47aa-be1a-f7985041467e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381039075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1381039075
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.3991147826
Short name T596
Test name
Test status
Simulation time 25528942800 ps
CPU time 57.7 seconds
Started Jun 26 06:30:59 PM PDT 24
Finished Jun 26 06:31:58 PM PDT 24
Peak memory 201680 kb
Host smart-4c67ce3c-080b-4125-bd92-c2b7ac0a542b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991147826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3991147826
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.651578623
Short name T605
Test name
Test status
Simulation time 3210411004 ps
CPU time 4.04 seconds
Started Jun 26 06:30:53 PM PDT 24
Finished Jun 26 06:30:58 PM PDT 24
Peak memory 201684 kb
Host smart-b5aa4552-f90e-467a-b6c6-d7ded3a34314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651578623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.651578623
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.3901035139
Short name T682
Test name
Test status
Simulation time 5752416116 ps
CPU time 3.08 seconds
Started Jun 26 06:31:08 PM PDT 24
Finished Jun 26 06:31:12 PM PDT 24
Peak memory 201556 kb
Host smart-92c51c81-5916-4ff8-810e-28e359dd97e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901035139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3901035139
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.2172138131
Short name T629
Test name
Test status
Simulation time 1983373006746 ps
CPU time 1627.55 seconds
Started Jun 26 06:30:52 PM PDT 24
Finished Jun 26 06:58:01 PM PDT 24
Peak memory 210388 kb
Host smart-f0ff3470-c8ba-4a75-bce0-877bff76676a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172138131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.2172138131
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.436415430
Short name T93
Test name
Test status
Simulation time 208372208566 ps
CPU time 493.09 seconds
Started Jun 26 06:31:01 PM PDT 24
Finished Jun 26 06:39:14 PM PDT 24
Peak memory 210528 kb
Host smart-7df37811-2c7b-4bf8-af6e-6a269946de79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436415430 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.436415430
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.351921456
Short name T426
Test name
Test status
Simulation time 417373329 ps
CPU time 0.89 seconds
Started Jun 26 06:31:10 PM PDT 24
Finished Jun 26 06:31:12 PM PDT 24
Peak memory 201612 kb
Host smart-136902a5-aa7f-46a6-862d-ce3434361f9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351921456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.351921456
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.869866258
Short name T245
Test name
Test status
Simulation time 168498744374 ps
CPU time 370.75 seconds
Started Jun 26 06:31:15 PM PDT 24
Finished Jun 26 06:37:27 PM PDT 24
Peak memory 201892 kb
Host smart-d3f724f5-6c14-4e59-aaca-a17a161bf37b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869866258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gati
ng.869866258
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.349303330
Short name T184
Test name
Test status
Simulation time 328169560348 ps
CPU time 129.8 seconds
Started Jun 26 06:31:10 PM PDT 24
Finished Jun 26 06:33:21 PM PDT 24
Peak memory 201916 kb
Host smart-0ccc162f-7a37-4a92-a108-e0952cb1ba81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349303330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.349303330
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.618934513
Short name T507
Test name
Test status
Simulation time 322147080727 ps
CPU time 145.38 seconds
Started Jun 26 06:31:04 PM PDT 24
Finished Jun 26 06:33:31 PM PDT 24
Peak memory 201852 kb
Host smart-ca0a26fa-57d3-4801-a499-4a827dddbd8a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=618934513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrup
t_fixed.618934513
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1520913017
Short name T124
Test name
Test status
Simulation time 167619459900 ps
CPU time 95.33 seconds
Started Jun 26 06:31:05 PM PDT 24
Finished Jun 26 06:32:42 PM PDT 24
Peak memory 201980 kb
Host smart-0446231b-5e05-4fac-9094-a8969c60ccf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520913017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1520913017
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.894824969
Short name T661
Test name
Test status
Simulation time 489592843406 ps
CPU time 244.24 seconds
Started Jun 26 06:31:09 PM PDT 24
Finished Jun 26 06:35:15 PM PDT 24
Peak memory 201852 kb
Host smart-f51125d7-2f2c-4f17-a064-67bb233c72df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=894824969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixe
d.894824969
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.4057298703
Short name T571
Test name
Test status
Simulation time 175543286167 ps
CPU time 104.37 seconds
Started Jun 26 06:31:02 PM PDT 24
Finished Jun 26 06:32:47 PM PDT 24
Peak memory 201960 kb
Host smart-08cbf243-c879-45c6-a138-35714ea837dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057298703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.4057298703
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3088149751
Short name T345
Test name
Test status
Simulation time 121283375980 ps
CPU time 401.59 seconds
Started Jun 26 06:31:05 PM PDT 24
Finished Jun 26 06:37:47 PM PDT 24
Peak memory 202160 kb
Host smart-1b489ba9-0641-4a0b-83d4-d7e1ec78bd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088149751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3088149751
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.780342650
Short name T375
Test name
Test status
Simulation time 30628965703 ps
CPU time 7.43 seconds
Started Jun 26 06:31:04 PM PDT 24
Finished Jun 26 06:31:12 PM PDT 24
Peak memory 201696 kb
Host smart-da18aa1e-c21d-4251-aa8c-aa640e385536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780342650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.780342650
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3550272010
Short name T525
Test name
Test status
Simulation time 5218109288 ps
CPU time 6.25 seconds
Started Jun 26 06:31:16 PM PDT 24
Finished Jun 26 06:31:23 PM PDT 24
Peak memory 201704 kb
Host smart-7b5bb230-58a7-4bdf-8333-29994e14424b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550272010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3550272010
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.2269838323
Short name T688
Test name
Test status
Simulation time 5864819612 ps
CPU time 2.68 seconds
Started Jun 26 06:31:06 PM PDT 24
Finished Jun 26 06:31:09 PM PDT 24
Peak memory 201680 kb
Host smart-81cf4305-c462-473c-97e6-73c7c1a366f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269838323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2269838323
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.989205639
Short name T14
Test name
Test status
Simulation time 105768888874 ps
CPU time 57.53 seconds
Started Jun 26 06:31:03 PM PDT 24
Finished Jun 26 06:32:01 PM PDT 24
Peak memory 202060 kb
Host smart-41d4f041-14d3-4584-88e5-2eb2dd068776
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989205639 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.989205639
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.366643248
Short name T384
Test name
Test status
Simulation time 499137961 ps
CPU time 0.78 seconds
Started Jun 26 06:31:14 PM PDT 24
Finished Jun 26 06:31:16 PM PDT 24
Peak memory 201648 kb
Host smart-90513602-1aae-4682-a6ef-9ff4c0b95993
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366643248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.366643248
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3184918171
Short name T238
Test name
Test status
Simulation time 339768513978 ps
CPU time 542.71 seconds
Started Jun 26 06:31:02 PM PDT 24
Finished Jun 26 06:40:05 PM PDT 24
Peak memory 201860 kb
Host smart-83bff784-a845-442e-b13e-d95d6772d726
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184918171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3184918171
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.474202166
Short name T116
Test name
Test status
Simulation time 168619699525 ps
CPU time 87.01 seconds
Started Jun 26 06:31:03 PM PDT 24
Finished Jun 26 06:32:31 PM PDT 24
Peak memory 201912 kb
Host smart-8f1ee62a-753c-4911-b3a4-8170a4f7aa9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474202166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.474202166
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1838454733
Short name T612
Test name
Test status
Simulation time 162822652603 ps
CPU time 365.42 seconds
Started Jun 26 06:31:16 PM PDT 24
Finished Jun 26 06:37:22 PM PDT 24
Peak memory 201872 kb
Host smart-942f12db-07c4-4525-9d4d-2992f7758c72
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838454733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1838454733
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1460221979
Short name T312
Test name
Test status
Simulation time 328047104985 ps
CPU time 722.73 seconds
Started Jun 26 06:31:14 PM PDT 24
Finished Jun 26 06:43:18 PM PDT 24
Peak memory 201968 kb
Host smart-3466e5e0-98ec-4f0b-85ee-7d6a4859cbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460221979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1460221979
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3960551285
Short name T649
Test name
Test status
Simulation time 164097894147 ps
CPU time 364.79 seconds
Started Jun 26 06:31:03 PM PDT 24
Finished Jun 26 06:37:09 PM PDT 24
Peak memory 201860 kb
Host smart-f9e67e87-91d3-4220-9298-4369cd017457
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960551285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3960551285
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2214634369
Short name T786
Test name
Test status
Simulation time 407243669680 ps
CPU time 939.57 seconds
Started Jun 26 06:31:15 PM PDT 24
Finished Jun 26 06:46:55 PM PDT 24
Peak memory 201968 kb
Host smart-3486f778-3232-468b-b9af-06a13e89c451
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214634369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2214634369
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.2396758418
Short name T372
Test name
Test status
Simulation time 206961769984 ps
CPU time 244.19 seconds
Started Jun 26 06:31:05 PM PDT 24
Finished Jun 26 06:35:10 PM PDT 24
Peak memory 201872 kb
Host smart-dc329680-051e-461c-9d73-80ceb49b5ce3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396758418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.2396758418
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.824838487
Short name T707
Test name
Test status
Simulation time 119203160819 ps
CPU time 587.54 seconds
Started Jun 26 06:31:01 PM PDT 24
Finished Jun 26 06:40:49 PM PDT 24
Peak memory 202268 kb
Host smart-044b10f6-20c0-40f9-9364-51660962afdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824838487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.824838487
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.2065215441
Short name T794
Test name
Test status
Simulation time 26478802233 ps
CPU time 32 seconds
Started Jun 26 06:31:10 PM PDT 24
Finished Jun 26 06:31:43 PM PDT 24
Peak memory 201564 kb
Host smart-424e4089-0744-44c1-b0ba-4bd7ead73f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065215441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.2065215441
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.2480814953
Short name T523
Test name
Test status
Simulation time 2921611952 ps
CPU time 1.71 seconds
Started Jun 26 06:31:03 PM PDT 24
Finished Jun 26 06:31:06 PM PDT 24
Peak memory 201656 kb
Host smart-c68c0fef-cebd-4309-b428-99361e091560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480814953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.2480814953
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.2658590841
Short name T504
Test name
Test status
Simulation time 5702165271 ps
CPU time 2.97 seconds
Started Jun 26 06:31:06 PM PDT 24
Finished Jun 26 06:31:10 PM PDT 24
Peak memory 201680 kb
Host smart-495b0da1-09b2-4515-a4cc-172cfd8b1fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658590841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2658590841
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.4234303125
Short name T251
Test name
Test status
Simulation time 337424377896 ps
CPU time 719.99 seconds
Started Jun 26 06:31:10 PM PDT 24
Finished Jun 26 06:43:11 PM PDT 24
Peak memory 201756 kb
Host smart-bd0f532c-1af8-43f9-8cb4-70529398fdd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234303125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.4234303125
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3698681712
Short name T17
Test name
Test status
Simulation time 81051497291 ps
CPU time 212.77 seconds
Started Jun 26 06:31:12 PM PDT 24
Finished Jun 26 06:34:46 PM PDT 24
Peak memory 211420 kb
Host smart-40d2a5ab-e016-466a-850c-05377a154ad6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698681712 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.3698681712
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.720541215
Short name T488
Test name
Test status
Simulation time 418132465 ps
CPU time 0.78 seconds
Started Jun 26 06:31:25 PM PDT 24
Finished Jun 26 06:31:26 PM PDT 24
Peak memory 201600 kb
Host smart-1b053a77-d430-4cc1-8f16-155d40474531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720541215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.720541215
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.509991483
Short name T262
Test name
Test status
Simulation time 365528069779 ps
CPU time 437.03 seconds
Started Jun 26 06:31:22 PM PDT 24
Finished Jun 26 06:38:41 PM PDT 24
Peak memory 201872 kb
Host smart-3b80a021-d729-4d65-91e0-904dfa430f48
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509991483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.509991483
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1477658978
Short name T267
Test name
Test status
Simulation time 331479955481 ps
CPU time 181.54 seconds
Started Jun 26 06:31:22 PM PDT 24
Finished Jun 26 06:34:25 PM PDT 24
Peak memory 201880 kb
Host smart-9e01abd8-ada7-46ae-9ad5-33173254e7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477658978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1477658978
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2086836521
Short name T582
Test name
Test status
Simulation time 500085710786 ps
CPU time 537.21 seconds
Started Jun 26 06:31:23 PM PDT 24
Finished Jun 26 06:40:21 PM PDT 24
Peak memory 201832 kb
Host smart-f02d9b6b-9462-47dc-8c02-1985408c8ebf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086836521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2086836521
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1924881694
Short name T180
Test name
Test status
Simulation time 168135713577 ps
CPU time 37.89 seconds
Started Jun 26 06:31:05 PM PDT 24
Finished Jun 26 06:31:44 PM PDT 24
Peak memory 201836 kb
Host smart-49aed9d8-88ce-42ab-b8d9-95f5f3f6d913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924881694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1924881694
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3720109123
Short name T633
Test name
Test status
Simulation time 501160682312 ps
CPU time 165.63 seconds
Started Jun 26 06:31:24 PM PDT 24
Finished Jun 26 06:34:11 PM PDT 24
Peak memory 201872 kb
Host smart-5ae9dddf-04d4-4a42-b5d2-4960c5ff83d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720109123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3720109123
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3634194352
Short name T652
Test name
Test status
Simulation time 219207412249 ps
CPU time 117.72 seconds
Started Jun 26 06:31:32 PM PDT 24
Finished Jun 26 06:33:30 PM PDT 24
Peak memory 201940 kb
Host smart-34f06c38-2dad-4fba-8a95-72d1de5bb853
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634194352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3634194352
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3547909376
Short name T744
Test name
Test status
Simulation time 199085789627 ps
CPU time 452.01 seconds
Started Jun 26 06:31:22 PM PDT 24
Finished Jun 26 06:38:56 PM PDT 24
Peak memory 201860 kb
Host smart-f9464de6-12fd-46cd-995f-d0c93ede7c95
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547909376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3547909376
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3685562274
Short name T588
Test name
Test status
Simulation time 110813981685 ps
CPU time 573.1 seconds
Started Jun 26 06:31:24 PM PDT 24
Finished Jun 26 06:40:58 PM PDT 24
Peak memory 202276 kb
Host smart-a4805267-fb01-412c-93bd-3c4733f40327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685562274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3685562274
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.4266642772
Short name T601
Test name
Test status
Simulation time 24471930813 ps
CPU time 56.15 seconds
Started Jun 26 06:31:22 PM PDT 24
Finished Jun 26 06:32:19 PM PDT 24
Peak memory 201664 kb
Host smart-196517e9-4eb0-4fc4-950e-0208ca0aa4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266642772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.4266642772
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3621563363
Short name T728
Test name
Test status
Simulation time 3571054481 ps
CPU time 9.06 seconds
Started Jun 26 06:31:22 PM PDT 24
Finished Jun 26 06:31:32 PM PDT 24
Peak memory 201680 kb
Host smart-ecf20408-1238-4b0b-b310-9def9718fc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621563363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3621563363
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.2917635715
Short name T392
Test name
Test status
Simulation time 5534096052 ps
CPU time 12.57 seconds
Started Jun 26 06:31:03 PM PDT 24
Finished Jun 26 06:31:16 PM PDT 24
Peak memory 201700 kb
Host smart-ec3e2dbe-bb40-4927-af5c-50371aaae94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917635715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.2917635715
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.3789075469
Short name T753
Test name
Test status
Simulation time 321552612930 ps
CPU time 408.45 seconds
Started Jun 26 06:31:29 PM PDT 24
Finished Jun 26 06:38:18 PM PDT 24
Peak memory 201756 kb
Host smart-365bbd01-a386-4d2c-8ac0-9029b9eb94d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789075469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.3789075469
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.1451099411
Short name T785
Test name
Test status
Simulation time 470108123 ps
CPU time 1.22 seconds
Started Jun 26 06:30:13 PM PDT 24
Finished Jun 26 06:30:16 PM PDT 24
Peak memory 201636 kb
Host smart-ee182fd7-cf58-43d5-9443-acec965b13d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451099411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1451099411
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1238735642
Short name T186
Test name
Test status
Simulation time 491771130711 ps
CPU time 207.39 seconds
Started Jun 26 06:30:04 PM PDT 24
Finished Jun 26 06:33:33 PM PDT 24
Peak memory 201960 kb
Host smart-e9ee7d55-b334-4b4f-8f67-e656e752ebd6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238735642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1238735642
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.959826008
Short name T630
Test name
Test status
Simulation time 328181312518 ps
CPU time 366.23 seconds
Started Jun 26 06:30:16 PM PDT 24
Finished Jun 26 06:36:25 PM PDT 24
Peak memory 201860 kb
Host smart-7d380220-73c0-47e4-aa88-6d29dd15f29e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=959826008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.959826008
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.167532719
Short name T123
Test name
Test status
Simulation time 169017122715 ps
CPU time 94.22 seconds
Started Jun 26 06:30:04 PM PDT 24
Finished Jun 26 06:31:41 PM PDT 24
Peak memory 201936 kb
Host smart-77f315d4-24cf-43bb-ad01-807c211addb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167532719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.167532719
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1182483874
Short name T617
Test name
Test status
Simulation time 161375626586 ps
CPU time 91.73 seconds
Started Jun 26 06:30:07 PM PDT 24
Finished Jun 26 06:31:41 PM PDT 24
Peak memory 201876 kb
Host smart-e8edec04-dd1c-4c51-9398-75bd5b552313
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182483874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1182483874
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.2675278511
Short name T560
Test name
Test status
Simulation time 182555428337 ps
CPU time 226.71 seconds
Started Jun 26 06:30:02 PM PDT 24
Finished Jun 26 06:33:51 PM PDT 24
Peak memory 201924 kb
Host smart-bf219826-7dcd-4d90-9979-b35b0b23ae73
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675278511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.2675278511
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.7959271
Short name T44
Test name
Test status
Simulation time 398140575816 ps
CPU time 883.48 seconds
Started Jun 26 06:30:03 PM PDT 24
Finished Jun 26 06:44:48 PM PDT 24
Peak memory 201872 kb
Host smart-e18cd193-eb4d-451b-af4c-444895e0880d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7959271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc
_ctrl_filters_wakeup_fixed.7959271
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.2629461462
Short name T544
Test name
Test status
Simulation time 141300138514 ps
CPU time 437.87 seconds
Started Jun 26 06:29:59 PM PDT 24
Finished Jun 26 06:37:18 PM PDT 24
Peak memory 202172 kb
Host smart-c217b26d-9f4b-4f18-bf74-ce76ee6f377b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629461462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.2629461462
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2070871830
Short name T190
Test name
Test status
Simulation time 34767341128 ps
CPU time 20.75 seconds
Started Jun 26 06:30:06 PM PDT 24
Finished Jun 26 06:30:29 PM PDT 24
Peak memory 201700 kb
Host smart-edcf1ddb-4022-43e5-bdab-744397a4d872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070871830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2070871830
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.2309094255
Short name T421
Test name
Test status
Simulation time 3605902133 ps
CPU time 2.81 seconds
Started Jun 26 06:30:08 PM PDT 24
Finished Jun 26 06:30:12 PM PDT 24
Peak memory 201904 kb
Host smart-6186b7d7-8736-4840-b7e1-d36b8a32885e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309094255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2309094255
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.2718392322
Short name T67
Test name
Test status
Simulation time 7997124703 ps
CPU time 17.94 seconds
Started Jun 26 06:30:02 PM PDT 24
Finished Jun 26 06:30:21 PM PDT 24
Peak memory 217172 kb
Host smart-15b215c7-7711-4981-b207-17e853d6ffca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718392322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.2718392322
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.2741956711
Short name T149
Test name
Test status
Simulation time 6134919609 ps
CPU time 15.69 seconds
Started Jun 26 06:29:57 PM PDT 24
Finished Jun 26 06:30:15 PM PDT 24
Peak memory 201644 kb
Host smart-641ae862-6a19-4269-a812-ad84754a96a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741956711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.2741956711
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.1144540714
Short name T286
Test name
Test status
Simulation time 468101993100 ps
CPU time 1103.81 seconds
Started Jun 26 06:30:14 PM PDT 24
Finished Jun 26 06:48:40 PM PDT 24
Peak memory 210388 kb
Host smart-d468e3b1-d909-495f-849b-1932cbc2f47e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144540714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
1144540714
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.43422622
Short name T23
Test name
Test status
Simulation time 48048005436 ps
CPU time 96.13 seconds
Started Jun 26 06:30:20 PM PDT 24
Finished Jun 26 06:32:01 PM PDT 24
Peak memory 210064 kb
Host smart-a0f75254-9353-4c9d-a1af-28d58f25afc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43422622 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.43422622
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3289510294
Short name T326
Test name
Test status
Simulation time 195595935500 ps
CPU time 418.95 seconds
Started Jun 26 06:31:22 PM PDT 24
Finished Jun 26 06:38:22 PM PDT 24
Peak memory 201944 kb
Host smart-80372779-98f3-4f71-8fca-99e1765c6896
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289510294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3289510294
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.916148377
Short name T451
Test name
Test status
Simulation time 167408008140 ps
CPU time 204.18 seconds
Started Jun 26 06:31:22 PM PDT 24
Finished Jun 26 06:34:47 PM PDT 24
Peak memory 201896 kb
Host smart-d06b0a67-58b5-4322-98cd-7d52df85d4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916148377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.916148377
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2781425353
Short name T402
Test name
Test status
Simulation time 495947891017 ps
CPU time 282.35 seconds
Started Jun 26 06:31:23 PM PDT 24
Finished Jun 26 06:36:06 PM PDT 24
Peak memory 201796 kb
Host smart-2ce47608-1856-468b-aae4-d549d7b175e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781425353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2781425353
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.1423822315
Short name T491
Test name
Test status
Simulation time 167097817111 ps
CPU time 357.57 seconds
Started Jun 26 06:31:21 PM PDT 24
Finished Jun 26 06:37:20 PM PDT 24
Peak memory 201896 kb
Host smart-29666247-3351-4d26-b100-22e80ee689e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423822315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.1423822315
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.200831115
Short name T473
Test name
Test status
Simulation time 322514398082 ps
CPU time 661.39 seconds
Started Jun 26 06:31:21 PM PDT 24
Finished Jun 26 06:42:24 PM PDT 24
Peak memory 202088 kb
Host smart-daa7ddf5-13f7-4f5c-aae0-bb70be560661
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=200831115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixe
d.200831115
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.796623043
Short name T606
Test name
Test status
Simulation time 196539696215 ps
CPU time 62.87 seconds
Started Jun 26 06:31:24 PM PDT 24
Finished Jun 26 06:32:28 PM PDT 24
Peak memory 201852 kb
Host smart-b00baa20-8226-4640-bb7c-aa01293781d4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796623043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
adc_ctrl_filters_wakeup_fixed.796623043
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2720974790
Short name T343
Test name
Test status
Simulation time 82899064851 ps
CPU time 297.35 seconds
Started Jun 26 06:31:23 PM PDT 24
Finished Jun 26 06:36:21 PM PDT 24
Peak memory 202192 kb
Host smart-a6335548-dbfa-423d-afea-9445c4e65528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720974790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2720974790
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2037122959
Short name T360
Test name
Test status
Simulation time 41809393869 ps
CPU time 44.24 seconds
Started Jun 26 06:31:25 PM PDT 24
Finished Jun 26 06:32:10 PM PDT 24
Peak memory 201684 kb
Host smart-6aa7d150-50a4-43e8-92cc-f640c1673923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037122959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2037122959
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.1390754457
Short name T419
Test name
Test status
Simulation time 3174392827 ps
CPU time 1.64 seconds
Started Jun 26 06:31:23 PM PDT 24
Finished Jun 26 06:31:26 PM PDT 24
Peak memory 201676 kb
Host smart-32d03853-0db4-4247-955a-7d310e089fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390754457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1390754457
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.4190663152
Short name T532
Test name
Test status
Simulation time 5872624894 ps
CPU time 4.16 seconds
Started Jun 26 06:31:22 PM PDT 24
Finished Jun 26 06:31:28 PM PDT 24
Peak memory 201680 kb
Host smart-a9c8c491-d9e9-4ece-bb3e-31b750913ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190663152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.4190663152
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.1800186475
Short name T549
Test name
Test status
Simulation time 163980662870 ps
CPU time 25.61 seconds
Started Jun 26 06:31:21 PM PDT 24
Finished Jun 26 06:31:48 PM PDT 24
Peak memory 201832 kb
Host smart-16ffafe1-f1a0-48f3-a676-0e9c381c5bcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800186475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.1800186475
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.3758665150
Short name T92
Test name
Test status
Simulation time 58099102461 ps
CPU time 45.6 seconds
Started Jun 26 06:31:24 PM PDT 24
Finished Jun 26 06:32:11 PM PDT 24
Peak memory 210256 kb
Host smart-06e07a4a-0aa5-46f7-b224-f87e12a2e2b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758665150 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.3758665150
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2368014702
Short name T396
Test name
Test status
Simulation time 299362897 ps
CPU time 0.77 seconds
Started Jun 26 06:33:24 PM PDT 24
Finished Jun 26 06:33:54 PM PDT 24
Peak memory 201624 kb
Host smart-27044fcc-a03f-4559-9015-0dd74ba21099
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368014702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2368014702
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.2903095806
Short name T299
Test name
Test status
Simulation time 173388565887 ps
CPU time 243.83 seconds
Started Jun 26 06:31:37 PM PDT 24
Finished Jun 26 06:35:42 PM PDT 24
Peak memory 201940 kb
Host smart-b4bc46ab-6691-482e-8062-88282724eff4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903095806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.2903095806
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.1510377260
Short name T730
Test name
Test status
Simulation time 332743084349 ps
CPU time 316.21 seconds
Started Jun 26 06:31:38 PM PDT 24
Finished Jun 26 06:36:55 PM PDT 24
Peak memory 201808 kb
Host smart-254558f9-6c3a-416d-9c47-e26c78bea4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510377260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.1510377260
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.359693321
Short name T577
Test name
Test status
Simulation time 325845203239 ps
CPU time 714.06 seconds
Started Jun 26 06:31:39 PM PDT 24
Finished Jun 26 06:43:35 PM PDT 24
Peak memory 201840 kb
Host smart-9564ad64-9b46-4312-9d20-a89140280084
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=359693321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrup
t_fixed.359693321
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.4067494803
Short name T587
Test name
Test status
Simulation time 324527452520 ps
CPU time 721.3 seconds
Started Jun 26 06:31:38 PM PDT 24
Finished Jun 26 06:43:41 PM PDT 24
Peak memory 201916 kb
Host smart-51b861be-b9fc-477c-abec-3354297473e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067494803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.4067494803
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.1127902263
Short name T496
Test name
Test status
Simulation time 488766470260 ps
CPU time 296.16 seconds
Started Jun 26 06:31:40 PM PDT 24
Finished Jun 26 06:36:38 PM PDT 24
Peak memory 201848 kb
Host smart-07ea770a-2aa3-4dc7-ad0d-a881c2591cbe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127902263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.1127902263
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.1160193036
Short name T260
Test name
Test status
Simulation time 587975357913 ps
CPU time 1147.62 seconds
Started Jun 26 06:31:38 PM PDT 24
Finished Jun 26 06:50:47 PM PDT 24
Peak memory 201888 kb
Host smart-a70e989f-3ea3-42b5-8ea1-cac8ed0e5ac1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160193036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.1160193036
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.2051112202
Short name T724
Test name
Test status
Simulation time 409177443528 ps
CPU time 478.38 seconds
Started Jun 26 06:31:39 PM PDT 24
Finished Jun 26 06:39:39 PM PDT 24
Peak memory 201852 kb
Host smart-2b8a9398-b77c-4940-85ef-eddfe20d18df
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051112202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.2051112202
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.3955657392
Short name T579
Test name
Test status
Simulation time 89052222956 ps
CPU time 303.63 seconds
Started Jun 26 06:32:00 PM PDT 24
Finished Jun 26 06:37:04 PM PDT 24
Peak memory 202200 kb
Host smart-daa3f216-c5a8-45b1-b98e-a524104e1249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955657392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.3955657392
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2964549688
Short name T732
Test name
Test status
Simulation time 31280058636 ps
CPU time 53.3 seconds
Started Jun 26 06:31:39 PM PDT 24
Finished Jun 26 06:32:34 PM PDT 24
Peak memory 201672 kb
Host smart-6e88755c-d987-4504-ab0b-d7312867a96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964549688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2964549688
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.4060009204
Short name T597
Test name
Test status
Simulation time 4429393353 ps
CPU time 2.41 seconds
Started Jun 26 06:31:39 PM PDT 24
Finished Jun 26 06:31:43 PM PDT 24
Peak memory 201676 kb
Host smart-0c0b1632-59c1-4518-a627-ad9987f34541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060009204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.4060009204
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2923005004
Short name T147
Test name
Test status
Simulation time 5791974711 ps
CPU time 4.18 seconds
Started Jun 26 06:31:39 PM PDT 24
Finished Jun 26 06:31:44 PM PDT 24
Peak memory 201700 kb
Host smart-bcc7afca-c3a4-4b81-aa74-464a9ec4c733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923005004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2923005004
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2384963715
Short name T305
Test name
Test status
Simulation time 81592249268 ps
CPU time 44 seconds
Started Jun 26 06:31:40 PM PDT 24
Finished Jun 26 06:32:26 PM PDT 24
Peak memory 210236 kb
Host smart-52ef4126-187e-4e49-9d34-bb0709374826
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384963715 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2384963715
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.2092741243
Short name T75
Test name
Test status
Simulation time 283958542 ps
CPU time 1.28 seconds
Started Jun 26 06:31:39 PM PDT 24
Finished Jun 26 06:31:41 PM PDT 24
Peak memory 201640 kb
Host smart-807bf850-a9df-4806-971e-215983d7ea33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092741243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.2092741243
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.939493748
Short name T323
Test name
Test status
Simulation time 167584860449 ps
CPU time 98.16 seconds
Started Jun 26 06:31:40 PM PDT 24
Finished Jun 26 06:33:20 PM PDT 24
Peak memory 201852 kb
Host smart-959a129b-e8e9-4389-bfe8-4dfb3323a97b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939493748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.939493748
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2441434774
Short name T119
Test name
Test status
Simulation time 419571964440 ps
CPU time 137.93 seconds
Started Jun 26 06:31:38 PM PDT 24
Finished Jun 26 06:33:57 PM PDT 24
Peak memory 201908 kb
Host smart-a7596364-2e1b-48ba-bb28-ffd2b79e7074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441434774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2441434774
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.2618567828
Short name T315
Test name
Test status
Simulation time 493459699510 ps
CPU time 1032.55 seconds
Started Jun 26 06:31:37 PM PDT 24
Finished Jun 26 06:48:51 PM PDT 24
Peak memory 201892 kb
Host smart-385e0079-f077-488f-9f2c-9e86d1e85180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618567828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.2618567828
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.4209833780
Short name T357
Test name
Test status
Simulation time 323407916979 ps
CPU time 713.89 seconds
Started Jun 26 06:31:39 PM PDT 24
Finished Jun 26 06:43:35 PM PDT 24
Peak memory 201884 kb
Host smart-58829085-c98d-4bfe-b489-269f05cca2ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209833780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.4209833780
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.3183431761
Short name T349
Test name
Test status
Simulation time 482716351684 ps
CPU time 1103.17 seconds
Started Jun 26 06:31:39 PM PDT 24
Finished Jun 26 06:50:03 PM PDT 24
Peak memory 201808 kb
Host smart-e4edc3c0-f00b-48de-9903-eed78e8f9804
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183431761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.3183431761
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.4064116742
Short name T248
Test name
Test status
Simulation time 180841978915 ps
CPU time 103.01 seconds
Started Jun 26 06:31:40 PM PDT 24
Finished Jun 26 06:33:25 PM PDT 24
Peak memory 201924 kb
Host smart-ea313ccc-5b00-4ada-9c1d-edf1f2b777b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064116742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.4064116742
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.1458907572
Short name T348
Test name
Test status
Simulation time 200988290938 ps
CPU time 208.01 seconds
Started Jun 26 06:31:39 PM PDT 24
Finished Jun 26 06:35:09 PM PDT 24
Peak memory 201824 kb
Host smart-6464511f-092e-4b1c-b42d-c18100919494
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458907572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.1458907572
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.3298133082
Short name T84
Test name
Test status
Simulation time 96351843316 ps
CPU time 357.49 seconds
Started Jun 26 06:31:41 PM PDT 24
Finished Jun 26 06:37:40 PM PDT 24
Peak memory 202260 kb
Host smart-a3b5ab54-bfeb-4801-93d9-79dde51fd1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298133082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.3298133082
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.4016747923
Short name T738
Test name
Test status
Simulation time 30528431709 ps
CPU time 34.4 seconds
Started Jun 26 06:31:41 PM PDT 24
Finished Jun 26 06:32:17 PM PDT 24
Peak memory 201684 kb
Host smart-ff96f385-165c-4fec-960e-fb1e3d3062cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016747923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.4016747923
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.3528467527
Short name T715
Test name
Test status
Simulation time 3838426908 ps
CPU time 5.31 seconds
Started Jun 26 06:31:38 PM PDT 24
Finished Jun 26 06:31:44 PM PDT 24
Peak memory 201628 kb
Host smart-d9c7241d-e79e-4796-b74c-93f0ec9717ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528467527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.3528467527
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.228622174
Short name T656
Test name
Test status
Simulation time 5900522174 ps
CPU time 10.76 seconds
Started Jun 26 06:31:40 PM PDT 24
Finished Jun 26 06:31:52 PM PDT 24
Peak memory 201660 kb
Host smart-ddc7caa5-2e4e-441b-bdfd-336dd6b48d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228622174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.228622174
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2967630443
Short name T111
Test name
Test status
Simulation time 365272263347 ps
CPU time 909.82 seconds
Started Jun 26 06:31:39 PM PDT 24
Finished Jun 26 06:46:50 PM PDT 24
Peak memory 201888 kb
Host smart-f930d282-ee61-45cf-9293-a9362bf2ccd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967630443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2967630443
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.21285749
Short name T21
Test name
Test status
Simulation time 39452001854 ps
CPU time 52.45 seconds
Started Jun 26 06:31:40 PM PDT 24
Finished Jun 26 06:32:34 PM PDT 24
Peak memory 210508 kb
Host smart-f5bcb78b-5180-4e51-94f0-2934a7aa7948
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21285749 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.21285749
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.52930919
Short name T642
Test name
Test status
Simulation time 460970544 ps
CPU time 1.64 seconds
Started Jun 26 06:31:50 PM PDT 24
Finished Jun 26 06:31:52 PM PDT 24
Peak memory 201640 kb
Host smart-30eee62f-5f17-44e6-9a0d-85fa5f801b1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52930919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.52930919
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.427870540
Short name T615
Test name
Test status
Simulation time 166119751054 ps
CPU time 360.71 seconds
Started Jun 26 06:31:37 PM PDT 24
Finished Jun 26 06:37:39 PM PDT 24
Peak memory 201800 kb
Host smart-51d95414-e3b5-45f4-99e5-8cf3fba549d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427870540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.427870540
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.3554102522
Short name T675
Test name
Test status
Simulation time 331785049271 ps
CPU time 119.64 seconds
Started Jun 26 06:31:39 PM PDT 24
Finished Jun 26 06:33:41 PM PDT 24
Peak memory 201860 kb
Host smart-e55d873c-edad-4909-98b4-63cfe84493c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554102522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.3554102522
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.1507379333
Short name T790
Test name
Test status
Simulation time 331885964670 ps
CPU time 697.05 seconds
Started Jun 26 06:31:39 PM PDT 24
Finished Jun 26 06:43:18 PM PDT 24
Peak memory 201788 kb
Host smart-1e7145b7-a8e3-484d-9bbe-b36ee340875a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507379333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.1507379333
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.2326989171
Short name T332
Test name
Test status
Simulation time 163006837428 ps
CPU time 93.37 seconds
Started Jun 26 06:31:38 PM PDT 24
Finished Jun 26 06:33:12 PM PDT 24
Peak memory 201904 kb
Host smart-1e6ec8eb-da2e-4fbd-afc2-cb960344bd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326989171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.2326989171
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1899749508
Short name T620
Test name
Test status
Simulation time 165871731974 ps
CPU time 76.97 seconds
Started Jun 26 06:31:40 PM PDT 24
Finished Jun 26 06:32:59 PM PDT 24
Peak memory 201864 kb
Host smart-732e1b4c-2b49-49e4-9e33-a7be5390334b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899749508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.1899749508
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.1977909195
Short name T428
Test name
Test status
Simulation time 185603739636 ps
CPU time 223.73 seconds
Started Jun 26 06:31:37 PM PDT 24
Finished Jun 26 06:35:22 PM PDT 24
Peak memory 201908 kb
Host smart-87056416-8afe-4bd1-93ab-31560d6915a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977909195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.1977909195
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.744842814
Short name T432
Test name
Test status
Simulation time 398391703531 ps
CPU time 946.51 seconds
Started Jun 26 06:31:38 PM PDT 24
Finished Jun 26 06:47:25 PM PDT 24
Peak memory 201860 kb
Host smart-916fdb68-3fe6-46d7-a6bd-e9c21ea7d5d8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744842814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
adc_ctrl_filters_wakeup_fixed.744842814
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.3138748105
Short name T698
Test name
Test status
Simulation time 112166826265 ps
CPU time 573.98 seconds
Started Jun 26 06:31:50 PM PDT 24
Finished Jun 26 06:41:25 PM PDT 24
Peak memory 202184 kb
Host smart-35382a6b-9306-4e07-8d2f-c091a9d55efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138748105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3138748105
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.1625389720
Short name T760
Test name
Test status
Simulation time 25906031285 ps
CPU time 14.56 seconds
Started Jun 26 06:31:50 PM PDT 24
Finished Jun 26 06:32:05 PM PDT 24
Peak memory 201692 kb
Host smart-e76c242c-c856-43f1-a9f2-05530a929c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625389720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.1625389720
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.2665033412
Short name T434
Test name
Test status
Simulation time 3466371528 ps
CPU time 4.7 seconds
Started Jun 26 06:31:48 PM PDT 24
Finished Jun 26 06:31:54 PM PDT 24
Peak memory 201648 kb
Host smart-ca49bd17-7159-426f-931e-6502a049ad5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665033412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2665033412
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.1040094890
Short name T377
Test name
Test status
Simulation time 5632105491 ps
CPU time 4.18 seconds
Started Jun 26 06:31:40 PM PDT 24
Finished Jun 26 06:31:46 PM PDT 24
Peak memory 201676 kb
Host smart-a00ee1f8-2b18-4d9e-8592-a2cd16b74817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040094890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1040094890
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.2391057460
Short name T263
Test name
Test status
Simulation time 183568843586 ps
CPU time 109.17 seconds
Started Jun 26 06:31:51 PM PDT 24
Finished Jun 26 06:33:40 PM PDT 24
Peak memory 201936 kb
Host smart-57f1c86c-cdd3-40fa-94bf-7cb94250f974
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391057460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.2391057460
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3649883325
Short name T766
Test name
Test status
Simulation time 21543734722 ps
CPU time 19.58 seconds
Started Jun 26 06:31:49 PM PDT 24
Finished Jun 26 06:32:09 PM PDT 24
Peak memory 210452 kb
Host smart-aa742bbc-c7d6-4741-a3df-5bc39684b66b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649883325 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.3649883325
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.3569160371
Short name T393
Test name
Test status
Simulation time 306075538 ps
CPU time 1.35 seconds
Started Jun 26 06:36:28 PM PDT 24
Finished Jun 26 06:36:30 PM PDT 24
Peak memory 201632 kb
Host smart-5500d58c-5471-4955-9913-30a034045731
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569160371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3569160371
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.3536662262
Short name T614
Test name
Test status
Simulation time 598480372856 ps
CPU time 675.44 seconds
Started Jun 26 06:36:29 PM PDT 24
Finished Jun 26 06:47:48 PM PDT 24
Peak memory 201908 kb
Host smart-ebf09ec4-e57b-4f66-b85a-2ca2a85ebdc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536662262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3536662262
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.891392868
Short name T223
Test name
Test status
Simulation time 159187878621 ps
CPU time 182.43 seconds
Started Jun 26 06:31:51 PM PDT 24
Finished Jun 26 06:34:54 PM PDT 24
Peak memory 201892 kb
Host smart-fcb9cd5f-1127-4e86-a35c-481283ca898e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891392868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.891392868
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1384484183
Short name T512
Test name
Test status
Simulation time 156378171985 ps
CPU time 174.55 seconds
Started Jun 26 06:31:51 PM PDT 24
Finished Jun 26 06:34:46 PM PDT 24
Peak memory 201880 kb
Host smart-2587b026-072b-4823-950d-6e3db8857688
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384484183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1384484183
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1022038120
Short name T2
Test name
Test status
Simulation time 320615254817 ps
CPU time 714.54 seconds
Started Jun 26 06:31:50 PM PDT 24
Finished Jun 26 06:43:45 PM PDT 24
Peak memory 201932 kb
Host smart-787b9176-16aa-48ab-9905-94fe466d480e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022038120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1022038120
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.3940437419
Short name T30
Test name
Test status
Simulation time 327875842048 ps
CPU time 177.24 seconds
Started Jun 26 06:31:49 PM PDT 24
Finished Jun 26 06:34:47 PM PDT 24
Peak memory 201872 kb
Host smart-bfe7a9bf-da3d-48dd-b583-db9e62b3560a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940437419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.3940437419
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3324708778
Short name T1
Test name
Test status
Simulation time 347784068521 ps
CPU time 383.94 seconds
Started Jun 26 06:31:49 PM PDT 24
Finished Jun 26 06:38:14 PM PDT 24
Peak memory 201836 kb
Host smart-78487fdc-eb91-4b22-8677-a0f10bd2ad04
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324708778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3324708778
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.4235645235
Short name T94
Test name
Test status
Simulation time 594695713324 ps
CPU time 842.75 seconds
Started Jun 26 06:31:50 PM PDT 24
Finished Jun 26 06:45:53 PM PDT 24
Peak memory 201800 kb
Host smart-872bdd8b-b8fd-4b19-b201-5e9f5b14c294
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235645235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.4235645235
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.2707611761
Short name T47
Test name
Test status
Simulation time 73269721906 ps
CPU time 245.95 seconds
Started Jun 26 06:36:17 PM PDT 24
Finished Jun 26 06:40:24 PM PDT 24
Peak memory 202220 kb
Host smart-f90b5b3f-9a0d-4d7d-985f-68ab75f6facd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707611761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.2707611761
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.1684310684
Short name T727
Test name
Test status
Simulation time 44732690989 ps
CPU time 46.85 seconds
Started Jun 26 06:36:16 PM PDT 24
Finished Jun 26 06:37:04 PM PDT 24
Peak memory 201632 kb
Host smart-c30c9206-c211-4e10-8d26-ad8153a58f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684310684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.1684310684
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.3292227408
Short name T543
Test name
Test status
Simulation time 3143757604 ps
CPU time 7.81 seconds
Started Jun 26 06:36:21 PM PDT 24
Finished Jun 26 06:36:31 PM PDT 24
Peak memory 201704 kb
Host smart-c4992bcf-cf57-42b1-ae12-10b510c775b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292227408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3292227408
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.3958696996
Short name T10
Test name
Test status
Simulation time 5768704147 ps
CPU time 13.21 seconds
Started Jun 26 06:31:49 PM PDT 24
Finished Jun 26 06:32:03 PM PDT 24
Peak memory 201660 kb
Host smart-de826474-5223-48b2-8b3b-9da9ee2374e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958696996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3958696996
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.1205436700
Short name T169
Test name
Test status
Simulation time 339943651971 ps
CPU time 120.85 seconds
Started Jun 26 06:36:19 PM PDT 24
Finished Jun 26 06:38:22 PM PDT 24
Peak memory 201880 kb
Host smart-398404f8-f008-4cad-b022-33913687182c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205436700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.1205436700
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1324627841
Short name T456
Test name
Test status
Simulation time 577850355 ps
CPU time 0.77 seconds
Started Jun 26 06:36:29 PM PDT 24
Finished Jun 26 06:36:34 PM PDT 24
Peak memory 201648 kb
Host smart-c545da1c-f491-4690-beed-ecba4bf00e09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324627841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1324627841
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.767380207
Short name T168
Test name
Test status
Simulation time 589405248820 ps
CPU time 1266.14 seconds
Started Jun 26 06:36:30 PM PDT 24
Finished Jun 26 06:57:41 PM PDT 24
Peak memory 202088 kb
Host smart-ea7ec15a-4e4c-4217-bbbe-3baee4e30006
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767380207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gati
ng.767380207
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.3719676704
Short name T627
Test name
Test status
Simulation time 363898843270 ps
CPU time 859.56 seconds
Started Jun 26 06:36:19 PM PDT 24
Finished Jun 26 06:50:40 PM PDT 24
Peak memory 202172 kb
Host smart-9bc7e04b-7700-416d-8e4b-f47a2113f5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719676704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3719676704
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.3450980155
Short name T163
Test name
Test status
Simulation time 331314964701 ps
CPU time 91.11 seconds
Started Jun 26 06:36:19 PM PDT 24
Finished Jun 26 06:37:53 PM PDT 24
Peak memory 201880 kb
Host smart-cab54887-4c63-4597-bf45-6aeb9f98c3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450980155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3450980155
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.768277264
Short name T592
Test name
Test status
Simulation time 166854199977 ps
CPU time 120.09 seconds
Started Jun 26 06:36:21 PM PDT 24
Finished Jun 26 06:38:24 PM PDT 24
Peak memory 201872 kb
Host smart-c33781a1-4661-413a-892b-5c2585c4db65
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=768277264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrup
t_fixed.768277264
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.637986103
Short name T663
Test name
Test status
Simulation time 164256798572 ps
CPU time 80.04 seconds
Started Jun 26 06:36:18 PM PDT 24
Finished Jun 26 06:37:39 PM PDT 24
Peak memory 201968 kb
Host smart-ee333de1-5653-43fc-bac5-550e0fdd1041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637986103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.637986103
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.4241306224
Short name T514
Test name
Test status
Simulation time 166915943235 ps
CPU time 91 seconds
Started Jun 26 06:36:18 PM PDT 24
Finished Jun 26 06:37:51 PM PDT 24
Peak memory 201848 kb
Host smart-2469ad8f-154e-4d4b-9d98-f4d544d75172
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241306224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.4241306224
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.4171608664
Short name T331
Test name
Test status
Simulation time 172017684497 ps
CPU time 158.13 seconds
Started Jun 26 06:36:19 PM PDT 24
Finished Jun 26 06:38:59 PM PDT 24
Peak memory 201884 kb
Host smart-52094290-8804-4e47-a77a-679561665b8c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171608664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.4171608664
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.4087127991
Short name T621
Test name
Test status
Simulation time 402833287842 ps
CPU time 188.51 seconds
Started Jun 26 06:36:18 PM PDT 24
Finished Jun 26 06:39:29 PM PDT 24
Peak memory 201872 kb
Host smart-e2100e98-b5f8-4133-9013-e0ab59434266
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087127991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.4087127991
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1138281738
Short name T643
Test name
Test status
Simulation time 123763229480 ps
CPU time 417.28 seconds
Started Jun 26 06:36:18 PM PDT 24
Finished Jun 26 06:43:16 PM PDT 24
Peak memory 202204 kb
Host smart-c3c0f565-e12c-48e0-9f8a-492fd7d4fab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138281738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1138281738
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2033770268
Short name T85
Test name
Test status
Simulation time 44274168490 ps
CPU time 102.34 seconds
Started Jun 26 06:36:17 PM PDT 24
Finished Jun 26 06:38:01 PM PDT 24
Peak memory 201676 kb
Host smart-e3850b01-1c9b-43af-aced-1ddff1ec92a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033770268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2033770268
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3212346328
Short name T478
Test name
Test status
Simulation time 3737049127 ps
CPU time 8.92 seconds
Started Jun 26 06:36:43 PM PDT 24
Finished Jun 26 06:37:16 PM PDT 24
Peak memory 201684 kb
Host smart-9b1e3974-b3d5-4b4c-bab2-4d2c57d4055a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212346328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3212346328
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.3460079199
Short name T604
Test name
Test status
Simulation time 5838120065 ps
CPU time 4.19 seconds
Started Jun 26 06:36:19 PM PDT 24
Finished Jun 26 06:36:26 PM PDT 24
Peak memory 201648 kb
Host smart-9f8ab4c2-f5c1-41d7-af40-afb42cdc207a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460079199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3460079199
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.1426346766
Short name T279
Test name
Test status
Simulation time 363555024083 ps
CPU time 870.63 seconds
Started Jun 26 06:36:29 PM PDT 24
Finished Jun 26 06:51:04 PM PDT 24
Peak memory 201888 kb
Host smart-b7c45a5b-8aab-4c24-b37a-c719a2ecedf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426346766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.1426346766
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2614386905
Short name T573
Test name
Test status
Simulation time 44495790782 ps
CPU time 97.56 seconds
Started Jun 26 06:36:30 PM PDT 24
Finished Jun 26 06:38:11 PM PDT 24
Peak memory 210400 kb
Host smart-333c97dd-d0c7-4bfc-9e38-f31467081087
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614386905 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2614386905
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.503713621
Short name T369
Test name
Test status
Simulation time 479212695 ps
CPU time 0.89 seconds
Started Jun 26 06:36:19 PM PDT 24
Finished Jun 26 06:36:22 PM PDT 24
Peak memory 201628 kb
Host smart-8cf6c75f-e9ac-47d7-9f57-fb9cf8966bb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503713621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.503713621
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.3569549837
Short name T99
Test name
Test status
Simulation time 163645453063 ps
CPU time 10.67 seconds
Started Jun 26 06:36:19 PM PDT 24
Finished Jun 26 06:36:32 PM PDT 24
Peak memory 201940 kb
Host smart-b29a5bde-a57c-4fdb-b259-13de6e56a091
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569549837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.3569549837
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.1985559246
Short name T269
Test name
Test status
Simulation time 168766710244 ps
CPU time 192.92 seconds
Started Jun 26 06:36:19 PM PDT 24
Finished Jun 26 06:39:34 PM PDT 24
Peak memory 201960 kb
Host smart-4b602697-76a7-4bfe-b332-432ab9f7d6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985559246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.1985559246
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.4089195228
Short name T476
Test name
Test status
Simulation time 492486233770 ps
CPU time 351.48 seconds
Started Jun 26 06:36:19 PM PDT 24
Finished Jun 26 06:42:13 PM PDT 24
Peak memory 201876 kb
Host smart-13c0b39e-4863-4d6a-b07d-83236a614bc3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089195228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.4089195228
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.2682292922
Short name T320
Test name
Test status
Simulation time 164598336803 ps
CPU time 256.35 seconds
Started Jun 26 06:36:18 PM PDT 24
Finished Jun 26 06:40:36 PM PDT 24
Peak memory 201896 kb
Host smart-0a6dbf01-cfd7-4289-a70e-87e50907dd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682292922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.2682292922
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1502877516
Short name T399
Test name
Test status
Simulation time 490864519264 ps
CPU time 556.22 seconds
Started Jun 26 06:36:21 PM PDT 24
Finished Jun 26 06:45:40 PM PDT 24
Peak memory 201864 kb
Host smart-0ca2568d-e93e-4e0e-acce-e9db23101717
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502877516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1502877516
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.221403686
Short name T282
Test name
Test status
Simulation time 354403487439 ps
CPU time 781.2 seconds
Started Jun 26 06:36:19 PM PDT 24
Finished Jun 26 06:49:23 PM PDT 24
Peak memory 202128 kb
Host smart-ef5f6df0-b2a6-477a-b73c-5c3bbf9ddedd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221403686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_
wakeup.221403686
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1969891104
Short name T542
Test name
Test status
Simulation time 189637245780 ps
CPU time 135.2 seconds
Started Jun 26 06:36:19 PM PDT 24
Finished Jun 26 06:38:37 PM PDT 24
Peak memory 202072 kb
Host smart-e498209b-bba8-40db-8d85-7d6f34571217
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969891104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.1969891104
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.549294824
Short name T747
Test name
Test status
Simulation time 84703485702 ps
CPU time 272.72 seconds
Started Jun 26 06:36:18 PM PDT 24
Finished Jun 26 06:40:53 PM PDT 24
Peak memory 202208 kb
Host smart-3053b038-26cc-4d9f-8501-082f31923ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549294824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.549294824
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2467413276
Short name T779
Test name
Test status
Simulation time 22945752943 ps
CPU time 48.27 seconds
Started Jun 26 06:36:19 PM PDT 24
Finished Jun 26 06:37:10 PM PDT 24
Peak memory 201680 kb
Host smart-72f7882d-d80b-4f96-97a6-cf5c1731b72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467413276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2467413276
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.2106496472
Short name T719
Test name
Test status
Simulation time 3751223815 ps
CPU time 9.04 seconds
Started Jun 26 06:36:19 PM PDT 24
Finished Jun 26 06:36:30 PM PDT 24
Peak memory 201700 kb
Host smart-6c260c3d-5cd8-4385-82fe-974f2c2a2bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106496472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.2106496472
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.1587580358
Short name T520
Test name
Test status
Simulation time 5983055939 ps
CPU time 14.92 seconds
Started Jun 26 06:36:18 PM PDT 24
Finished Jun 26 06:36:35 PM PDT 24
Peak memory 201680 kb
Host smart-ee3b6822-6396-45bb-8579-ce0ac8b18b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587580358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1587580358
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3902816596
Short name T34
Test name
Test status
Simulation time 342098759718 ps
CPU time 581.32 seconds
Started Jun 26 06:36:17 PM PDT 24
Finished Jun 26 06:45:59 PM PDT 24
Peak memory 210568 kb
Host smart-5739ea64-87c6-4fd6-8a25-a89013f01224
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902816596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3902816596
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.3228208632
Short name T502
Test name
Test status
Simulation time 181157494899 ps
CPU time 191.74 seconds
Started Jun 26 06:36:36 PM PDT 24
Finished Jun 26 06:40:05 PM PDT 24
Peak memory 210268 kb
Host smart-fa85077b-94ef-49c7-86fa-2f3c2a6b39b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228208632 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.3228208632
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.865689620
Short name T752
Test name
Test status
Simulation time 376649210 ps
CPU time 1.08 seconds
Started Jun 26 06:36:32 PM PDT 24
Finished Jun 26 06:36:44 PM PDT 24
Peak memory 201612 kb
Host smart-973927bb-a9ca-472c-acde-78ca6f30d42a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865689620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.865689620
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.358657359
Short name T775
Test name
Test status
Simulation time 437573093167 ps
CPU time 260.46 seconds
Started Jun 26 06:36:18 PM PDT 24
Finished Jun 26 06:40:40 PM PDT 24
Peak memory 201888 kb
Host smart-1eb1d763-76fb-416e-b076-5f0d65411e1b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358657359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gati
ng.358657359
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.1771975251
Short name T693
Test name
Test status
Simulation time 508621839364 ps
CPU time 543.83 seconds
Started Jun 26 06:36:19 PM PDT 24
Finished Jun 26 06:45:24 PM PDT 24
Peak memory 201888 kb
Host smart-f11cc517-c870-4691-b84d-34cb22ddc0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771975251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1771975251
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.3798356574
Short name T264
Test name
Test status
Simulation time 170692595709 ps
CPU time 112.54 seconds
Started Jun 26 06:36:19 PM PDT 24
Finished Jun 26 06:38:14 PM PDT 24
Peak memory 201852 kb
Host smart-9e7f43b5-69ff-426b-b3a6-ce05e2eded40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798356574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.3798356574
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.3924466150
Short name T189
Test name
Test status
Simulation time 163923861988 ps
CPU time 199.85 seconds
Started Jun 26 06:36:21 PM PDT 24
Finished Jun 26 06:39:43 PM PDT 24
Peak memory 201852 kb
Host smart-492e8486-d6d7-4687-bb0e-73bc870256dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924466150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.3924466150
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2417676130
Short name T720
Test name
Test status
Simulation time 324681479528 ps
CPU time 111.51 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:38:42 PM PDT 24
Peak memory 201940 kb
Host smart-d1b71016-ba2a-49c0-a38c-23d736f8737c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417676130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2417676130
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.902080374
Short name T88
Test name
Test status
Simulation time 486203335453 ps
CPU time 237.66 seconds
Started Jun 26 06:36:17 PM PDT 24
Finished Jun 26 06:40:16 PM PDT 24
Peak memory 201864 kb
Host smart-4bc58bb5-b015-4b0d-86b7-eea09c47f8e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=902080374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixe
d.902080374
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.1834325392
Short name T691
Test name
Test status
Simulation time 414089491323 ps
CPU time 973.23 seconds
Started Jun 26 06:36:18 PM PDT 24
Finished Jun 26 06:52:34 PM PDT 24
Peak memory 201896 kb
Host smart-d844a1c1-f6ae-4fea-a1ba-91f5c7cc4fbd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834325392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.1834325392
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2346558404
Short name T580
Test name
Test status
Simulation time 599039501119 ps
CPU time 365.53 seconds
Started Jun 26 06:36:19 PM PDT 24
Finished Jun 26 06:42:26 PM PDT 24
Peak memory 201868 kb
Host smart-cd7eb7d1-d98e-428f-b283-c80df1fd3e1f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346558404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2346558404
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.3021083100
Short name T96
Test name
Test status
Simulation time 114502362847 ps
CPU time 503.78 seconds
Started Jun 26 06:36:18 PM PDT 24
Finished Jun 26 06:44:44 PM PDT 24
Peak memory 202204 kb
Host smart-f041d19b-867d-4af0-b4a8-6fe15040164c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021083100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3021083100
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.3832950576
Short name T353
Test name
Test status
Simulation time 33781984754 ps
CPU time 7.93 seconds
Started Jun 26 06:36:21 PM PDT 24
Finished Jun 26 06:36:32 PM PDT 24
Peak memory 201704 kb
Host smart-8849dee9-a685-410f-953a-3ff33af87023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832950576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3832950576
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.4215109879
Short name T118
Test name
Test status
Simulation time 5235965649 ps
CPU time 3.5 seconds
Started Jun 26 06:36:18 PM PDT 24
Finished Jun 26 06:36:23 PM PDT 24
Peak memory 201696 kb
Host smart-fc78abcb-e09d-48d3-83fc-32931a29f845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215109879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.4215109879
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.1750676018
Short name T445
Test name
Test status
Simulation time 5714646402 ps
CPU time 7.63 seconds
Started Jun 26 06:36:17 PM PDT 24
Finished Jun 26 06:36:25 PM PDT 24
Peak memory 201672 kb
Host smart-1e9f208e-15e8-40e4-a2bc-1b91a271eeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750676018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1750676018
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.726047692
Short name T486
Test name
Test status
Simulation time 400232725210 ps
CPU time 631.13 seconds
Started Jun 26 06:36:17 PM PDT 24
Finished Jun 26 06:46:49 PM PDT 24
Peak memory 202064 kb
Host smart-f4386445-7ff1-4594-8584-13b46ca2752c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726047692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
726047692
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1087861314
Short name T33
Test name
Test status
Simulation time 45534367969 ps
CPU time 72.75 seconds
Started Jun 26 06:36:19 PM PDT 24
Finished Jun 26 06:37:34 PM PDT 24
Peak memory 210572 kb
Host smart-a8c2d861-4425-4595-9df3-82c49577e896
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087861314 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.1087861314
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.159770978
Short name T616
Test name
Test status
Simulation time 476017534 ps
CPU time 0.88 seconds
Started Jun 26 06:36:44 PM PDT 24
Finished Jun 26 06:37:10 PM PDT 24
Peak memory 201692 kb
Host smart-4a27f230-9bef-4350-9c88-8ea474c15ec8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159770978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.159770978
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.404699150
Short name T254
Test name
Test status
Simulation time 510434635288 ps
CPU time 1165.17 seconds
Started Jun 26 06:36:34 PM PDT 24
Finished Jun 26 06:56:12 PM PDT 24
Peak memory 201924 kb
Host smart-da42da5b-7426-4a0a-b9db-e7f8bcb89b63
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404699150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gati
ng.404699150
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.952789891
Short name T563
Test name
Test status
Simulation time 519187079396 ps
CPU time 316.02 seconds
Started Jun 26 06:36:31 PM PDT 24
Finished Jun 26 06:41:56 PM PDT 24
Peak memory 201920 kb
Host smart-5a9dad34-a803-464b-9454-7a8674f3bba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952789891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.952789891
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.3258530238
Short name T329
Test name
Test status
Simulation time 496090962349 ps
CPU time 1103.94 seconds
Started Jun 26 06:36:31 PM PDT 24
Finished Jun 26 06:55:04 PM PDT 24
Peak memory 201956 kb
Host smart-b90f37c2-096c-461f-9cd6-e9c3b2286ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258530238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.3258530238
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1138935641
Short name T365
Test name
Test status
Simulation time 165921986852 ps
CPU time 358.83 seconds
Started Jun 26 06:36:48 PM PDT 24
Finished Jun 26 06:43:12 PM PDT 24
Peak memory 201748 kb
Host smart-38d888cd-c60d-4c77-bb39-e86e500d0a24
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138935641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1138935641
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.427873361
Short name T717
Test name
Test status
Simulation time 163692971599 ps
CPU time 102.56 seconds
Started Jun 26 06:36:34 PM PDT 24
Finished Jun 26 06:38:32 PM PDT 24
Peak memory 201868 kb
Host smart-5f26d79c-16f1-4f00-8e30-99ac0bbdd6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427873361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.427873361
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2176684784
Short name T653
Test name
Test status
Simulation time 495681974070 ps
CPU time 169.07 seconds
Started Jun 26 06:36:33 PM PDT 24
Finished Jun 26 06:39:34 PM PDT 24
Peak memory 201860 kb
Host smart-850fd99d-70ac-4117-8aaa-87eb78ba464b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176684784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2176684784
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.3571031008
Short name T524
Test name
Test status
Simulation time 363680143908 ps
CPU time 192.41 seconds
Started Jun 26 06:36:34 PM PDT 24
Finished Jun 26 06:40:01 PM PDT 24
Peak memory 201880 kb
Host smart-2c9241c2-edf3-4c05-ae11-8d30a198862d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571031008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.3571031008
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3559622472
Short name T26
Test name
Test status
Simulation time 607389584013 ps
CPU time 1347.4 seconds
Started Jun 26 06:36:33 PM PDT 24
Finished Jun 26 06:59:14 PM PDT 24
Peak memory 201908 kb
Host smart-f781ae03-6cfc-430d-b3a2-07bd460442f5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559622472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3559622472
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.3448799330
Short name T758
Test name
Test status
Simulation time 96743903408 ps
CPU time 393.2 seconds
Started Jun 26 06:36:32 PM PDT 24
Finished Jun 26 06:43:17 PM PDT 24
Peak memory 202268 kb
Host smart-43cea74c-b58b-4332-aa4b-545854395592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448799330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3448799330
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.531282341
Short name T450
Test name
Test status
Simulation time 45686764260 ps
CPU time 108.33 seconds
Started Jun 26 06:36:34 PM PDT 24
Finished Jun 26 06:38:37 PM PDT 24
Peak memory 201680 kb
Host smart-b7d7e2f6-8714-4084-8976-98cca05dcdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531282341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.531282341
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.1459920620
Short name T410
Test name
Test status
Simulation time 3983157780 ps
CPU time 4.96 seconds
Started Jun 26 06:36:33 PM PDT 24
Finished Jun 26 06:36:50 PM PDT 24
Peak memory 201688 kb
Host smart-da36f1f8-52a2-4f8e-a146-89eb9881d537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459920620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.1459920620
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.3937838160
Short name T400
Test name
Test status
Simulation time 5977828841 ps
CPU time 3.46 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:36:57 PM PDT 24
Peak memory 201688 kb
Host smart-87a401cc-74b1-429c-a08e-233e21027751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937838160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.3937838160
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.2046154449
Short name T207
Test name
Test status
Simulation time 302696680651 ps
CPU time 487.94 seconds
Started Jun 26 06:36:33 PM PDT 24
Finished Jun 26 06:44:53 PM PDT 24
Peak memory 202176 kb
Host smart-fa9a15f1-45bb-40e6-9a0f-d86c2d8532ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046154449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.2046154449
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1101593617
Short name T278
Test name
Test status
Simulation time 72280542848 ps
CPU time 150.08 seconds
Started Jun 26 06:36:31 PM PDT 24
Finished Jun 26 06:39:11 PM PDT 24
Peak memory 218004 kb
Host smart-993f00d9-8e7b-4501-9a05-b537edfffb75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101593617 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.1101593617
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.1085125221
Short name T628
Test name
Test status
Simulation time 390249128 ps
CPU time 1.51 seconds
Started Jun 26 06:36:42 PM PDT 24
Finished Jun 26 06:37:07 PM PDT 24
Peak memory 201560 kb
Host smart-185a0354-961e-4b03-93ed-c61546c60539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085125221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.1085125221
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.278610444
Short name T634
Test name
Test status
Simulation time 186164705249 ps
CPU time 2.98 seconds
Started Jun 26 06:36:40 PM PDT 24
Finished Jun 26 06:37:04 PM PDT 24
Peak memory 201872 kb
Host smart-a339d03d-d91f-414b-91fa-10310254b4b1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278610444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gati
ng.278610444
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.1494814435
Short name T240
Test name
Test status
Simulation time 369379238681 ps
CPU time 824.64 seconds
Started Jun 26 06:36:36 PM PDT 24
Finished Jun 26 06:50:38 PM PDT 24
Peak memory 201892 kb
Host smart-70e4dd43-5e9d-4b61-9c3e-0b14051051d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494814435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1494814435
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.2099073438
Short name T229
Test name
Test status
Simulation time 331849561669 ps
CPU time 188.85 seconds
Started Jun 26 06:36:33 PM PDT 24
Finished Jun 26 06:39:56 PM PDT 24
Peak memory 201864 kb
Host smart-f9c1a8ca-f5e9-4eb5-aabe-56c017474d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099073438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2099073438
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.4271153227
Short name T458
Test name
Test status
Simulation time 167064498163 ps
CPU time 397.94 seconds
Started Jun 26 06:36:39 PM PDT 24
Finished Jun 26 06:43:38 PM PDT 24
Peak memory 201852 kb
Host smart-0ed21743-daec-41e7-a404-66421ae93351
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271153227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.4271153227
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.3545548824
Short name T108
Test name
Test status
Simulation time 490793543379 ps
CPU time 1163.57 seconds
Started Jun 26 06:36:34 PM PDT 24
Finished Jun 26 06:56:13 PM PDT 24
Peak memory 201888 kb
Host smart-0c7b64b2-27bf-4af0-aa70-88c1d0479645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545548824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3545548824
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.3332465587
Short name T444
Test name
Test status
Simulation time 161628210753 ps
CPU time 357.02 seconds
Started Jun 26 06:36:33 PM PDT 24
Finished Jun 26 06:42:42 PM PDT 24
Peak memory 201856 kb
Host smart-23170de2-5a0b-4f0f-b32d-aa9aa65625a1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332465587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.3332465587
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3864149434
Short name T694
Test name
Test status
Simulation time 538211292859 ps
CPU time 665.53 seconds
Started Jun 26 06:36:34 PM PDT 24
Finished Jun 26 06:47:55 PM PDT 24
Peak memory 201960 kb
Host smart-13b3ec1f-2fe7-4e4f-9ba5-62657ab4addd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864149434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3864149434
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2738944193
Short name T188
Test name
Test status
Simulation time 625504921682 ps
CPU time 386.44 seconds
Started Jun 26 06:36:34 PM PDT 24
Finished Jun 26 06:43:13 PM PDT 24
Peak memory 201840 kb
Host smart-b982fd4b-eaaf-4bd8-acee-50cec4d4eda5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738944193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2738944193
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.4245322624
Short name T213
Test name
Test status
Simulation time 82876223752 ps
CPU time 260.05 seconds
Started Jun 26 06:36:34 PM PDT 24
Finished Jun 26 06:41:09 PM PDT 24
Peak memory 202168 kb
Host smart-d8baed27-b6e4-495c-996c-eda5cbcc840f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245322624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.4245322624
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.3261649793
Short name T739
Test name
Test status
Simulation time 36321422454 ps
CPU time 5.73 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:36:59 PM PDT 24
Peak memory 201660 kb
Host smart-1900f204-4ad8-4562-af79-5160f4effcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261649793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3261649793
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.81377405
Short name T412
Test name
Test status
Simulation time 4260520901 ps
CPU time 3.48 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:36:57 PM PDT 24
Peak memory 201712 kb
Host smart-b7dfd1ba-6f4d-44b5-b141-1a80ee9c7e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81377405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.81377405
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.4085324696
Short name T439
Test name
Test status
Simulation time 6171184800 ps
CPU time 4.41 seconds
Started Jun 26 06:36:33 PM PDT 24
Finished Jun 26 06:36:49 PM PDT 24
Peak memory 201656 kb
Host smart-03ea18d3-222e-4e6a-85b1-0cef29a04549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085324696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.4085324696
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1633926253
Short name T321
Test name
Test status
Simulation time 668419436223 ps
CPU time 321.19 seconds
Started Jun 26 06:36:34 PM PDT 24
Finished Jun 26 06:42:10 PM PDT 24
Peak memory 201828 kb
Host smart-901432ef-6687-4a65-a068-167d84ba5584
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633926253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1633926253
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.649308194
Short name T341
Test name
Test status
Simulation time 220162010967 ps
CPU time 313.83 seconds
Started Jun 26 06:36:34 PM PDT 24
Finished Jun 26 06:42:03 PM PDT 24
Peak memory 217724 kb
Host smart-fb17f51c-01ae-4f7e-be1f-f795f7c9be0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649308194 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.649308194
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2635534337
Short name T773
Test name
Test status
Simulation time 328789480 ps
CPU time 1.04 seconds
Started Jun 26 06:30:01 PM PDT 24
Finished Jun 26 06:30:04 PM PDT 24
Peak memory 201616 kb
Host smart-d6544f57-c2ec-46d9-be3c-11ed8b232f90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635534337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2635534337
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.542247814
Short name T228
Test name
Test status
Simulation time 163708674586 ps
CPU time 351.71 seconds
Started Jun 26 06:30:03 PM PDT 24
Finished Jun 26 06:35:56 PM PDT 24
Peak memory 201952 kb
Host smart-4f1d5df6-370f-4357-8a83-b68e986e715e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542247814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.542247814
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1347485282
Short name T660
Test name
Test status
Simulation time 167498141409 ps
CPU time 185.3 seconds
Started Jun 26 06:30:16 PM PDT 24
Finished Jun 26 06:33:23 PM PDT 24
Peak memory 201856 kb
Host smart-d8249aa6-bf23-4eac-91b9-c74982f214d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347485282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.1347485282
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.637703032
Short name T318
Test name
Test status
Simulation time 497865347137 ps
CPU time 1115.11 seconds
Started Jun 26 06:30:00 PM PDT 24
Finished Jun 26 06:48:37 PM PDT 24
Peak memory 201948 kb
Host smart-e6475f88-4662-4f53-aa87-8c4310ded4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637703032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.637703032
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.745199135
Short name T581
Test name
Test status
Simulation time 326819791548 ps
CPU time 208.26 seconds
Started Jun 26 06:30:04 PM PDT 24
Finished Jun 26 06:33:34 PM PDT 24
Peak memory 201868 kb
Host smart-10669e4f-1cfe-4e55-a7f7-0b10259c36b6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=745199135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed
.745199135
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.3921050182
Short name T474
Test name
Test status
Simulation time 361014868093 ps
CPU time 742.55 seconds
Started Jun 26 06:30:10 PM PDT 24
Finished Jun 26 06:42:35 PM PDT 24
Peak memory 201844 kb
Host smart-ba3dcb28-9c21-40a9-9c4c-f3a851587527
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921050182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.3921050182
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2507489646
Short name T352
Test name
Test status
Simulation time 205979718631 ps
CPU time 226.05 seconds
Started Jun 26 06:30:09 PM PDT 24
Finished Jun 26 06:33:56 PM PDT 24
Peak memory 201868 kb
Host smart-36039cfd-3717-4b4e-ab9a-e0da70605c26
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507489646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.2507489646
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.4109887953
Short name T338
Test name
Test status
Simulation time 131260793302 ps
CPU time 452.64 seconds
Started Jun 26 06:30:08 PM PDT 24
Finished Jun 26 06:37:42 PM PDT 24
Peak memory 202220 kb
Host smart-afa123f6-d82d-436b-b054-8e9d2287781b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109887953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.4109887953
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.3853081472
Short name T576
Test name
Test status
Simulation time 22322403708 ps
CPU time 12.27 seconds
Started Jun 26 06:30:09 PM PDT 24
Finished Jun 26 06:30:22 PM PDT 24
Peak memory 201668 kb
Host smart-e55fd666-167e-4658-b2e9-d16304465470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853081472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.3853081472
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.612334501
Short name T619
Test name
Test status
Simulation time 5371180645 ps
CPU time 12.71 seconds
Started Jun 26 06:30:10 PM PDT 24
Finished Jun 26 06:30:25 PM PDT 24
Peak memory 201712 kb
Host smart-cc02659b-1f8f-4918-bc1a-f2b223b80812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612334501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.612334501
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2074404321
Short name T83
Test name
Test status
Simulation time 7899691281 ps
CPU time 19.58 seconds
Started Jun 26 06:30:17 PM PDT 24
Finished Jun 26 06:30:40 PM PDT 24
Peak memory 218192 kb
Host smart-c177668e-ce48-400e-a4ee-1313acf39e97
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074404321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2074404321
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.4207588065
Short name T526
Test name
Test status
Simulation time 5657113600 ps
CPU time 14.54 seconds
Started Jun 26 06:30:03 PM PDT 24
Finished Jun 26 06:30:19 PM PDT 24
Peak memory 201704 kb
Host smart-386c31b0-203c-43fd-bf33-79e0902a0735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207588065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.4207588065
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3373548143
Short name T553
Test name
Test status
Simulation time 123453800560 ps
CPU time 252.24 seconds
Started Jun 26 06:30:00 PM PDT 24
Finished Jun 26 06:34:14 PM PDT 24
Peak memory 210492 kb
Host smart-fc7967b5-ed36-41c9-b30e-a62fa3f9a750
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373548143 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3373548143
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2393052592
Short name T716
Test name
Test status
Simulation time 331154907 ps
CPU time 0.82 seconds
Started Jun 26 06:36:36 PM PDT 24
Finished Jun 26 06:36:54 PM PDT 24
Peak memory 201548 kb
Host smart-3ceca591-ed03-4cb2-811f-002b94392c01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393052592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2393052592
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.3284118431
Short name T178
Test name
Test status
Simulation time 332074055677 ps
CPU time 111.53 seconds
Started Jun 26 06:36:36 PM PDT 24
Finished Jun 26 06:38:45 PM PDT 24
Peak memory 201848 kb
Host smart-d8d5b1f9-e5b0-44df-9bed-6d0b82d5bd4a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284118431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.3284118431
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.2310678671
Short name T301
Test name
Test status
Simulation time 162496618410 ps
CPU time 99.98 seconds
Started Jun 26 06:36:37 PM PDT 24
Finished Jun 26 06:38:36 PM PDT 24
Peak memory 201856 kb
Host smart-2deab06c-a8ef-4503-aca0-6327b8d8e4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310678671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.2310678671
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.1378048283
Short name T471
Test name
Test status
Simulation time 497053067514 ps
CPU time 1090.86 seconds
Started Jun 26 06:36:33 PM PDT 24
Finished Jun 26 06:54:56 PM PDT 24
Peak memory 201932 kb
Host smart-34e69123-4880-4d9f-8da7-dc0910298cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378048283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1378048283
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3035363374
Short name T566
Test name
Test status
Simulation time 163132716105 ps
CPU time 95.74 seconds
Started Jun 26 06:36:41 PM PDT 24
Finished Jun 26 06:38:39 PM PDT 24
Peak memory 201876 kb
Host smart-092915f8-1a38-4e79-98f3-ac542996399b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035363374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.3035363374
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.1990182279
Short name T534
Test name
Test status
Simulation time 162125529195 ps
CPU time 50.63 seconds
Started Jun 26 06:36:59 PM PDT 24
Finished Jun 26 06:38:14 PM PDT 24
Peak memory 201876 kb
Host smart-63bbec4c-1060-4cc9-ae03-f075c3760c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990182279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1990182279
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.3568239130
Short name T455
Test name
Test status
Simulation time 166412593122 ps
CPU time 35.92 seconds
Started Jun 26 06:36:33 PM PDT 24
Finished Jun 26 06:37:23 PM PDT 24
Peak memory 201848 kb
Host smart-a5244c22-0214-44b5-b712-280145888029
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568239130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.3568239130
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.2935717938
Short name T255
Test name
Test status
Simulation time 169350369533 ps
CPU time 111.46 seconds
Started Jun 26 06:36:59 PM PDT 24
Finished Jun 26 06:39:15 PM PDT 24
Peak memory 201584 kb
Host smart-b7f02c5b-c5c1-4c0d-b7b0-4020bf182bf3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935717938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.2935717938
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.3322488954
Short name T774
Test name
Test status
Simulation time 391376948023 ps
CPU time 888.86 seconds
Started Jun 26 06:36:38 PM PDT 24
Finished Jun 26 06:51:46 PM PDT 24
Peak memory 201840 kb
Host smart-3f800e85-0856-47a9-8a36-4aa868f6bffa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322488954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.3322488954
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2378165906
Short name T201
Test name
Test status
Simulation time 103350902054 ps
CPU time 548.4 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:46:00 PM PDT 24
Peak memory 202252 kb
Host smart-582353e6-acaa-4cf6-a948-0742df48ed80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378165906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2378165906
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.1818747191
Short name T50
Test name
Test status
Simulation time 50267236830 ps
CPU time 110.48 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:38:42 PM PDT 24
Peak memory 201684 kb
Host smart-5b809ad2-aad6-40ab-91c3-a021e1aab738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818747191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1818747191
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.1663988107
Short name T477
Test name
Test status
Simulation time 3030172518 ps
CPU time 7.06 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:36:58 PM PDT 24
Peak memory 201688 kb
Host smart-e746e766-5f3d-43e6-9ff2-a0964f6389fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663988107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.1663988107
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.820744159
Short name T696
Test name
Test status
Simulation time 5853210510 ps
CPU time 14.52 seconds
Started Jun 26 06:36:34 PM PDT 24
Finished Jun 26 06:37:01 PM PDT 24
Peak memory 201680 kb
Host smart-52055f7b-63d4-4580-8efa-85e1d1cb9542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820744159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.820744159
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.358426885
Short name T277
Test name
Test status
Simulation time 249683297997 ps
CPU time 553.14 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:46:04 PM PDT 24
Peak memory 201864 kb
Host smart-ec6ac91b-7cd2-4e75-a5f5-e65cdc5de886
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358426885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.
358426885
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.664578026
Short name T22
Test name
Test status
Simulation time 37605265713 ps
CPU time 130.69 seconds
Started Jun 26 06:36:59 PM PDT 24
Finished Jun 26 06:39:34 PM PDT 24
Peak memory 210512 kb
Host smart-9f591367-ca68-4c19-9873-8a7716156878
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664578026 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.664578026
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.1592688749
Short name T355
Test name
Test status
Simulation time 529481571 ps
CPU time 0.91 seconds
Started Jun 26 06:36:44 PM PDT 24
Finished Jun 26 06:37:10 PM PDT 24
Peak memory 201516 kb
Host smart-71022d38-da44-49a2-b901-cc02cd978b78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592688749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1592688749
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.3455252242
Short name T680
Test name
Test status
Simulation time 162629968565 ps
CPU time 6.09 seconds
Started Jun 26 06:36:39 PM PDT 24
Finished Jun 26 06:37:06 PM PDT 24
Peak memory 201864 kb
Host smart-09db05d8-ea8e-4a07-887d-52bf9cb995bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455252242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.3455252242
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.3582697351
Short name T288
Test name
Test status
Simulation time 406653073861 ps
CPU time 873.98 seconds
Started Jun 26 06:36:39 PM PDT 24
Finished Jun 26 06:51:34 PM PDT 24
Peak memory 201880 kb
Host smart-6b44d960-3ae4-4cfb-b46f-3d355d7eaa06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582697351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.3582697351
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1396550369
Short name T442
Test name
Test status
Simulation time 169797700756 ps
CPU time 364.31 seconds
Started Jun 26 06:36:38 PM PDT 24
Finished Jun 26 06:43:02 PM PDT 24
Peak memory 201868 kb
Host smart-11671c80-4133-4ec5-9ec6-e91e16b610bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396550369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1396550369
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2065225343
Short name T437
Test name
Test status
Simulation time 159658384965 ps
CPU time 384.45 seconds
Started Jun 26 06:36:38 PM PDT 24
Finished Jun 26 06:43:22 PM PDT 24
Peak memory 201952 kb
Host smart-fe92cb4f-a3d2-4de5-99d1-78ebe4713347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065225343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2065225343
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2664548252
Short name T667
Test name
Test status
Simulation time 161986102050 ps
CPU time 387.59 seconds
Started Jun 26 06:36:38 PM PDT 24
Finished Jun 26 06:43:25 PM PDT 24
Peak memory 201860 kb
Host smart-9be55f03-4f69-48bc-92db-ef633a204bf5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664548252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2664548252
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.3956591814
Short name T43
Test name
Test status
Simulation time 186958442456 ps
CPU time 439.43 seconds
Started Jun 26 06:36:39 PM PDT 24
Finished Jun 26 06:44:19 PM PDT 24
Peak memory 201876 kb
Host smart-1be080c7-2348-47c1-8276-7a398f64ab99
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956591814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.3956591814
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1553946570
Short name T405
Test name
Test status
Simulation time 619276577854 ps
CPU time 387.9 seconds
Started Jun 26 06:36:40 PM PDT 24
Finished Jun 26 06:43:29 PM PDT 24
Peak memory 201884 kb
Host smart-823682be-0870-4fe8-bebb-f95bbe668786
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553946570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1553946570
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.1656815787
Short name T624
Test name
Test status
Simulation time 78264757084 ps
CPU time 314.53 seconds
Started Jun 26 06:36:42 PM PDT 24
Finished Jun 26 06:42:20 PM PDT 24
Peak memory 202104 kb
Host smart-a581f444-c1c7-42bd-be33-2afbfec81fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656815787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1656815787
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.2048766200
Short name T387
Test name
Test status
Simulation time 45113404084 ps
CPU time 91.2 seconds
Started Jun 26 06:36:39 PM PDT 24
Finished Jun 26 06:38:31 PM PDT 24
Peak memory 201708 kb
Host smart-28d8df82-155d-42ff-a4ae-acdb4b776478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048766200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2048766200
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.2593562794
Short name T782
Test name
Test status
Simulation time 4909558899 ps
CPU time 3.57 seconds
Started Jun 26 06:36:39 PM PDT 24
Finished Jun 26 06:37:03 PM PDT 24
Peak memory 201672 kb
Host smart-3ee0baef-495f-4db6-8605-1dd27d9852ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593562794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2593562794
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.3230996372
Short name T378
Test name
Test status
Simulation time 5586446622 ps
CPU time 12.56 seconds
Started Jun 26 06:36:36 PM PDT 24
Finished Jun 26 06:37:06 PM PDT 24
Peak memory 201612 kb
Host smart-04cff2fa-1551-48f2-a2f4-1ea727a3b903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230996372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3230996372
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.3251192654
Short name T792
Test name
Test status
Simulation time 335942678900 ps
CPU time 776.12 seconds
Started Jun 26 06:36:44 PM PDT 24
Finished Jun 26 06:50:04 PM PDT 24
Peak memory 201932 kb
Host smart-9fb92a36-312e-49b6-bc25-79f1134ba565
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251192654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.3251192654
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3810222147
Short name T40
Test name
Test status
Simulation time 234388023983 ps
CPU time 61.39 seconds
Started Jun 26 06:36:39 PM PDT 24
Finished Jun 26 06:38:01 PM PDT 24
Peak memory 210188 kb
Host smart-ac2181f4-c205-4cce-9d1b-ac0087e2b589
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810222147 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3810222147
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2836843347
Short name T754
Test name
Test status
Simulation time 370167552 ps
CPU time 0.84 seconds
Started Jun 26 06:36:37 PM PDT 24
Finished Jun 26 06:36:56 PM PDT 24
Peak memory 201640 kb
Host smart-fac104ab-beda-48f4-95f6-73a0d6a02bf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836843347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2836843347
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3619129599
Short name T789
Test name
Test status
Simulation time 342851340912 ps
CPU time 523.48 seconds
Started Jun 26 06:36:44 PM PDT 24
Finished Jun 26 06:45:53 PM PDT 24
Peak memory 201880 kb
Host smart-e8e1f69e-5612-45e6-acf0-d6fbba7232b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619129599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3619129599
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.3827805281
Short name T561
Test name
Test status
Simulation time 492788381882 ps
CPU time 559.16 seconds
Started Jun 26 06:36:46 PM PDT 24
Finished Jun 26 06:46:31 PM PDT 24
Peak memory 201892 kb
Host smart-4b79ddcf-48fc-4c2b-ac44-8fa226229663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827805281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3827805281
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.740903717
Short name T296
Test name
Test status
Simulation time 166063641794 ps
CPU time 210.49 seconds
Started Jun 26 06:36:44 PM PDT 24
Finished Jun 26 06:40:39 PM PDT 24
Peak memory 201888 kb
Host smart-1bed5e48-70a0-436b-903f-029469aab37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740903717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.740903717
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.455677703
Short name T438
Test name
Test status
Simulation time 484895270264 ps
CPU time 290.96 seconds
Started Jun 26 06:36:42 PM PDT 24
Finished Jun 26 06:41:56 PM PDT 24
Peak memory 201864 kb
Host smart-5280feea-782b-467d-b5d1-4437d088173d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=455677703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrup
t_fixed.455677703
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.4061511741
Short name T569
Test name
Test status
Simulation time 165384302980 ps
CPU time 102.12 seconds
Started Jun 26 06:36:41 PM PDT 24
Finished Jun 26 06:38:45 PM PDT 24
Peak memory 201560 kb
Host smart-6fc02ef0-cced-4acd-b551-5eb503988af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061511741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.4061511741
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.859020742
Short name T528
Test name
Test status
Simulation time 324140604735 ps
CPU time 194.16 seconds
Started Jun 26 06:36:43 PM PDT 24
Finished Jun 26 06:40:22 PM PDT 24
Peak memory 201808 kb
Host smart-cbd88737-612e-4949-be48-6453a54608de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=859020742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.859020742
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.2987659867
Short name T244
Test name
Test status
Simulation time 374886516615 ps
CPU time 442.06 seconds
Started Jun 26 06:36:44 PM PDT 24
Finished Jun 26 06:44:31 PM PDT 24
Peak memory 201896 kb
Host smart-a43af74e-c7f5-4ab8-b452-cd95c8c95595
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987659867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.2987659867
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3598223392
Short name T470
Test name
Test status
Simulation time 391537584468 ps
CPU time 415.08 seconds
Started Jun 26 06:36:44 PM PDT 24
Finished Jun 26 06:44:04 PM PDT 24
Peak memory 201936 kb
Host smart-fe1ba028-b649-4b0b-b608-be07880022a1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598223392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3598223392
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.699164137
Short name T206
Test name
Test status
Simulation time 93023514605 ps
CPU time 308.98 seconds
Started Jun 26 06:36:47 PM PDT 24
Finished Jun 26 06:42:22 PM PDT 24
Peak memory 202260 kb
Host smart-d28499ad-1132-4ac1-8216-dec6bbfec8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699164137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.699164137
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3036646148
Short name T631
Test name
Test status
Simulation time 44252906688 ps
CPU time 26.58 seconds
Started Jun 26 06:36:47 PM PDT 24
Finished Jun 26 06:37:38 PM PDT 24
Peak memory 201624 kb
Host smart-34bb53fc-c8e9-49ca-9225-fb73d7355ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036646148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3036646148
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.643864209
Short name T463
Test name
Test status
Simulation time 3019602352 ps
CPU time 4.13 seconds
Started Jun 26 06:36:46 PM PDT 24
Finished Jun 26 06:37:16 PM PDT 24
Peak memory 201684 kb
Host smart-3f3a6e4f-457b-4f3a-a343-4971a7110c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643864209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.643864209
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.751639094
Short name T558
Test name
Test status
Simulation time 5840984292 ps
CPU time 3.92 seconds
Started Jun 26 06:36:41 PM PDT 24
Finished Jun 26 06:37:07 PM PDT 24
Peak memory 201468 kb
Host smart-bb4345e4-11a3-4069-943e-109b9e11c140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751639094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.751639094
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.1925170754
Short name T764
Test name
Test status
Simulation time 22615768562 ps
CPU time 41.6 seconds
Started Jun 26 06:36:45 PM PDT 24
Finished Jun 26 06:37:53 PM PDT 24
Peak memory 201872 kb
Host smart-925c474a-a95c-4c6f-9a0d-4eff682febb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925170754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.1925170754
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2342179260
Short name T103
Test name
Test status
Simulation time 273234846893 ps
CPU time 170.5 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:39:44 PM PDT 24
Peak memory 218692 kb
Host smart-fff7a6db-eb6f-4448-80d4-d0bfcb76d645
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342179260 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2342179260
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.3756311291
Short name T351
Test name
Test status
Simulation time 372490943 ps
CPU time 1.42 seconds
Started Jun 26 06:36:37 PM PDT 24
Finished Jun 26 06:36:57 PM PDT 24
Peak memory 201608 kb
Host smart-6c61da48-21ed-407b-98f9-628cca88af42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756311291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.3756311291
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1393143490
Short name T256
Test name
Test status
Simulation time 517491773231 ps
CPU time 1218.64 seconds
Started Jun 26 06:36:33 PM PDT 24
Finished Jun 26 06:57:04 PM PDT 24
Peak memory 201892 kb
Host smart-f2ed2493-3917-4ea9-8d5d-15a34dfc1062
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393143490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1393143490
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2961734415
Short name T645
Test name
Test status
Simulation time 499787072732 ps
CPU time 308.23 seconds
Started Jun 26 06:36:34 PM PDT 24
Finished Jun 26 06:41:57 PM PDT 24
Peak memory 201780 kb
Host smart-bddfc426-dc7a-4ab1-9b04-f004fb88feac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961734415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2961734415
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1728408918
Short name T398
Test name
Test status
Simulation time 483121923621 ps
CPU time 288.41 seconds
Started Jun 26 06:36:34 PM PDT 24
Finished Jun 26 06:41:35 PM PDT 24
Peak memory 201812 kb
Host smart-e68c4c14-bfb5-4619-a425-9973897c688c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728408918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1728408918
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.1641279429
Short name T710
Test name
Test status
Simulation time 158706351190 ps
CPU time 86.96 seconds
Started Jun 26 06:36:33 PM PDT 24
Finished Jun 26 06:38:12 PM PDT 24
Peak memory 201884 kb
Host smart-3121ded1-6085-4b74-a422-50c07f90b582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641279429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.1641279429
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2453075169
Short name T583
Test name
Test status
Simulation time 319024163863 ps
CPU time 761.39 seconds
Started Jun 26 06:36:32 PM PDT 24
Finished Jun 26 06:49:25 PM PDT 24
Peak memory 201908 kb
Host smart-04a2350e-8e8e-46e0-aceb-9af5f19f44a9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453075169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2453075169
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.2183644732
Short name T261
Test name
Test status
Simulation time 346392001548 ps
CPU time 413.5 seconds
Started Jun 26 06:36:55 PM PDT 24
Finished Jun 26 06:44:13 PM PDT 24
Peak memory 201916 kb
Host smart-e5c72329-e988-408f-abb9-3a08b3ac232d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183644732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.2183644732
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.2156011280
Short name T638
Test name
Test status
Simulation time 195066322958 ps
CPU time 118.78 seconds
Started Jun 26 06:36:34 PM PDT 24
Finished Jun 26 06:38:48 PM PDT 24
Peak memory 201836 kb
Host smart-676f700a-b55e-4078-aafc-ce6f2c8f1f7a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156011280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.2156011280
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.4150696606
Short name T200
Test name
Test status
Simulation time 70492692493 ps
CPU time 389.43 seconds
Started Jun 26 06:36:41 PM PDT 24
Finished Jun 26 06:43:33 PM PDT 24
Peak memory 202240 kb
Host smart-c210dff4-7066-4c75-a8bf-c6dc728fd42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150696606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.4150696606
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.591919845
Short name T395
Test name
Test status
Simulation time 36129356751 ps
CPU time 21.44 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:37:13 PM PDT 24
Peak memory 201692 kb
Host smart-2ef788e3-bbfa-45ef-baa4-c78ebad8cafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591919845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.591919845
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.2753265959
Short name T711
Test name
Test status
Simulation time 4198139140 ps
CPU time 1.9 seconds
Started Jun 26 06:36:36 PM PDT 24
Finished Jun 26 06:36:57 PM PDT 24
Peak memory 201632 kb
Host smart-0e9cb5c2-e558-428c-9512-72064176b5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753265959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.2753265959
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2583835313
Short name T740
Test name
Test status
Simulation time 5704924511 ps
CPU time 4.29 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:36:55 PM PDT 24
Peak memory 201668 kb
Host smart-067813c0-efe5-4ad0-a005-104c15ad1f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583835313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2583835313
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.254674664
Short name T600
Test name
Test status
Simulation time 209859311948 ps
CPU time 99.25 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:38:30 PM PDT 24
Peak memory 201948 kb
Host smart-9ddfca1f-fe61-43a2-bfaa-9f54a61565bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254674664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.
254674664
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3526436053
Short name T18
Test name
Test status
Simulation time 243590059910 ps
CPU time 448.2 seconds
Started Jun 26 06:36:34 PM PDT 24
Finished Jun 26 06:44:17 PM PDT 24
Peak memory 210520 kb
Host smart-b279d1f0-27f8-41d7-ab0b-187652e39a64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526436053 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3526436053
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.729454724
Short name T537
Test name
Test status
Simulation time 469115765 ps
CPU time 0.89 seconds
Started Jun 26 06:36:39 PM PDT 24
Finished Jun 26 06:37:00 PM PDT 24
Peak memory 201652 kb
Host smart-07ac7d4e-02d6-4cc6-828d-81d5950f20ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729454724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.729454724
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.2959979388
Short name T722
Test name
Test status
Simulation time 165353700364 ps
CPU time 4.06 seconds
Started Jun 26 06:36:41 PM PDT 24
Finished Jun 26 06:37:07 PM PDT 24
Peak memory 201880 kb
Host smart-a232ddd5-65e4-4de0-868a-8b4fea778d9a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959979388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.2959979388
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1990874760
Short name T657
Test name
Test status
Simulation time 166092503594 ps
CPU time 106.91 seconds
Started Jun 26 06:36:45 PM PDT 24
Finished Jun 26 06:38:56 PM PDT 24
Peak memory 201972 kb
Host smart-1f83bb06-8da6-4f99-bea4-228972c0a418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990874760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1990874760
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.774579028
Short name T250
Test name
Test status
Simulation time 330038140196 ps
CPU time 162.29 seconds
Started Jun 26 06:36:34 PM PDT 24
Finished Jun 26 06:39:31 PM PDT 24
Peak memory 201868 kb
Host smart-50a4c613-b747-44b8-8b93-814614620de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774579028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.774579028
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2245689233
Short name T648
Test name
Test status
Simulation time 170353670637 ps
CPU time 384.85 seconds
Started Jun 26 06:36:42 PM PDT 24
Finished Jun 26 06:43:30 PM PDT 24
Peak memory 201816 kb
Host smart-1e87b5f9-ff37-4426-8217-1c1f0d06aae6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245689233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.2245689233
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.1184884039
Short name T179
Test name
Test status
Simulation time 489304405448 ps
CPU time 1082.48 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:54:56 PM PDT 24
Peak memory 201932 kb
Host smart-76d651e1-37e1-45c6-b6dc-1dde26b873f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184884039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1184884039
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.4231243687
Short name T3
Test name
Test status
Simulation time 492648166105 ps
CPU time 272.11 seconds
Started Jun 26 06:36:34 PM PDT 24
Finished Jun 26 06:41:23 PM PDT 24
Peak memory 201904 kb
Host smart-e40e8888-f048-4dbc-8f4f-8d802dfc0761
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231243687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.4231243687
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2551635018
Short name T610
Test name
Test status
Simulation time 444788986215 ps
CPU time 1035.67 seconds
Started Jun 26 06:36:39 PM PDT 24
Finished Jun 26 06:54:13 PM PDT 24
Peak memory 201956 kb
Host smart-c0487000-87b3-4eaf-a1f4-cbfefe0e9165
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551635018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2551635018
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.937107781
Short name T540
Test name
Test status
Simulation time 614060281873 ps
CPU time 285.44 seconds
Started Jun 26 06:36:38 PM PDT 24
Finished Jun 26 06:41:42 PM PDT 24
Peak memory 201860 kb
Host smart-6cd020ea-b0c5-4c74-aeeb-fb98407cf2c6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937107781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
adc_ctrl_filters_wakeup_fixed.937107781
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.3018403984
Short name T772
Test name
Test status
Simulation time 138049906218 ps
CPU time 467.68 seconds
Started Jun 26 06:36:40 PM PDT 24
Finished Jun 26 06:44:49 PM PDT 24
Peak memory 202284 kb
Host smart-9bae09f4-fc62-45db-9db2-6dc0cae2770f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018403984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3018403984
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1086378145
Short name T379
Test name
Test status
Simulation time 39345824670 ps
CPU time 43.41 seconds
Started Jun 26 06:36:37 PM PDT 24
Finished Jun 26 06:37:39 PM PDT 24
Peak memory 201676 kb
Host smart-4aea8706-c768-4d90-bec9-4edf612bb4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086378145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1086378145
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.4121349552
Short name T702
Test name
Test status
Simulation time 4893865802 ps
CPU time 2.95 seconds
Started Jun 26 06:36:42 PM PDT 24
Finished Jun 26 06:37:08 PM PDT 24
Peak memory 201648 kb
Host smart-89eaa61f-1b3e-4d54-844e-374cf5985706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121349552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.4121349552
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.3790217510
Short name T466
Test name
Test status
Simulation time 5953324454 ps
CPU time 4.83 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:36:56 PM PDT 24
Peak memory 201688 kb
Host smart-48160edb-fb4d-4a30-bc23-fd51a4185991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790217510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.3790217510
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.3541351237
Short name T547
Test name
Test status
Simulation time 600247330552 ps
CPU time 254.26 seconds
Started Jun 26 06:37:02 PM PDT 24
Finished Jun 26 06:41:41 PM PDT 24
Peak memory 210508 kb
Host smart-77c06b5c-3d83-4d91-9e16-3390214ea183
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541351237 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.3541351237
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2783877839
Short name T376
Test name
Test status
Simulation time 340354582 ps
CPU time 1.35 seconds
Started Jun 26 06:36:46 PM PDT 24
Finished Jun 26 06:37:13 PM PDT 24
Peak memory 201568 kb
Host smart-9361635a-2f43-4911-afb8-232f489345ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783877839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2783877839
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2343551706
Short name T154
Test name
Test status
Simulation time 331497217372 ps
CPU time 350.11 seconds
Started Jun 26 06:36:46 PM PDT 24
Finished Jun 26 06:43:02 PM PDT 24
Peak memory 201944 kb
Host smart-c62bbb17-0f0a-4450-8f97-dca3ab9e552b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343551706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2343551706
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.2369012907
Short name T173
Test name
Test status
Simulation time 531964559693 ps
CPU time 212.32 seconds
Started Jun 26 06:36:44 PM PDT 24
Finished Jun 26 06:40:41 PM PDT 24
Peak memory 201900 kb
Host smart-aff3de09-5e41-44a8-ab19-004ff0c831b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369012907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2369012907
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.4128110326
Short name T283
Test name
Test status
Simulation time 167698985735 ps
CPU time 200.23 seconds
Started Jun 26 06:36:42 PM PDT 24
Finished Jun 26 06:40:25 PM PDT 24
Peak memory 201844 kb
Host smart-01bee96f-59c3-4ccb-96c6-9fc0b6e1eb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128110326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.4128110326
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1247918733
Short name T506
Test name
Test status
Simulation time 488307585714 ps
CPU time 1072.32 seconds
Started Jun 26 06:36:45 PM PDT 24
Finished Jun 26 06:55:03 PM PDT 24
Peak memory 201856 kb
Host smart-10a4db5a-0ec7-4257-9597-b77ce4590870
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247918733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1247918733
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.642293339
Short name T29
Test name
Test status
Simulation time 169348279633 ps
CPU time 171.87 seconds
Started Jun 26 06:36:39 PM PDT 24
Finished Jun 26 06:39:51 PM PDT 24
Peak memory 201988 kb
Host smart-e7734a20-c27b-4f18-bfc6-6126f341e840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642293339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.642293339
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2057405006
Short name T679
Test name
Test status
Simulation time 492411225754 ps
CPU time 558.63 seconds
Started Jun 26 06:36:40 PM PDT 24
Finished Jun 26 06:46:20 PM PDT 24
Peak memory 201876 kb
Host smart-ca8fe812-3be2-46cc-b924-2ad38040af28
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057405006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2057405006
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2032547040
Short name T453
Test name
Test status
Simulation time 608407327099 ps
CPU time 632.44 seconds
Started Jun 26 06:36:43 PM PDT 24
Finished Jun 26 06:47:40 PM PDT 24
Peak memory 201872 kb
Host smart-ad7cacbf-5d4f-4130-ac63-b8abacdbacd6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032547040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.2032547040
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.785667170
Short name T503
Test name
Test status
Simulation time 71109275571 ps
CPU time 266.48 seconds
Started Jun 26 06:36:46 PM PDT 24
Finished Jun 26 06:41:38 PM PDT 24
Peak memory 202168 kb
Host smart-99ba2cdf-d3cc-49fd-af80-9c50ec87e6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785667170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.785667170
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2360208354
Short name T460
Test name
Test status
Simulation time 38860761978 ps
CPU time 21.82 seconds
Started Jun 26 06:36:51 PM PDT 24
Finished Jun 26 06:37:39 PM PDT 24
Peak memory 201664 kb
Host smart-318cec70-7aae-451b-a8b2-10a614cbd800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360208354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2360208354
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.4090951279
Short name T459
Test name
Test status
Simulation time 5062086146 ps
CPU time 7.52 seconds
Started Jun 26 06:36:55 PM PDT 24
Finished Jun 26 06:37:27 PM PDT 24
Peak memory 201660 kb
Host smart-f1017839-cddc-4121-8ba0-a0a18c03c0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090951279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.4090951279
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.2845117368
Short name T457
Test name
Test status
Simulation time 5854302508 ps
CPU time 7.17 seconds
Started Jun 26 06:36:59 PM PDT 24
Finished Jun 26 06:37:30 PM PDT 24
Peak memory 201488 kb
Host smart-9a1a48dd-5ffa-428b-ab02-701aaffeb360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845117368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.2845117368
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2242008767
Short name T347
Test name
Test status
Simulation time 123333446974 ps
CPU time 375.48 seconds
Started Jun 26 06:36:46 PM PDT 24
Finished Jun 26 06:43:27 PM PDT 24
Peak memory 202120 kb
Host smart-addb6055-47cb-4448-8617-e54e9298dc60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242008767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2242008767
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.3479335877
Short name T433
Test name
Test status
Simulation time 504805271 ps
CPU time 1.15 seconds
Started Jun 26 06:36:34 PM PDT 24
Finished Jun 26 06:36:50 PM PDT 24
Peak memory 201624 kb
Host smart-a221d090-58e4-4c76-a17d-48068841e0da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479335877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.3479335877
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.1597590876
Short name T243
Test name
Test status
Simulation time 166295386016 ps
CPU time 191.29 seconds
Started Jun 26 06:36:34 PM PDT 24
Finished Jun 26 06:40:00 PM PDT 24
Peak memory 201832 kb
Host smart-b9128e85-6dad-4073-a68f-2bfaf5a7f4fa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597590876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.1597590876
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.3298216433
Short name T239
Test name
Test status
Simulation time 325705293489 ps
CPU time 766.24 seconds
Started Jun 26 06:36:33 PM PDT 24
Finished Jun 26 06:49:33 PM PDT 24
Peak memory 201916 kb
Host smart-e4fd7c7e-cc5e-4b87-8630-75ee3dd633b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298216433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3298216433
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2422228578
Short name T443
Test name
Test status
Simulation time 324396216385 ps
CPU time 189.26 seconds
Started Jun 26 06:36:45 PM PDT 24
Finished Jun 26 06:40:20 PM PDT 24
Peak memory 201852 kb
Host smart-80b8c769-2358-468e-be79-b6139c338f9e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422228578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.2422228578
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3679806213
Short name T165
Test name
Test status
Simulation time 487825794308 ps
CPU time 114.22 seconds
Started Jun 26 06:36:46 PM PDT 24
Finished Jun 26 06:39:06 PM PDT 24
Peak memory 201932 kb
Host smart-537ec843-7832-4fb2-a113-8d4dd711c9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679806213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3679806213
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2316791761
Short name T27
Test name
Test status
Simulation time 326243408961 ps
CPU time 351.27 seconds
Started Jun 26 06:36:46 PM PDT 24
Finished Jun 26 06:43:03 PM PDT 24
Peak memory 201752 kb
Host smart-cce096ab-0464-4d34-a39a-8a2164019ffb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316791761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2316791761
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.3884651024
Short name T308
Test name
Test status
Simulation time 401228174373 ps
CPU time 953.72 seconds
Started Jun 26 06:36:34 PM PDT 24
Finished Jun 26 06:52:43 PM PDT 24
Peak memory 201900 kb
Host smart-f132b91c-74d3-4cd1-a89b-0f07f9c21a00
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884651024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.3884651024
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3234784097
Short name T611
Test name
Test status
Simulation time 195013075913 ps
CPU time 452.21 seconds
Started Jun 26 06:36:33 PM PDT 24
Finished Jun 26 06:44:19 PM PDT 24
Peak memory 201848 kb
Host smart-0505e010-7b9f-4630-b4c5-25de91f0bca2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234784097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.3234784097
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.2990293178
Short name T737
Test name
Test status
Simulation time 69990034406 ps
CPU time 263.76 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:41:15 PM PDT 24
Peak memory 202264 kb
Host smart-0058e369-0e5e-4c05-aa4c-c8d1b817ae97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990293178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.2990293178
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.1270474830
Short name T712
Test name
Test status
Simulation time 23791285067 ps
CPU time 14.13 seconds
Started Jun 26 06:36:34 PM PDT 24
Finished Jun 26 06:37:03 PM PDT 24
Peak memory 201544 kb
Host smart-132a65bc-1b42-4559-92a6-28b6b1cdf964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270474830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.1270474830
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.47133658
Short name T435
Test name
Test status
Simulation time 3840246635 ps
CPU time 3.05 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:36:54 PM PDT 24
Peak memory 201652 kb
Host smart-bde5e8a9-de80-4fd9-82b3-67e7ab164de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47133658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.47133658
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.605357511
Short name T501
Test name
Test status
Simulation time 5588142723 ps
CPU time 7.17 seconds
Started Jun 26 06:36:47 PM PDT 24
Finished Jun 26 06:37:21 PM PDT 24
Peak memory 201620 kb
Host smart-3b617b72-bec9-4330-a6c9-5b977d918687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605357511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.605357511
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2613125683
Short name T468
Test name
Test status
Simulation time 186991169304 ps
CPU time 425.72 seconds
Started Jun 26 06:36:38 PM PDT 24
Finished Jun 26 06:44:03 PM PDT 24
Peak memory 201912 kb
Host smart-dde4d2ca-68fd-4c1f-a645-2b974525823b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613125683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2613125683
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.2883928620
Short name T761
Test name
Test status
Simulation time 52541375414 ps
CPU time 182.36 seconds
Started Jun 26 06:36:33 PM PDT 24
Finished Jun 26 06:39:49 PM PDT 24
Peak memory 210696 kb
Host smart-8cc54550-e1d1-4ede-88a6-d3cc386c5456
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883928620 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.2883928620
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2284813810
Short name T494
Test name
Test status
Simulation time 535701548 ps
CPU time 0.87 seconds
Started Jun 26 06:36:59 PM PDT 24
Finished Jun 26 06:37:24 PM PDT 24
Peak memory 201628 kb
Host smart-b9da9ee6-fcd1-4459-bd67-231067a9a6d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284813810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2284813810
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.3972791452
Short name T270
Test name
Test status
Simulation time 518304437075 ps
CPU time 157 seconds
Started Jun 26 06:36:37 PM PDT 24
Finished Jun 26 06:39:33 PM PDT 24
Peak memory 201904 kb
Host smart-bb2805dc-de83-4320-8fee-029ce435f2fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972791452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.3972791452
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.3070723796
Short name T313
Test name
Test status
Simulation time 331457236740 ps
CPU time 412.2 seconds
Started Jun 26 06:36:39 PM PDT 24
Finished Jun 26 06:43:52 PM PDT 24
Peak memory 201960 kb
Host smart-766db497-d1d8-403f-a7a0-8661d69cebf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070723796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3070723796
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1948586954
Short name T391
Test name
Test status
Simulation time 330570067230 ps
CPU time 780.71 seconds
Started Jun 26 06:36:33 PM PDT 24
Finished Jun 26 06:49:48 PM PDT 24
Peak memory 201912 kb
Host smart-b60d1d96-a147-46ee-93f8-03f527a087c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948586954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1948586954
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.778233252
Short name T198
Test name
Test status
Simulation time 489596437989 ps
CPU time 285.03 seconds
Started Jun 26 06:36:44 PM PDT 24
Finished Jun 26 06:41:53 PM PDT 24
Peak memory 201168 kb
Host smart-ae34ae47-46a3-440a-a6a6-37cb1f431620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778233252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.778233252
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2817294899
Short name T622
Test name
Test status
Simulation time 334617309163 ps
CPU time 406.99 seconds
Started Jun 26 06:36:34 PM PDT 24
Finished Jun 26 06:43:38 PM PDT 24
Peak memory 201832 kb
Host smart-0f619c01-41b6-41e7-adb8-f891264116b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817294899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2817294899
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.2096070782
Short name T241
Test name
Test status
Simulation time 364806399668 ps
CPU time 429.53 seconds
Started Jun 26 06:36:54 PM PDT 24
Finished Jun 26 06:44:29 PM PDT 24
Peak memory 201860 kb
Host smart-0f57794d-6ad4-4b19-bac0-52a8a4dedf6b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096070782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.2096070782
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.187569357
Short name T683
Test name
Test status
Simulation time 203415855054 ps
CPU time 234.29 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:40:45 PM PDT 24
Peak memory 201844 kb
Host smart-e5882ac8-6f1f-4df8-9f82-d606db911332
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187569357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
adc_ctrl_filters_wakeup_fixed.187569357
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.3650579538
Short name T212
Test name
Test status
Simulation time 145423727702 ps
CPU time 476.99 seconds
Started Jun 26 06:36:36 PM PDT 24
Finished Jun 26 06:44:51 PM PDT 24
Peak memory 202192 kb
Host smart-d0360507-cbd8-4bc0-8680-2560e71cf60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650579538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3650579538
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.2026487409
Short name T110
Test name
Test status
Simulation time 37979143257 ps
CPU time 86.91 seconds
Started Jun 26 06:36:36 PM PDT 24
Finished Jun 26 06:38:22 PM PDT 24
Peak memory 201664 kb
Host smart-374c2cee-4f54-41f9-b6bf-6a24b4e949cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026487409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2026487409
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.2261265301
Short name T386
Test name
Test status
Simulation time 4517946416 ps
CPU time 1.62 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:36:53 PM PDT 24
Peak memory 201672 kb
Host smart-eacec8ed-d1f6-4704-bce4-2ba5b66b193e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261265301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.2261265301
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.1160033964
Short name T677
Test name
Test status
Simulation time 5768443379 ps
CPU time 7.45 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:36:58 PM PDT 24
Peak memory 201692 kb
Host smart-a7b9a5ad-5e6f-43ff-9cd3-5a175d821da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160033964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1160033964
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.3054591645
Short name T194
Test name
Test status
Simulation time 208428308806 ps
CPU time 65.86 seconds
Started Jun 26 06:36:38 PM PDT 24
Finished Jun 26 06:38:03 PM PDT 24
Peak memory 201864 kb
Host smart-4b2a49c5-acc1-4396-8635-d83471aa5562
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054591645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.3054591645
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3610452688
Short name T36
Test name
Test status
Simulation time 143494478998 ps
CPU time 84.63 seconds
Started Jun 26 06:36:41 PM PDT 24
Finished Jun 26 06:38:28 PM PDT 24
Peak memory 210288 kb
Host smart-c15e1536-91a4-4085-a582-3f3c0f4ec715
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610452688 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.3610452688
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.3051142490
Short name T13
Test name
Test status
Simulation time 438962768 ps
CPU time 1.66 seconds
Started Jun 26 06:36:43 PM PDT 24
Finished Jun 26 06:37:09 PM PDT 24
Peak memory 201700 kb
Host smart-d485ee21-b27a-4530-a42c-1e0afd2dfac2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051142490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.3051142490
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.689915782
Short name T60
Test name
Test status
Simulation time 501051717931 ps
CPU time 219.27 seconds
Started Jun 26 06:36:44 PM PDT 24
Finished Jun 26 06:40:47 PM PDT 24
Peak memory 201116 kb
Host smart-cbc88e0b-fce2-4dcb-9aab-a003b3490a09
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689915782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gati
ng.689915782
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.314418278
Short name T795
Test name
Test status
Simulation time 486468417596 ps
CPU time 314.43 seconds
Started Jun 26 06:36:39 PM PDT 24
Finished Jun 26 06:42:14 PM PDT 24
Peak memory 201868 kb
Host smart-6c7abfa6-0497-46cc-a8e2-cbdbae78347d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314418278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.314418278
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3526616279
Short name T113
Test name
Test status
Simulation time 479832782832 ps
CPU time 289.43 seconds
Started Jun 26 06:36:39 PM PDT 24
Finished Jun 26 06:41:49 PM PDT 24
Peak memory 201844 kb
Host smart-18ebad16-acd2-448e-874f-dc52bf9cb556
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526616279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.3526616279
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.4282078679
Short name T529
Test name
Test status
Simulation time 159512531983 ps
CPU time 379.93 seconds
Started Jun 26 06:36:38 PM PDT 24
Finished Jun 26 06:43:17 PM PDT 24
Peak memory 201964 kb
Host smart-63f34eac-0003-45df-a8a6-503b0c48b6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282078679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.4282078679
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2832848937
Short name T574
Test name
Test status
Simulation time 488692912434 ps
CPU time 1041.32 seconds
Started Jun 26 06:36:41 PM PDT 24
Finished Jun 26 06:54:25 PM PDT 24
Peak memory 201668 kb
Host smart-97016572-94aa-4ff3-9d0b-81d936dd5146
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832848937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2832848937
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.3642922798
Short name T196
Test name
Test status
Simulation time 554869494299 ps
CPU time 86.82 seconds
Started Jun 26 06:36:47 PM PDT 24
Finished Jun 26 06:38:40 PM PDT 24
Peak memory 201836 kb
Host smart-aec28d67-46d8-47eb-a0cb-ddf65ac9e0cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642922798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.3642922798
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.1607655962
Short name T757
Test name
Test status
Simulation time 392392217711 ps
CPU time 881.3 seconds
Started Jun 26 06:36:44 PM PDT 24
Finished Jun 26 06:51:49 PM PDT 24
Peak memory 201872 kb
Host smart-400d373a-0c72-4105-b83d-a79fa1a90f0b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607655962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.1607655962
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.805173553
Short name T52
Test name
Test status
Simulation time 82601320491 ps
CPU time 319.57 seconds
Started Jun 26 06:36:43 PM PDT 24
Finished Jun 26 06:42:25 PM PDT 24
Peak memory 202100 kb
Host smart-0e75c3a2-3459-468c-83af-c27d9fdaf67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805173553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.805173553
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.4029292849
Short name T602
Test name
Test status
Simulation time 29126290237 ps
CPU time 17.15 seconds
Started Jun 26 06:36:44 PM PDT 24
Finished Jun 26 06:37:25 PM PDT 24
Peak memory 201572 kb
Host smart-baa1ff84-ca6d-4a10-b6d4-15e03110ee60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029292849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.4029292849
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.3779034529
Short name T704
Test name
Test status
Simulation time 4578643104 ps
CPU time 10.36 seconds
Started Jun 26 06:36:42 PM PDT 24
Finished Jun 26 06:37:16 PM PDT 24
Peak memory 201684 kb
Host smart-1af12f0b-e2f6-49dd-9022-93c84afb1e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779034529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3779034529
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.772957437
Short name T487
Test name
Test status
Simulation time 5926831596 ps
CPU time 13.45 seconds
Started Jun 26 06:36:52 PM PDT 24
Finished Jun 26 06:37:31 PM PDT 24
Peak memory 201692 kb
Host smart-2edcd286-4c97-4fab-910f-4fbd64c5daa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772957437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.772957437
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.1860208281
Short name T550
Test name
Test status
Simulation time 386075576918 ps
CPU time 247.12 seconds
Started Jun 26 06:36:42 PM PDT 24
Finished Jun 26 06:41:13 PM PDT 24
Peak memory 201924 kb
Host smart-a7491ba7-013a-4551-b5f4-6d282fb87bc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860208281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.1860208281
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2379163106
Short name T35
Test name
Test status
Simulation time 358606978168 ps
CPU time 145.74 seconds
Started Jun 26 06:36:43 PM PDT 24
Finished Jun 26 06:39:33 PM PDT 24
Peak memory 210276 kb
Host smart-84353f1a-a1e1-4319-ab6a-bd7f99910d48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379163106 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.2379163106
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.36811045
Short name T535
Test name
Test status
Simulation time 362279785 ps
CPU time 1.36 seconds
Started Jun 26 06:36:34 PM PDT 24
Finished Jun 26 06:36:48 PM PDT 24
Peak memory 201628 kb
Host smart-1c044a9d-456f-41b7-8a10-56868f99aea0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36811045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.36811045
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.133220377
Short name T319
Test name
Test status
Simulation time 539524682871 ps
CPU time 132.83 seconds
Started Jun 26 06:36:44 PM PDT 24
Finished Jun 26 06:39:20 PM PDT 24
Peak memory 201988 kb
Host smart-eef8484a-1827-4e90-a24f-7f225660f58b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133220377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gati
ng.133220377
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.207096535
Short name T268
Test name
Test status
Simulation time 354636519714 ps
CPU time 853.76 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:51:05 PM PDT 24
Peak memory 201856 kb
Host smart-adfd76ee-e460-45f4-9e20-d2869ca39ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207096535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.207096535
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.2013164314
Short name T690
Test name
Test status
Simulation time 169914514463 ps
CPU time 392.08 seconds
Started Jun 26 06:36:45 PM PDT 24
Finished Jun 26 06:43:41 PM PDT 24
Peak memory 201892 kb
Host smart-862dd541-29ad-4af6-a21e-2dd58704c880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013164314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2013164314
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2252631247
Short name T461
Test name
Test status
Simulation time 329708216158 ps
CPU time 331.72 seconds
Started Jun 26 06:36:47 PM PDT 24
Finished Jun 26 06:42:43 PM PDT 24
Peak memory 201772 kb
Host smart-c525a093-94ec-4700-849f-20642b6bd1af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252631247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.2252631247
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1264494930
Short name T151
Test name
Test status
Simulation time 481661419049 ps
CPU time 253.52 seconds
Started Jun 26 06:36:44 PM PDT 24
Finished Jun 26 06:41:22 PM PDT 24
Peak memory 201896 kb
Host smart-9882ab0a-e3ba-4169-b117-80ac3b578b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264494930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1264494930
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.2518752902
Short name T562
Test name
Test status
Simulation time 328101344451 ps
CPU time 733.57 seconds
Started Jun 26 06:36:43 PM PDT 24
Finished Jun 26 06:49:21 PM PDT 24
Peak memory 201852 kb
Host smart-037d9f18-4827-4dd4-95ec-ba8511e5f94b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518752902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.2518752902
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.3726449542
Short name T644
Test name
Test status
Simulation time 506504476193 ps
CPU time 1166.3 seconds
Started Jun 26 06:36:58 PM PDT 24
Finished Jun 26 06:56:50 PM PDT 24
Peak memory 201896 kb
Host smart-a9048ade-a968-4cca-a25f-fb400c43ae81
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726449542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.3726449542
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.3230960670
Short name T404
Test name
Test status
Simulation time 380434163716 ps
CPU time 203.17 seconds
Started Jun 26 06:36:48 PM PDT 24
Finished Jun 26 06:40:37 PM PDT 24
Peak memory 201816 kb
Host smart-da111cc6-c793-445e-b387-f5fafb9bdaab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230960670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.3230960670
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.792313203
Short name T632
Test name
Test status
Simulation time 132914236175 ps
CPU time 701.33 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:48:35 PM PDT 24
Peak memory 202240 kb
Host smart-7d8d6e70-82e9-4ecb-92d3-514b749b2791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792313203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.792313203
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.567888501
Short name T464
Test name
Test status
Simulation time 29684961511 ps
CPU time 17.77 seconds
Started Jun 26 06:36:35 PM PDT 24
Finished Jun 26 06:37:09 PM PDT 24
Peak memory 201692 kb
Host smart-8a880ccf-9dad-417d-adc4-9ee194f34d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567888501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.567888501
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.2179917821
Short name T371
Test name
Test status
Simulation time 4499269540 ps
CPU time 3.37 seconds
Started Jun 26 06:36:33 PM PDT 24
Finished Jun 26 06:36:50 PM PDT 24
Peak memory 201644 kb
Host smart-b61b99e6-51ff-484f-9b37-e33bd82a43c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179917821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2179917821
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3639666727
Short name T364
Test name
Test status
Simulation time 6139430130 ps
CPU time 15.1 seconds
Started Jun 26 06:36:44 PM PDT 24
Finished Jun 26 06:37:23 PM PDT 24
Peak memory 201688 kb
Host smart-1ed18992-53e9-4226-b7d6-edbf488f8ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639666727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3639666727
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.3592369291
Short name T115
Test name
Test status
Simulation time 548909080935 ps
CPU time 1190.79 seconds
Started Jun 26 06:36:47 PM PDT 24
Finished Jun 26 06:57:04 PM PDT 24
Peak memory 201828 kb
Host smart-83ed0049-7cd8-4f3b-ae81-eb9db681c924
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592369291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.3592369291
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.1111684348
Short name T498
Test name
Test status
Simulation time 344218248 ps
CPU time 1.34 seconds
Started Jun 26 06:30:18 PM PDT 24
Finished Jun 26 06:30:23 PM PDT 24
Peak memory 201628 kb
Host smart-384376e2-bfcc-44af-9e18-3e8e1770b77b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111684348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1111684348
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3530215383
Short name T152
Test name
Test status
Simulation time 476251062655 ps
CPU time 647.41 seconds
Started Jun 26 06:30:19 PM PDT 24
Finished Jun 26 06:41:10 PM PDT 24
Peak memory 201928 kb
Host smart-4512a8e4-9e3d-44c5-94a0-166caf3922ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530215383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3530215383
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2597430810
Short name T713
Test name
Test status
Simulation time 318270303553 ps
CPU time 401.94 seconds
Started Jun 26 06:30:05 PM PDT 24
Finished Jun 26 06:36:50 PM PDT 24
Peak memory 201844 kb
Host smart-966fa2ed-24c7-4fa7-9a50-415e428cf59e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597430810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2597430810
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.626408361
Short name T689
Test name
Test status
Simulation time 164730226627 ps
CPU time 90.94 seconds
Started Jun 26 06:30:10 PM PDT 24
Finished Jun 26 06:31:42 PM PDT 24
Peak memory 201816 kb
Host smart-287d35da-44ef-4efd-b2a3-f07e3a90bf19
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=626408361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.626408361
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1229431460
Short name T327
Test name
Test status
Simulation time 397134067670 ps
CPU time 793.43 seconds
Started Jun 26 06:30:15 PM PDT 24
Finished Jun 26 06:43:31 PM PDT 24
Peak memory 201968 kb
Host smart-3b4e77ea-b5cf-4a81-9a69-423e5a30feb5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229431460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1229431460
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.7709640
Short name T708
Test name
Test status
Simulation time 197565952467 ps
CPU time 107.04 seconds
Started Jun 26 06:30:17 PM PDT 24
Finished Jun 26 06:32:08 PM PDT 24
Peak memory 201868 kb
Host smart-1a3e74ef-d2fd-4da1-be1b-3862d5c36ee5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7709640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc
_ctrl_filters_wakeup_fixed.7709640
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.1547231818
Short name T344
Test name
Test status
Simulation time 89182220025 ps
CPU time 482.39 seconds
Started Jun 26 06:30:14 PM PDT 24
Finished Jun 26 06:38:18 PM PDT 24
Peak memory 202208 kb
Host smart-4592939f-3c44-4442-973f-bdf0f35f9b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547231818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1547231818
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.956731001
Short name T681
Test name
Test status
Simulation time 38174560025 ps
CPU time 92.48 seconds
Started Jun 26 06:30:02 PM PDT 24
Finished Jun 26 06:31:37 PM PDT 24
Peak memory 201660 kb
Host smart-2cd760a9-fb6d-41ac-8243-6689f471b34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956731001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.956731001
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2109097625
Short name T589
Test name
Test status
Simulation time 3866624727 ps
CPU time 3.25 seconds
Started Jun 26 06:30:03 PM PDT 24
Finished Jun 26 06:30:09 PM PDT 24
Peak memory 201692 kb
Host smart-5e0d976b-c7eb-44f0-98e3-9b762d656d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109097625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2109097625
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.314551422
Short name T373
Test name
Test status
Simulation time 5691516623 ps
CPU time 14.56 seconds
Started Jun 26 06:30:02 PM PDT 24
Finished Jun 26 06:30:18 PM PDT 24
Peak memory 201688 kb
Host smart-143488fe-2675-4fe0-a10f-cc84dc2a41ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314551422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.314551422
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1669014499
Short name T42
Test name
Test status
Simulation time 91870669838 ps
CPU time 184.52 seconds
Started Jun 26 06:30:11 PM PDT 24
Finished Jun 26 06:33:17 PM PDT 24
Peak memory 202028 kb
Host smart-4c04031c-b9f7-4a8b-a245-aa7391dbf9ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669014499 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.1669014499
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.1852828966
Short name T363
Test name
Test status
Simulation time 519148746 ps
CPU time 1.52 seconds
Started Jun 26 06:30:17 PM PDT 24
Finished Jun 26 06:30:22 PM PDT 24
Peak memory 201628 kb
Host smart-3b22d948-9111-43fd-b1db-75ce690cff8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852828966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.1852828966
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1159224193
Short name T572
Test name
Test status
Simulation time 160868128216 ps
CPU time 261.77 seconds
Started Jun 26 06:30:04 PM PDT 24
Finished Jun 26 06:34:28 PM PDT 24
Peak memory 201844 kb
Host smart-d5faf6f8-62b1-4be5-a425-d3f6bcde9b68
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159224193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1159224193
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3461737061
Short name T293
Test name
Test status
Simulation time 181880545506 ps
CPU time 199.7 seconds
Started Jun 26 06:30:11 PM PDT 24
Finished Jun 26 06:33:33 PM PDT 24
Peak memory 201876 kb
Host smart-e9dff57c-b031-462b-b87a-eb85cacaca4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461737061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3461737061
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1574316676
Short name T298
Test name
Test status
Simulation time 331468605768 ps
CPU time 193.06 seconds
Started Jun 26 06:30:09 PM PDT 24
Finished Jun 26 06:33:24 PM PDT 24
Peak memory 201840 kb
Host smart-887e9953-ef29-4d4d-a23e-69e00d4f4991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574316676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1574316676
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.846269686
Short name T706
Test name
Test status
Simulation time 163859102815 ps
CPU time 101.01 seconds
Started Jun 26 06:30:10 PM PDT 24
Finished Jun 26 06:31:52 PM PDT 24
Peak memory 201832 kb
Host smart-9939febb-3811-4380-b544-032f2f0f0e36
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=846269686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt
_fixed.846269686
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.2092476665
Short name T787
Test name
Test status
Simulation time 485147266012 ps
CPU time 399.69 seconds
Started Jun 26 06:30:04 PM PDT 24
Finished Jun 26 06:36:46 PM PDT 24
Peak memory 201872 kb
Host smart-4616ac09-f034-4748-87bc-7e5af1dac05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092476665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.2092476665
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.95981762
Short name T424
Test name
Test status
Simulation time 170037624051 ps
CPU time 64.83 seconds
Started Jun 26 06:30:05 PM PDT 24
Finished Jun 26 06:31:12 PM PDT 24
Peak memory 201932 kb
Host smart-cd5b11dd-d062-4abb-b8ac-3d17270166d7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=95981762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed.95981762
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1688577317
Short name T697
Test name
Test status
Simulation time 204571942386 ps
CPU time 119.6 seconds
Started Jun 26 06:30:18 PM PDT 24
Finished Jun 26 06:32:21 PM PDT 24
Peak memory 201884 kb
Host smart-9bc6f8d3-1064-4762-98ee-f0b621d3e06a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688577317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.1688577317
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.409248611
Short name T647
Test name
Test status
Simulation time 46962728961 ps
CPU time 110.65 seconds
Started Jun 26 06:30:06 PM PDT 24
Finished Jun 26 06:31:59 PM PDT 24
Peak memory 201632 kb
Host smart-d093759c-04f3-4df3-bb7f-94cc54d2989d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409248611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.409248611
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2156264478
Short name T623
Test name
Test status
Simulation time 4733073045 ps
CPU time 1.71 seconds
Started Jun 26 06:30:06 PM PDT 24
Finished Jun 26 06:30:10 PM PDT 24
Peak memory 201692 kb
Host smart-713185a0-ce83-4d19-aa1e-1f8a91db98cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156264478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2156264478
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.1653023747
Short name T490
Test name
Test status
Simulation time 5551242545 ps
CPU time 3.97 seconds
Started Jun 26 06:30:16 PM PDT 24
Finished Jun 26 06:30:23 PM PDT 24
Peak memory 201580 kb
Host smart-4c229371-058c-4935-9b72-e41e979c01f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653023747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.1653023747
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3186227744
Short name T654
Test name
Test status
Simulation time 167555525296 ps
CPU time 381.27 seconds
Started Jun 26 06:30:19 PM PDT 24
Finished Jun 26 06:36:44 PM PDT 24
Peak memory 201856 kb
Host smart-2a2023e8-79f5-4956-bf59-fc90858a1f7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186227744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3186227744
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3945056821
Short name T122
Test name
Test status
Simulation time 138120184621 ps
CPU time 129.27 seconds
Started Jun 26 06:30:13 PM PDT 24
Finished Jun 26 06:32:24 PM PDT 24
Peak memory 217884 kb
Host smart-c904f8e5-3587-4eb9-b15a-4772ba1fddb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945056821 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3945056821
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.2264215238
Short name T733
Test name
Test status
Simulation time 290912683 ps
CPU time 1.42 seconds
Started Jun 26 06:30:03 PM PDT 24
Finished Jun 26 06:30:06 PM PDT 24
Peak memory 201636 kb
Host smart-faaf6c9b-122a-42ab-8d82-fe7c5c53ce05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264215238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.2264215238
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1680142883
Short name T193
Test name
Test status
Simulation time 339054700959 ps
CPU time 111.42 seconds
Started Jun 26 06:30:17 PM PDT 24
Finished Jun 26 06:32:12 PM PDT 24
Peak memory 201948 kb
Host smart-259b3696-884f-4ec1-a773-a600e3621f9d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680142883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1680142883
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.1664931256
Short name T521
Test name
Test status
Simulation time 225544068892 ps
CPU time 134.76 seconds
Started Jun 26 06:30:19 PM PDT 24
Finished Jun 26 06:32:53 PM PDT 24
Peak memory 201908 kb
Host smart-de60ab20-3d07-4128-b223-5a30fa943189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664931256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.1664931256
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.2227924609
Short name T325
Test name
Test status
Simulation time 328791441064 ps
CPU time 727.34 seconds
Started Jun 26 06:30:16 PM PDT 24
Finished Jun 26 06:42:26 PM PDT 24
Peak memory 202096 kb
Host smart-f5020c4b-b805-4312-a240-96415d3d4603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227924609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.2227924609
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2254600794
Short name T413
Test name
Test status
Simulation time 502783390249 ps
CPU time 293.68 seconds
Started Jun 26 06:30:07 PM PDT 24
Finished Jun 26 06:35:03 PM PDT 24
Peak memory 201832 kb
Host smart-ebc03644-022e-4f94-ad7a-946cf73f9188
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254600794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.2254600794
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.2272057889
Short name T725
Test name
Test status
Simulation time 163025434865 ps
CPU time 383.39 seconds
Started Jun 26 06:30:17 PM PDT 24
Finished Jun 26 06:36:44 PM PDT 24
Peak memory 201976 kb
Host smart-5574f9e9-bb96-4469-8b81-c9e593587055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272057889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.2272057889
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.541393875
Short name T721
Test name
Test status
Simulation time 326587537380 ps
CPU time 97.44 seconds
Started Jun 26 06:30:02 PM PDT 24
Finished Jun 26 06:31:42 PM PDT 24
Peak memory 201864 kb
Host smart-f5743b5d-73e4-46de-be2d-577d183e3669
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=541393875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.541393875
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.4098935405
Short name T746
Test name
Test status
Simulation time 178057052660 ps
CPU time 39.72 seconds
Started Jun 26 06:30:14 PM PDT 24
Finished Jun 26 06:30:56 PM PDT 24
Peak memory 201896 kb
Host smart-e56588fe-3296-4cc6-85cf-b1f8ed2ec8df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098935405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.4098935405
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1680438928
Short name T517
Test name
Test status
Simulation time 383851220039 ps
CPU time 212.73 seconds
Started Jun 26 06:30:21 PM PDT 24
Finished Jun 26 06:33:57 PM PDT 24
Peak memory 201844 kb
Host smart-e56e99d8-4997-406a-bd84-0ef2afcb0cdc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680438928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1680438928
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3767822886
Short name T346
Test name
Test status
Simulation time 103173166364 ps
CPU time 556.45 seconds
Started Jun 26 06:30:04 PM PDT 24
Finished Jun 26 06:39:22 PM PDT 24
Peak memory 202232 kb
Host smart-459d9253-838d-4766-8f3c-570b0f007b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767822886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3767822886
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.1940650240
Short name T755
Test name
Test status
Simulation time 34448049767 ps
CPU time 75.29 seconds
Started Jun 26 06:30:03 PM PDT 24
Finished Jun 26 06:31:20 PM PDT 24
Peak memory 201692 kb
Host smart-0809d249-5dc7-4f8d-92d5-644d3d02c3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940650240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.1940650240
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.381608552
Short name T670
Test name
Test status
Simulation time 4773367291 ps
CPU time 11.91 seconds
Started Jun 26 06:30:04 PM PDT 24
Finished Jun 26 06:30:18 PM PDT 24
Peak memory 201700 kb
Host smart-f5358392-eb0c-4046-a338-4954f600b8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381608552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.381608552
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.1039381903
Short name T515
Test name
Test status
Simulation time 5967610371 ps
CPU time 7.36 seconds
Started Jun 26 06:30:05 PM PDT 24
Finished Jun 26 06:30:15 PM PDT 24
Peak memory 201676 kb
Host smart-f6e2a963-8e69-46b0-97b1-edae3304d7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039381903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1039381903
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.295231702
Short name T546
Test name
Test status
Simulation time 230126228787 ps
CPU time 350.74 seconds
Started Jun 26 06:30:17 PM PDT 24
Finished Jun 26 06:36:11 PM PDT 24
Peak memory 218508 kb
Host smart-d741cded-6869-4cb7-b8f9-a5902df6cd01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295231702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.295231702
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2113861566
Short name T39
Test name
Test status
Simulation time 17903656707 ps
CPU time 36.39 seconds
Started Jun 26 06:30:17 PM PDT 24
Finished Jun 26 06:30:57 PM PDT 24
Peak memory 210164 kb
Host smart-7fba7280-7c3a-48f2-881e-19d3f56552e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113861566 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.2113861566
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2603692515
Short name T626
Test name
Test status
Simulation time 486792879 ps
CPU time 0.89 seconds
Started Jun 26 06:30:16 PM PDT 24
Finished Jun 26 06:30:19 PM PDT 24
Peak memory 201568 kb
Host smart-20ad1f59-c3c1-4470-9eee-8addce598b5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603692515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2603692515
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1563137342
Short name T242
Test name
Test status
Simulation time 529255782539 ps
CPU time 516.37 seconds
Started Jun 26 06:30:18 PM PDT 24
Finished Jun 26 06:38:58 PM PDT 24
Peak memory 201868 kb
Host smart-58895f7d-0229-48d9-9702-45007d3cc50c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563137342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1563137342
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.579231903
Short name T227
Test name
Test status
Simulation time 177961529690 ps
CPU time 389.46 seconds
Started Jun 26 06:30:17 PM PDT 24
Finished Jun 26 06:36:49 PM PDT 24
Peak memory 201976 kb
Host smart-1ce5bc30-eb96-4a9e-8fb8-f9a075459f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579231903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.579231903
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.4266781790
Short name T221
Test name
Test status
Simulation time 322626029710 ps
CPU time 370.13 seconds
Started Jun 26 06:30:19 PM PDT 24
Finished Jun 26 06:36:33 PM PDT 24
Peak memory 201912 kb
Host smart-c26f52a4-0d29-4a0e-a9ca-677e7b8d6e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266781790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.4266781790
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.3970628000
Short name T117
Test name
Test status
Simulation time 161562770170 ps
CPU time 393.86 seconds
Started Jun 26 06:30:08 PM PDT 24
Finished Jun 26 06:36:44 PM PDT 24
Peak memory 201872 kb
Host smart-72808acb-b3bc-4fca-a497-f77367af3839
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970628000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.3970628000
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.784267309
Short name T328
Test name
Test status
Simulation time 496044235240 ps
CPU time 536.84 seconds
Started Jun 26 06:30:10 PM PDT 24
Finished Jun 26 06:39:09 PM PDT 24
Peak memory 201940 kb
Host smart-310f1ff5-16a6-4806-9ae3-7bce8ab5e6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784267309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.784267309
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.1043186529
Short name T585
Test name
Test status
Simulation time 496916343274 ps
CPU time 215.07 seconds
Started Jun 26 06:30:05 PM PDT 24
Finished Jun 26 06:33:43 PM PDT 24
Peak memory 201868 kb
Host smart-9629678f-7ef2-4ff7-a175-e6ce93c6361e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043186529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.1043186529
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1691315251
Short name T695
Test name
Test status
Simulation time 407473378359 ps
CPU time 844.91 seconds
Started Jun 26 06:30:06 PM PDT 24
Finished Jun 26 06:44:13 PM PDT 24
Peak memory 201916 kb
Host smart-5085e88f-c41a-4737-9044-c258bac3c031
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691315251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.1691315251
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.4100601890
Short name T709
Test name
Test status
Simulation time 27768530696 ps
CPU time 61.62 seconds
Started Jun 26 06:30:10 PM PDT 24
Finished Jun 26 06:31:13 PM PDT 24
Peak memory 201644 kb
Host smart-7af511bb-7be3-405d-87c5-4cd0ef050b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100601890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.4100601890
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.3955868238
Short name T791
Test name
Test status
Simulation time 4045765911 ps
CPU time 10.12 seconds
Started Jun 26 06:30:07 PM PDT 24
Finished Jun 26 06:30:19 PM PDT 24
Peak memory 201700 kb
Host smart-0483045e-017c-497d-9290-3476140d89aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955868238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.3955868238
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.1342887039
Short name T427
Test name
Test status
Simulation time 6096140038 ps
CPU time 14.57 seconds
Started Jun 26 06:30:18 PM PDT 24
Finished Jun 26 06:30:36 PM PDT 24
Peak memory 201684 kb
Host smart-b022267f-3515-4215-acef-50673a913e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342887039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1342887039
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1360792735
Short name T513
Test name
Test status
Simulation time 179679849138 ps
CPU time 372.88 seconds
Started Jun 26 06:30:19 PM PDT 24
Finished Jun 26 06:36:36 PM PDT 24
Peak memory 201932 kb
Host smart-8293f40b-03e3-475a-97b0-6333537b9c25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360792735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1360792735
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.722637141
Short name T104
Test name
Test status
Simulation time 105528414099 ps
CPU time 150.55 seconds
Started Jun 26 06:30:20 PM PDT 24
Finished Jun 26 06:32:55 PM PDT 24
Peak memory 210216 kb
Host smart-761256f7-65a9-4b07-821a-5cafe286e77a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722637141 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.722637141
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.699860395
Short name T467
Test name
Test status
Simulation time 475109358 ps
CPU time 1.74 seconds
Started Jun 26 06:30:15 PM PDT 24
Finished Jun 26 06:30:18 PM PDT 24
Peak memory 201632 kb
Host smart-f373ef35-f48c-40ae-8c74-897719ad2015
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699860395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.699860395
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.405072031
Short name T102
Test name
Test status
Simulation time 197992421911 ps
CPU time 442.45 seconds
Started Jun 26 06:30:16 PM PDT 24
Finished Jun 26 06:37:42 PM PDT 24
Peak memory 201900 kb
Host smart-95f01ec5-557e-4ee4-ae2c-01449316fda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405072031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.405072031
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1647325521
Short name T492
Test name
Test status
Simulation time 163684896165 ps
CPU time 189.15 seconds
Started Jun 26 06:30:13 PM PDT 24
Finished Jun 26 06:33:24 PM PDT 24
Peak memory 201844 kb
Host smart-7df39066-4544-4cc0-94d7-97c22154a8fb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647325521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.1647325521
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.4020696301
Short name T271
Test name
Test status
Simulation time 488896739146 ps
CPU time 258.39 seconds
Started Jun 26 06:30:17 PM PDT 24
Finished Jun 26 06:34:39 PM PDT 24
Peak memory 201840 kb
Host smart-61e35dde-8f97-42b0-945c-5d19416f4803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020696301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.4020696301
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.424898111
Short name T759
Test name
Test status
Simulation time 159284161818 ps
CPU time 190.74 seconds
Started Jun 26 06:30:19 PM PDT 24
Finished Jun 26 06:33:34 PM PDT 24
Peak memory 201860 kb
Host smart-b06b7351-91ec-4b69-834f-f9d0f73b36ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=424898111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.424898111
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.2815082983
Short name T748
Test name
Test status
Simulation time 186581709487 ps
CPU time 94.5 seconds
Started Jun 26 06:30:20 PM PDT 24
Finished Jun 26 06:31:59 PM PDT 24
Peak memory 201896 kb
Host smart-c1c5cc1e-f3bd-4d83-9d48-b59d701f84c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815082983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.2815082983
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1436600720
Short name T586
Test name
Test status
Simulation time 204939375772 ps
CPU time 470.49 seconds
Started Jun 26 06:30:22 PM PDT 24
Finished Jun 26 06:38:16 PM PDT 24
Peak memory 201932 kb
Host smart-f69c7f7d-44c1-400b-b030-9fa22a0e7758
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436600720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.1436600720
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.2211232616
Short name T340
Test name
Test status
Simulation time 116589141067 ps
CPU time 602.76 seconds
Started Jun 26 06:30:15 PM PDT 24
Finished Jun 26 06:40:19 PM PDT 24
Peak memory 202196 kb
Host smart-adcb4508-6071-4813-ba93-b7d5d5521469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211232616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.2211232616
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.1407666610
Short name T522
Test name
Test status
Simulation time 23946805426 ps
CPU time 54.86 seconds
Started Jun 26 06:30:19 PM PDT 24
Finished Jun 26 06:31:18 PM PDT 24
Peak memory 201572 kb
Host smart-4710d6c4-b3e6-4446-b50d-4d56cc22aad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407666610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.1407666610
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1302339228
Short name T446
Test name
Test status
Simulation time 4800550084 ps
CPU time 3.83 seconds
Started Jun 26 06:30:12 PM PDT 24
Finished Jun 26 06:30:17 PM PDT 24
Peak memory 201636 kb
Host smart-e75484cc-e7ae-4119-9b42-d436b32dba89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302339228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1302339228
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.605846017
Short name T497
Test name
Test status
Simulation time 6000557181 ps
CPU time 6.68 seconds
Started Jun 26 06:30:04 PM PDT 24
Finished Jun 26 06:30:13 PM PDT 24
Peak memory 201660 kb
Host smart-47694886-b8b7-4bbe-8bad-bbece8f940bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605846017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.605846017
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2850149452
Short name T493
Test name
Test status
Simulation time 171024843350 ps
CPU time 385.92 seconds
Started Jun 26 06:30:37 PM PDT 24
Finished Jun 26 06:37:06 PM PDT 24
Peak memory 201864 kb
Host smart-93dcbf75-175e-412f-9e58-c9dd1cf8cf92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850149452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2850149452
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1071216511
Short name T105
Test name
Test status
Simulation time 51909750180 ps
CPU time 109.76 seconds
Started Jun 26 06:30:17 PM PDT 24
Finished Jun 26 06:32:09 PM PDT 24
Peak memory 210196 kb
Host smart-cc9abce2-a227-4b19-84e3-e7d81c360c34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071216511 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.1071216511
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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