Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6696	1			T1	20		T6	20		T15	4
testmodes[AdcCtrlTestmodeNormal]	5490	1			T2	3		T4	2		T5	2
testmodes[AdcCtrlTestmodeLowpower]	5726	1			T3	15		T9	3		T10	16
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3559	1			T1	19		T6	19		T15	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1759	1			T15	2		T13	1		T14	9
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1274	1			T29	14		T40	1		T46	24
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1696	1			T15	2		T13	1		T14	10
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1998	1			T2	2		T4	1		T5	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1462	1			T13	2		T29	9		T46	11
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1324	1			T29	11		T40	1		T46	23
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1397	1			T13	2		T29	12		T40	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2743	1			T3	14		T9	2		T10	15