Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26190

1

T1

20

T2

24

T3

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22554

1

T1

20

T2

24

T3

15

auto[ADC_CTRL_FILTER_COND_OUT]

3636

1

T4

9

T5

2

T8

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20211

1

T1

20

T3

15

T4

14

auto[1]

5979

1

T2

24

T5

1

T7

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22215

1

T1

20

T2

3

T3

15

auto[1]

3975

1

T2

21

T4

12

T7

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	89	1			T146	11		T228	16		T229	5
values[1]	802	1			T4	5		T44	13		T110	14
values[2]	719	1			T9	10		T40	10		T146	5
values[3]	664	1			T40	11		T145	16		T43	17
values[4]	2945	1			T2	24		T7	15		T12	14
values[5]	783	1			T4	9		T9	26		T13	26
values[6]	654	1			T11	1		T157	1		T16	10
values[7]	813	1			T5	2		T14	3		T42	1
values[8]	620	1			T145	11		T147	10		T34	6
values[9]	1131	1			T8	2		T42	1		T43	10
minimum	16970	1			T1	20		T3	15		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1063	1			T4	5		T9	10		T44	13
values[1]	659	1			T40	10		T145	16		T43	17
values[2]	645	1			T40	11		T230	14		T114	5
values[3]	3027	1			T2	24		T4	9		T7	15
values[4]	749	1			T9	26		T11	1		T16	10
values[5]	572	1			T5	1		T157	1		T83	1
values[6]	847	1			T5	1		T42	1		T147	15
values[7]	637	1			T8	1		T14	3		T145	11
values[8]	819	1			T8	1		T42	1		T43	10
values[9]	166	1			T44	25		T114	12		T231	5
minimum	17006	1			T1	20		T3	15		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21887

1

T1

20

T2

24

T3

15

auto[1]

4303

1

T9

33

T12

12

T13

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	361	1			T4	1		T9	10		T44	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T146	7		T110	14		T232	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T145	1		T108	12		T143	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T40	10		T43	15		T146	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T40	8		T142	20		T233	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T230	1		T114	1		T174	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1583	1			T2	3		T7	2		T12	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T4	1		T147	13		T112	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T11	1		T144	8		T234	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T9	26		T16	7		T110	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T83	1		T167	12		T37	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	1		T157	1		T174	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T42	1		T147	15		T142	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	1		T112	1		T88	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T34	4		T35	8		T17	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T8	1		T14	2		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T42	1		T87	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T8	1		T43	10		T86	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T114	1		T235	12		T236	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T44	12		T231	5		T237	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16870	1			T1	20		T3	15		T6	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T4	4		T44	2		T150	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T146	4		T177	9		T238	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T145	15		T143	11		T163	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T43	2		T159	14		T239	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T40	3		T142	14		T233	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T230	13		T114	4		T152	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	927	1			T2	21		T7	13		T13	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T4	8		T112	12		T167	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T144	14		T209	8		T39	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T16	3		T149	4		T143	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T37	8		T240	18		T241	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T152	12		T164	15		T241	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T142	13		T213	8		T144	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T112	10		T150	17		T189	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T34	2		T35	1		T242	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T14	1		T145	10		T146	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T142	1		T150	8		T93	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T86	13		T243	12		T166	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T114	11		T235	10		T236	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T44	13		T181	14		T244	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	2		T14	1		T33	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T228	1		T229	1		T245	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T146	7		T246	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T4	1		T44	11		T112	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T110	14		T232	1		T208	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T9	10		T108	25		T143	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T40	10		T146	5		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T40	8		T145	1		T142	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T43	15		T112	1		T114	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1622	1			T2	3		T7	2		T12	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T230	1		T167	12		T163	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T13	15		T234	1		T176	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	350	1			T4	1		T9	26		T147	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	1		T83	1		T144	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T157	1		T16	7		T110	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T42	1		T147	15		T35	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	2		T14	2		T234	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T34	4		T175	1		T242	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T145	1		T147	10		T112	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T42	1		T114	1		T87	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T8	2		T43	10		T33	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16853	1			T1	20		T3	15		T6	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T228	15		T229	4		T245	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T146	4		T246	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T4	4		T44	2		T112	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T177	9		T97	13		T247	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T143	11		T163	2		T164	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T159	14		T238	6		T243	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T40	3		T145	15		T142	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T43	2		T112	12		T114	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	908	1			T2	21		T7	13		T30	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T230	13		T167	10		T163	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T13	11		T177	4		T37	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T4	8		T149	4		T143	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T144	14		T241	1		T239	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T16	3		T164	15		T241	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T35	1		T142	13		T213	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T14	1		T189	5		T152	35
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T34	2		T242	3		T58	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T145	10		T112	10		T150	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T114	11		T142	1		T150	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T44	13		T146	8		T86	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	2		T14	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	351	1			T4	5		T9	1		T44	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T146	5		T110	1		T232	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T145	16		T108	1		T143	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T40	1		T43	3		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T40	4		T142	15		T233	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T230	14		T114	5		T174	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T2	24		T7	15		T12	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T4	9		T147	1		T112	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T11	1		T144	15		T234	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T9	2		T16	7		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T83	1		T167	1		T37	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	1		T157	1		T174	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T42	1		T147	1		T142	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T5	1		T112	11		T88	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T34	4		T35	6		T17	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T8	1		T14	3		T145	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T42	1		T87	1		T142	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T8	1		T43	1		T86	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T114	12		T235	11		T236	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T44	14		T231	1		T237	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16992	1			T1	20		T3	15		T6	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T9	9		T44	10		T108	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T146	6		T110	13		T177	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T108	11		T143	9		T231	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T40	9		T43	14		T146	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T40	7		T142	19		T233	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T174	11		T152	7		T162	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1247	1			T12	12		T13	7		T41	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T147	12		T167	11		T163	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T144	7		T220	2		T92	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T9	24		T16	3		T110	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T167	11		T37	3		T248	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T174	14		T152	9		T164	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T147	14		T142	6		T213	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T150	16		T189	13		T152	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T34	2		T35	3		T105	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T33	1		T146	12		T147	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T150	12		T249	8		T93	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T43	9		T250	11		T243	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T235	11		T236	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T44	11		T231	4		T181	25
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T245	14		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T228	16		T229	5		T245	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T146	5		T246	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T4	5		T44	3		T112	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T110	1		T232	1		T208	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T9	1		T108	2		T143	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T40	1		T146	1		T159	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T40	4		T145	16		T142	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T43	3		T112	13		T114	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T2	24		T7	15		T12	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T230	14		T167	11		T163	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T13	19		T234	1		T176	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T4	9		T9	2		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T11	1		T83	1		T144	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T157	1		T16	7		T110	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T42	1		T147	1		T35	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	2		T14	3		T234	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T34	4		T175	1		T242	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T145	11		T147	1		T112	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T42	1		T114	12		T87	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T8	2		T43	1		T33	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16970	1			T1	20		T3	15		T6	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T245	14		T251	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T146	6		T246	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T44	10		T150	5		T189	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T110	13		T177	10		T97	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T9	9		T108	23		T143	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T40	9		T146	4		T148	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T40	7		T142	19		T233	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T43	14		T174	11		T152	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1288	1			T12	12		T41	7		T160	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T167	11		T163	14		T250	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T13	7		T176	10		T177	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T9	24		T147	12		T143	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T144	7		T167	11		T220	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T16	3		T110	3		T174	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T147	14		T35	3		T142	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T189	13		T152	28		T162	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T34	2		T58	1		T105	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T147	9		T150	16		T189	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T150	12		T249	8		T235	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T43	9		T33	1		T44	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21887

1

T1

20

T2

24

T3

15

auto[1]

auto[0]

4303

1

T9

33

T12

12

T13

7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26190

1

T1

20

T2

24

T3

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20466

1

T1

20

T3

15

T4

14

auto[ADC_CTRL_FILTER_COND_OUT]

5724

1

T2

24

T5

1

T7

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20109

1

T1

20

T3

15

T4

14

auto[1]

6081

1

T2

24

T5

1

T7

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22215

1

T1

20

T2

3

T3

15

auto[1]

3975

1

T2

21

T4

12

T7

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	76	1			T92	12		T252	17		T253	12
values[1]	699	1			T14	3		T40	10		T230	14
values[2]	650	1			T5	1		T8	1		T33	5
values[3]	729	1			T9	5		T40	11		T16	10
values[4]	622	1			T44	13		T108	13		T114	1
values[5]	742	1			T11	1		T13	26		T14	1
values[6]	599	1			T9	10		T145	27		T44	25
values[7]	816	1			T42	1		T146	26		T112	11
values[8]	779	1			T4	5		T42	1		T147	25
values[9]	3508	1			T2	24		T4	9		T5	1
minimum	16970	1			T1	20		T3	15		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	928	1			T14	3		T40	10		T230	14
values[1]	2935	1			T2	24		T5	1		T7	15
values[2]	624	1			T9	5		T40	11		T114	18
values[3]	651	1			T44	13		T108	13		T110	4
values[4]	769	1			T9	10		T11	1		T13	26
values[5]	492	1			T145	16		T42	1		T110	14
values[6]	883	1			T4	5		T146	21		T112	11
values[7]	711	1			T42	1		T146	5		T147	10
values[8]	946	1			T4	9		T5	1		T8	1
values[9]	241	1			T159	15		T151	1		T235	22
minimum	17010	1			T1	20		T3	15		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21887

1

T1

20

T2

24

T3

15

auto[1]

4303

1

T9

33

T12

12

T13

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T14	2		T33	5		T108	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T40	10		T230	1		T34	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T5	1		T8	1		T88	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1581	1			T2	3		T7	2		T12	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T9	5		T114	1		T35	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T40	8		T114	2		T150	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T44	11		T108	13		T110	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T208	1		T231	11		T150	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T13	15		T44	12		T147	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T9	10		T11	1		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T145	1		T88	2		T152	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T42	1		T110	14		T232	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T4	1		T146	13		T112	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T213	10		T233	14		T209	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T42	1		T189	13		T153	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T146	5		T147	10		T112	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T4	1		T9	21		T146	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	1		T8	1		T43	25
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T159	1		T92	8		T252	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T151	1		T235	12		T20	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16854	1			T1	20		T3	15		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T243	13		T254	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T14	1		T86	13		T143	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T230	13		T34	2		T142	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T144	14		T152	23		T163	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	980	1			T2	21		T7	13		T30	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T35	1		T143	11		T144	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T40	3		T114	15		T150	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T44	2		T164	12		T37	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T150	10		T163	16		T177	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T13	11		T44	13		T241	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T145	10		T112	5		T142	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T145	15		T152	12		T240	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T255	13		T58	4		T256	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T4	4		T146	8		T112	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T213	8		T233	12		T209	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T189	13		T37	1		T92	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T112	12		T167	10		T186	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T4	8		T146	4		T142	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T43	2		T189	9		T257	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T159	14		T92	7		T252	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T235	10		T258	10		T259	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	2		T14	1		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T243	12		T254	2		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T92	7		T252	1		T260	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T253	12		T261	1		T262	24
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T14	2		T108	12		T143	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T40	10		T230	1		T34	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	1		T8	1		T33	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T231	5		T189	14		T152	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T9	5		T208	1		T169	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T40	8		T16	7		T114	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T44	11		T108	13		T114	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T208	1		T231	11		T163	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T13	15		T110	4		T250	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T11	1		T14	1		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T145	1		T44	12		T147	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T9	10		T145	1		T110	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T146	13		T112	1		T174	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T42	1		T146	5		T213	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T4	1		T42	1		T174	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T147	25		T112	1		T233	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	395	1			T4	1		T9	21		T146	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1721	1			T2	3		T5	1		T7	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16853	1			T1	20		T3	15		T6	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T92	5		T252	16		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T261	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T14	1		T143	14		T152	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T230	13		T34	2		T142	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T86	13		T144	14		T163	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T189	5		T152	8		T263	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T144	4		T152	23		T243	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T40	3		T16	3		T114	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T44	2		T35	1		T143	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T163	16		T166	7		T22	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	11		T264	15		T265	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T142	14		T150	10		T177	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T145	15		T44	13		T241	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T145	10		T112	5		T177	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T146	8		T112	10		T152	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T213	8		T209	8		T241	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T4	4		T150	17		T189	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T112	12		T233	12		T186	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	370	1			T4	8		T146	4		T159	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1022	1			T2	21		T7	13		T30	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	2		T14	1		T33	1