Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26190

1

T1

20

T2

24

T3

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22284

1

T1

20

T2

24

T3

15

auto[ADC_CTRL_FILTER_COND_OUT]

3906

1

T4

14

T8

1

T9

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19879

1

T1

20

T3

15

T4

14

auto[1]

6311

1

T2

24

T7

15

T8

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22215

1

T1

20

T2

3

T3

15

auto[1]

3975

1

T2

21

T4

12

T7

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	240	1			T9	5		T208	1		T144	10
values[0]	6	1			T35	1		T297	1		T277	4
values[1]	642	1			T4	9		T42	1		T230	14
values[2]	719	1			T13	26		T40	10		T43	17
values[3]	759	1			T8	1		T9	21		T11	1
values[4]	563	1			T5	2		T146	5		T147	13
values[5]	706	1			T9	10		T145	11		T147	15
values[6]	741	1			T34	6		T110	4		T114	6
values[7]	695	1			T8	1		T42	1		T159	15
values[8]	2939	1			T2	24		T7	15		T12	14
values[9]	1210	1			T4	5		T14	3		T40	11
minimum	16970	1			T1	20		T3	15		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	574	1			T4	9		T42	1		T230	14
values[1]	786	1			T8	1		T9	21		T11	1
values[2]	645	1			T5	1		T147	13		T231	11
values[3]	652	1			T5	1		T146	5		T110	13
values[4]	608	1			T9	10		T145	11		T147	15
values[5]	832	1			T8	1		T34	6		T108	13
values[6]	2840	1			T2	24		T7	15		T12	14
values[7]	802	1			T43	10		T16	10		T112	13
values[8]	1017	1			T4	5		T9	5		T14	3
values[9]	227	1			T208	1		T152	22		T238	21
minimum	17207	1			T1	20		T3	15		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21887

1

T1

20

T2

24

T3

15

auto[1]

4303

1

T9

33

T12

12

T13

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T33	5		T108	12		T241	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T4	1		T42	1		T230	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T9	21		T11	1		T13	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T8	1		T40	10		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T5	1		T231	11		T190	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T147	13		T241	18		T297	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	1		T110	13		T208	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T146	5		T174	12		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T145	1		T147	15		T110	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T9	10		T88	1		T142	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T8	1		T34	4		T108	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T114	2		T35	8		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1483	1			T2	3		T7	2		T12	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T42	1		T146	7		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T112	1		T232	1		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T43	10		T16	7		T169	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T9	5		T40	8		T146	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T4	1		T14	2		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T152	10		T170	10		T317	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T208	1		T238	15		T264	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16907	1			T1	20		T3	15		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T44	12		T110	14		T35	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T241	8		T264	5		T235	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T4	8		T230	13		T142	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	11		T43	2		T44	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T240	18		T92	5		T210	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T272	12		T325	5		T309	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T241	15		T247	9		T19	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T233	12		T164	15		T37	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T37	1		T22	1		T324	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T145	10		T144	4		T238	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T142	14		T36	2		T177	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T34	2		T112	5		T86	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T114	4		T35	1		T142	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	892	1			T2	21		T7	13		T30	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T146	4		T159	14		T243	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T112	12		T150	10		T189	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T16	3		T143	14		T164	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T40	3		T146	8		T242	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T4	4		T14	1		T145	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T152	12		T317	12		T326	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T238	6		T264	15		T32	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	2		T14	1		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T44	13		T181	14		T327	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T9	5		T96	5		T104	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T208	1		T144	6		T150	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T277	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T35	1		T297	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T147	10		T112	1		T152	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T4	1		T42	1		T230	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T13	15		T43	15		T33	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T40	10		T189	11		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T9	21		T11	1		T231	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T8	1		T240	1		T209	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T5	2		T208	1		T233	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T146	5		T147	13		T174	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T145	1		T147	15		T110	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T9	10		T88	1		T36	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T34	4		T110	4		T143	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T114	2		T35	8		T142	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T8	1		T108	13		T112	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T42	1		T159	1		T232	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1542	1			T2	3		T7	2		T12	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T146	7		T16	7		T169	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T40	8		T146	13		T88	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	388	1			T4	1		T14	2		T145	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16853	1			T1	20		T3	15		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T328	6		T329	11		T330	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T144	4		T150	8		T167	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T277	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T112	10		T152	8		T241	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T4	8		T230	13		T44	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T13	11		T43	2		T44	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T189	9		T210	2		T310	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T272	12		T274	4		T309	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T240	18		T241	15		T92	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T233	12		T186	15		T209	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T37	1		T22	1		T215	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T145	10		T144	4		T164	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T36	2		T177	13		T210	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T34	2		T143	11		T39	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T114	4		T35	1		T142	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T112	5		T86	13		T163	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T159	14		T243	12		T92	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	969	1			T2	21		T7	13		T30	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T146	4		T16	3		T143	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T40	3		T146	8		T150	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T4	4		T14	1		T145	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	2		T14	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T33	4		T108	1		T241	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T4	9		T42	1		T230	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T9	1		T11	1		T13	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T8	1		T40	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	1		T231	1		T190	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T147	1		T241	16		T297	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T5	1		T110	1		T208	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T146	1		T174	1		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T145	11		T147	1		T110	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T9	1		T88	1		T142	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	1		T34	4		T108	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T114	6		T35	6		T142	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1225	1			T2	24		T7	15		T12	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T42	1		T146	5		T159	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T112	13		T232	1		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T43	1		T16	7		T169	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T9	1		T40	4		T146	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T4	5		T14	3		T145	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T152	13		T170	1		T317	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T208	1		T238	7		T264	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17044	1			T1	20		T3	15		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T44	14		T110	1		T35	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T33	1		T108	11		T241	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T142	6		T213	9		T144	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T9	20		T13	7		T43	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T40	9		T250	10		T92	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T231	10		T190	14		T272	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T147	12		T241	17		T294	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T110	12		T174	14		T233	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T146	4		T174	11		T162	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T147	14		T110	3		T144	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T9	9		T142	19		T36	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T34	2		T108	12		T143	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T35	3		T163	12		T168	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1150	1			T12	12		T41	7		T160	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T146	6		T168	16		T220	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T150	5		T189	13		T263	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T43	9		T16	3		T143	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T9	4		T40	7		T146	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T144	5		T150	28		T189	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T152	9		T170	9		T317	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T238	14		T264	12		T90	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T147	9		T152	7		T246	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T44	11		T110	13		T181	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T9	1		T96	1		T104	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T208	1		T144	5		T150	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T277	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T35	1		T297	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T147	1		T112	11		T152	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T4	9		T42	1		T230	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T13	19		T43	3		T33	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T40	1		T189	10		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	1		T11	1		T231	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T8	1		T240	19		T209	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T5	2		T208	1		T233	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T146	1		T147	1		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T145	11		T147	1		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T9	1		T88	1		T36	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T34	4		T110	1		T143	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T114	6		T35	6		T142	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	1		T108	1		T112	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T42	1		T159	15		T232	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1299	1			T2	24		T7	15		T12	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T146	5		T16	7		T169	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T40	4		T146	9		T88	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T4	5		T14	3		T145	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16970	1			T1	20		T3	15		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T9	4		T96	4		T104	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T144	5		T150	12		T167	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T277	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T147	9		T152	7		T241	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T44	11		T110	13		T142	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T13	7		T43	14		T33	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T40	9		T189	10		T176	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T9	20		T231	10		T190	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T241	17		T92	6		T294	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T233	13		T186	15		T171	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T146	4		T147	12		T174	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T147	14		T110	12		T174	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T9	9		T36	2		T168	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T34	2		T110	3		T143	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T35	3		T142	19		T163	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T108	12		T231	4		T163	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T168	16		T220	2		T243	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1212	1			T12	12		T41	7		T160	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T146	6		T16	3		T143	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T40	7		T146	12		T150	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T43	9		T150	16		T189	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21887

1

T1

20

T2

24

T3

15

auto[1]

auto[0]

4303

1

T9

33

T12

12

T13

7