Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26190

1

T1

20

T2

24

T3

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22706

1

T1

20

T2

24

T3

15

auto[ADC_CTRL_FILTER_COND_OUT]

3484

1

T4

5

T5

1

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19897

1

T1

20

T3

15

T5

1

auto[1]

6293

1

T2

24

T4

14

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22215

1

T1

20

T2

3

T3

15

auto[1]

3975

1

T2

21

T4

12

T7

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	99	1			T331	1		T228	16		T289	10
values[0]	115	1			T142	2		T231	5		T175	1
values[1]	531	1			T4	9		T110	13		T17	1
values[2]	2840	1			T2	24		T7	15		T12	14
values[3]	673	1			T11	1		T86	14		T87	1
values[4]	787	1			T145	16		T43	17		T230	14
values[5]	765	1			T4	5		T14	1		T112	17
values[6]	646	1			T5	1		T16	10		T114	1
values[7]	614	1			T8	2		T9	21		T145	11
values[8]	751	1			T5	1		T14	3		T42	1
values[9]	1399	1			T9	15		T13	26		T43	10
minimum	16970	1			T1	20		T3	15		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	785	1			T4	9		T110	13		T88	2
values[1]	2819	1			T2	24		T7	15		T12	14
values[2]	672	1			T11	1		T44	25		T108	25
values[3]	776	1			T4	5		T14	1		T145	16
values[4]	769	1			T43	17		T112	11		T148	16
values[5]	613	1			T5	1		T147	15		T16	10
values[6]	739	1			T8	2		T9	21		T145	11
values[7]	792	1			T5	1		T9	5		T14	3
values[8]	1058	1			T9	10		T43	10		T157	1
values[9]	179	1			T13	26		T159	15		T110	14
minimum	16988	1			T1	20		T3	15		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21887

1

T1

20

T2

24

T3

15

auto[1]

4303

1

T9

33

T12

12

T13

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T4	1		T110	13		T88	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T88	1		T17	1		T169	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1536	1			T2	3		T7	2		T12	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T40	8		T33	5		T232	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T110	4		T87	1		T152	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T11	1		T44	12		T108	25
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T145	1		T146	13		T147	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T4	1		T14	1		T230	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T43	15		T148	16		T144	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T112	1		T169	1		T150	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T147	15		T112	1		T232	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T5	1		T16	7		T114	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T8	1		T9	21		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T8	1		T42	1		T143	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T5	1		T146	5		T147	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T9	5		T14	2		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T43	10		T157	1		T112	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T9	10		T83	1		T142	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T13	15		T110	14		T232	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T159	1		T114	1		T39	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16853	1			T1	20		T3	15		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T332	10		T333	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T4	8		T142	1		T37	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T150	17		T36	2		T163	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1008	1			T2	21		T7	13		T30	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T40	3		T213	8		T233	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T152	8		T255	7		T19	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T44	13		T86	13		T35	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T145	15		T146	8		T34	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T4	4		T230	13		T189	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T43	2		T144	4		T164	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T112	10		T150	10		T152	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T112	5		T167	10		T264	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T16	3		T152	12		T164	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T145	10		T146	4		T144	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T143	11		T186	15		T105	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T142	13		T144	14		T331	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T14	1		T44	2		T150	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T112	12		T114	11		T189	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T142	14		T152	15		T241	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T13	11		T289	4		T334	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T159	14		T114	4		T39	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	2		T14	1		T33	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T331	1		T228	1		T289	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T335	1		T336	14		T330	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T142	1		T231	5		T175	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T220	3		T337	9		T338	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T4	1		T110	13		T37	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T17	1		T150	17		T176	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1578	1			T2	3		T7	2		T12	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T40	8		T33	5		T108	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T87	1		T149	1		T249	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T11	1		T86	1		T35	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T145	1		T43	15		T146	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T230	1		T44	12		T108	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T112	1		T148	16		T176	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T4	1		T14	1		T112	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T144	6		T167	12		T249	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T5	1		T16	7		T114	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T8	1		T9	21		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T8	1		T42	1		T243	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	1		T146	5		T147	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T14	2		T42	1		T88	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	387	1			T13	15		T43	10		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	368	1			T9	15		T44	11		T159	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16853	1			T1	20		T3	15		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T228	15		T289	4		T339	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T335	10		T336	10		T330	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T142	1		T240	18		T58	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T337	3		T338	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T4	8		T37	1		T241	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T150	17		T36	2		T177	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	966	1			T2	21		T7	13		T30	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T40	3		T143	14		T163	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T149	4		T19	3		T270	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T86	13		T35	1		T213	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T145	15		T43	2		T146	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T230	13		T44	13		T189	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T112	5		T164	12		T239	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T4	4		T112	10		T150	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T144	4		T167	10		T264	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T16	3		T152	12		T164	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T145	10		T146	4		T144	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T243	4		T105	13		T340	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T142	13		T209	8		T92	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T14	1		T143	11		T177	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T13	11		T112	12		T114	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T44	2		T159	14		T114	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	2		T14	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T4	9		T110	1		T88	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T88	1		T17	1		T169	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T2	24		T7	15		T12	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T40	4		T33	4		T232	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T110	1		T87	1		T152	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T11	1		T44	14		T108	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T145	16		T146	9		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T4	5		T14	1		T230	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T43	3		T148	1		T144	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T112	11		T169	1		T150	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T147	1		T112	6		T232	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T5	1		T16	7		T114	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T8	1		T9	1		T145	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T8	1		T42	1		T143	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T5	1		T146	1		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T9	1		T14	3		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T43	1		T157	1		T112	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T9	1		T83	1		T142	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T13	19		T110	1		T232	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T159	15		T114	5		T39	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16970	1			T1	20		T3	15		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T332	1		T333	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T110	12		T231	4		T58	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T150	16		T176	8		T36	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1201	1			T12	12		T40	9		T41	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T40	7		T33	1		T213	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T110	3		T152	7		T249	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T44	11		T108	23		T35	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T146	12		T147	9		T34	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T189	10		T163	14		T235	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T43	14		T148	15		T144	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T150	5		T152	19		T243	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T147	14		T167	11		T249	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T16	3		T152	9		T162	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T9	20		T146	6		T144	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T143	9		T186	15		T294	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T146	4		T147	12		T142	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T9	4		T44	10		T150	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T43	9		T231	10		T189	25
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	9		T142	19		T241	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T13	7		T110	13		T289	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T330	14		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T332	9		T333	7		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T331	1		T228	16		T289	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T335	11		T336	11		T330	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T142	2		T231	1		T175	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T220	1		T337	4		T338	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T4	9		T110	1		T37	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T17	1		T150	18		T176	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1299	1			T2	24		T7	15		T12	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T40	4		T33	4		T108	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T87	1		T149	5		T249	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T11	1		T86	14		T35	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T145	16		T43	3		T146	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T230	14		T44	14		T108	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T112	6		T148	1		T176	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T4	5		T14	1		T112	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T144	5		T167	11		T249	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T5	1		T16	7		T114	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T8	1		T9	1		T145	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T8	1		T42	1		T243	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T5	1		T146	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T14	3		T42	1		T88	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	379	1			T13	19		T43	1		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	412	1			T9	2		T44	3		T159	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16970	1			T1	20		T3	15		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T289	5		T339	1		T267	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T336	13		T330	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T231	4		T58	1		T182	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T220	2		T337	8		T338	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T110	12		T166	6		T214	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T150	16		T176	8		T36	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1245	1			T12	12		T40	9		T41	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T40	7		T33	1		T108	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T249	8		T250	10		T19	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T35	3		T213	9		T233	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T43	14		T146	12		T147	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T44	11		T108	11		T189	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T148	15		T176	10		T153	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T150	5		T152	19		T243	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T144	5		T167	11		T249	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T16	3		T152	9		T162	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T9	20		T146	6		T147	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T243	3		T105	12		T301	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T146	4		T147	12		T142	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T143	9		T177	14		T294	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T13	7		T43	9		T110	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T9	13		T44	10		T142	19

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21887

1

T1

20

T2

24

T3

15

auto[1]

auto[0]

4303

1

T9

33

T12

12

T13

7