Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26190

1

T1

20

T2

24

T3

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22674

1

T1

20

T2

24

T3

15

auto[ADC_CTRL_FILTER_COND_OUT]

3516

1

T4

9

T8

1

T11

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19744

1

T1

20

T3

15

T6

20

auto[1]

6446

1

T2

24

T4

14

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22215

1

T1

20

T2

3

T3

15

auto[1]

3975

1

T2

21

T4

12

T7

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	609	1			T29	2		T46	4		T47	4
values[0]	13	1			T295	1		T107	4		T341	8
values[1]	818	1			T5	1		T8	1		T9	5
values[2]	2863	1			T2	24		T7	15		T11	1
values[3]	635	1			T40	11		T33	5		T110	14
values[4]	764	1			T8	1		T43	17		T16	10
values[5]	794	1			T4	9		T14	3		T145	11
values[6]	724	1			T5	1		T9	21		T44	13
values[7]	771	1			T4	5		T9	10		T146	21
values[8]	707	1			T114	5		T83	1		T88	1
values[9]	935	1			T13	26		T230	14		T44	25
minimum	16557	1			T1	20		T3	15		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	676	1			T5	1		T8	1		T11	1
values[1]	2972	1			T2	24		T7	15		T12	14
values[2]	720	1			T8	1		T40	11		T43	17
values[3]	695	1			T145	11		T157	1		T110	13
values[4]	827	1			T4	9		T5	1		T9	21
values[5]	710	1			T44	13		T147	15		T112	11
values[6]	728	1			T4	5		T9	10		T146	21
values[7]	596	1			T230	14		T83	1		T88	1
values[8]	941	1			T13	26		T44	25		T108	13
values[9]	132	1			T114	12		T170	10		T264	16
minimum	17193	1			T1	20		T3	15		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21887

1

T1

20

T2

24

T3

15

auto[1]

4303

1

T9

33

T12

12

T13

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T5	1		T8	1		T42	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T11	1		T14	1		T147	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1634	1			T2	3		T7	2		T12	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T147	13		T114	1		T189	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T40	8		T33	5		T108	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T8	1		T43	15		T16	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T145	1		T157	1		T110	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T35	1		T232	1		T174	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T5	1		T9	21		T43	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T4	1		T14	2		T88	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T147	15		T174	15		T143	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T44	11		T112	1		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T4	1		T9	10		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T146	13		T86	1		T231	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T230	1		T88	1		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T83	1		T150	17		T164	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T44	12		T112	1		T114	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T13	15		T108	13		T213	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T170	10		T264	9		T235	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T114	1		T342	1		T300	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16885	1			T1	20		T3	15		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T145	1		T42	1		T176	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T146	4		T220	13		T93	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T142	13		T189	5		T152	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1039	1			T2	21		T7	13		T30	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T189	9		T240	18		T331	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T40	3		T112	12		T35	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T43	2		T16	3		T150	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T145	10		T233	12		T167	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T144	4		T248	9		T270	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T143	11		T164	12		T241	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T4	8		T14	1		T152	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T143	14		T152	12		T36	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T44	2		T112	10		T142	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T4	4		T159	14		T34	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T146	8		T86	13		T164	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T230	13		T144	4		T163	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T150	17		T97	13		T257	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T44	13		T112	5		T114	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T13	11		T213	8		T150	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T264	7		T235	10		T298	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T114	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	2		T14	1		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T145	15		T107	7		T343	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	496	1			T29	2		T46	4		T47	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T114	1		T215	17		T300	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T341	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T295	1		T107	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	1		T8	1		T9	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T14	1		T145	1		T42	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1570	1			T2	3		T7	2		T12	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T11	1		T147	13		T110	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T40	8		T33	5		T110	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T148	16		T150	6		T189	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T108	12		T110	13		T35	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T8	1		T43	15		T16	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T145	1		T43	10		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T4	1		T14	2		T88	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T5	1		T9	21		T147	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T44	11		T112	1		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T4	1		T9	10		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T146	13		T86	1		T234	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T114	1		T88	1		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T83	1		T231	11		T150	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T230	1		T44	12		T112	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T13	15		T108	13		T213	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16440	1			T1	20		T3	15		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T238	1		T92	7		T283	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T114	11		T215	12		T286	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T341	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T107	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T146	4		T163	2		T220	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T145	15		T142	13		T189	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	974	1			T2	21		T7	13		T30	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T189	9		T240	18		T39	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T40	3		T112	12		T149	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T150	10		T189	13		T240	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T35	1		T233	12		T167	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T43	2		T16	3		T144	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T145	10		T143	11		T209	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T4	8		T14	1		T152	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T143	14		T152	12		T36	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T44	2		T112	10		T142	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T4	4		T159	14		T34	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T146	8		T86	13		T164	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T114	4		T163	14		T209	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T150	17		T97	13		T257	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T230	13		T44	13		T112	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T13	11		T213	8		T150	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	2		T14	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	1		T8	1		T42	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T11	1		T14	1		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1379	1			T2	24		T7	15		T12	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T147	1		T114	1		T189	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T40	4		T33	4		T108	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T8	1		T43	3		T16	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T145	11		T157	1		T110	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T35	1		T232	1		T174	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T5	1		T9	1		T43	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T4	9		T14	3		T88	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T147	1		T174	1		T143	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T44	3		T112	11		T142	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T4	5		T9	1		T159	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T146	9		T86	14		T231	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T230	14		T88	1		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T83	1		T150	18		T164	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T44	14		T112	6		T114	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T13	19		T108	1		T213	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T170	1		T264	8		T235	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T114	12		T342	1		T300	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17017	1			T1	20		T3	15		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T145	16		T42	1		T176	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T146	6		T93	15		T302	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T147	9		T110	3		T142	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T12	12		T40	9		T41	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T147	12		T189	10		T331	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T40	7		T33	1		T108	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T43	14		T16	3		T148	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T110	12		T233	13		T167	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T174	11		T144	12		T168	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T9	20		T43	9		T143	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T168	13		T37	3		T186	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T147	14		T174	14		T143	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T44	10		T167	11		T163	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	9		T34	2		T162	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T146	12		T231	10		T162	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T144	5		T163	12		T243	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T150	16		T94	14		T97	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T44	11		T142	19		T144	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T13	7		T108	12		T213	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T170	9		T264	8		T235	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T300	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T9	4		T163	6		T301	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T176	8		T250	11		T323	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	469	1			T29	2		T46	4		T47	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T114	12		T215	13		T300	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T341	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T295	1		T107	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	1		T8	1		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T14	1		T145	16		T42	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T2	24		T7	15		T12	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T11	1		T147	1		T110	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T40	4		T33	4		T110	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T148	1		T150	11		T189	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T108	1		T110	1		T35	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T8	1		T43	3		T16	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T145	11		T43	1		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T4	9		T14	3		T88	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	1		T9	1		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T44	3		T112	11		T142	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T4	5		T9	1		T159	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T146	9		T86	14		T234	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T114	5		T88	1		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T83	1		T231	1		T150	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T230	14		T44	14		T112	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T13	19		T108	1		T213	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16557	1			T1	20		T3	15		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T170	9		T92	7		T190	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T215	16		T300	11		T344	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T107	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T9	4		T146	6		T163	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T147	9		T142	6		T231	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1244	1			T12	12		T40	9		T41	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T147	12		T110	3		T189	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T40	7		T33	1		T110	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T148	15		T150	5		T189	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T108	11		T110	12		T35	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T43	14		T16	3		T144	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T43	9		T143	9		T249	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T174	11		T168	13		T37	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	20		T147	14		T174	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T44	10		T167	11		T163	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T9	9		T34	2		T162	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T146	12		T162	11		T164	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T163	12		T302	11		T299	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T231	10		T150	16		T94	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T44	11		T142	19		T144	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T13	7		T108	12		T213	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21887

1

T1

20

T2

24

T3

15

auto[1]

auto[0]

4303

1

T9

33

T12

12

T13

7