Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26190

1

T1

20

T2

24

T3

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22902

1

T1

20

T2

24

T3

15

auto[ADC_CTRL_FILTER_COND_OUT]

3288

1

T9

21

T13

26

T14

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20235

1

T1

20

T3

15

T4

14

auto[1]

5955

1

T2

24

T5

1

T7

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22215

1

T1

20

T2

3

T3

15

auto[1]

3975

1

T2

21

T4

12

T7

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	250	1			T146	21		T147	15		T169	1
values[0]	98	1			T9	21		T250	12		T270	6
values[1]	614	1			T4	9		T5	1		T9	10
values[2]	889	1			T110	13		T88	1		T232	1
values[3]	661	1			T13	26		T42	1		T159	15
values[4]	723	1			T5	1		T8	1		T11	1
values[5]	2780	1			T2	24		T4	5		T7	15
values[6]	879	1			T40	11		T145	16		T44	25
values[7]	679	1			T145	11		T42	1		T33	5
values[8]	547	1			T14	3		T108	12		T114	13
values[9]	1100	1			T8	1		T9	5		T40	10
minimum	16970	1			T1	20		T3	15		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	660	1			T4	9		T5	1		T9	10
values[1]	966	1			T159	15		T232	1		T174	15
values[2]	574	1			T13	26		T42	1		T16	10
values[3]	2917	1			T2	24		T5	1		T7	15
values[4]	630	1			T4	5		T157	1		T147	13
values[5]	726	1			T145	27		T42	1		T33	5
values[6]	738	1			T40	11		T34	6		T114	12
values[7]	633	1			T14	3		T147	10		T108	12
values[8]	1022	1			T8	1		T40	10		T43	17
values[9]	117	1			T9	5		T146	21		T345	1
minimum	17207	1			T1	20		T3	15		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21887

1

T1

20

T2

24

T3

15

auto[1]

4303

1

T9

33

T12

12

T13

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T4	1		T5	1		T9	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T108	13		T110	13		T114	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T150	19		T189	13		T168	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T159	1		T232	1		T174	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T16	7		T149	1		T175	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	15		T42	1		T88	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1592	1			T2	3		T5	1		T7	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T14	1		T112	1		T142	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T4	1		T208	1		T177	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T157	1		T147	13		T87	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T145	1		T42	1		T33	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T145	1		T35	8		T143	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T40	8		T34	4		T83	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T114	1		T86	1		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T108	12		T169	1		T231	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	2		T147	10		T114	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T8	1		T40	10		T230	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T43	15		T142	8		T17	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T9	5		T281	1		T183	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T146	13		T345	1		T211	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16927	1			T1	20		T3	15		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T9	21		T163	7		T270	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T4	8		T112	12		T144	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T114	4		T152	8		T164	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T150	18		T189	13		T239	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T159	14		T164	12		T18	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T16	3		T149	4		T36	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T13	11		T143	11		T37	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	989	1			T2	21		T7	13		T30	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T112	10		T142	14		T209	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T4	4		T177	4		T257	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T233	12		T189	9		T39	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T145	10		T44	13		T112	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T145	15		T35	1		T143	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T40	3		T34	2		T144	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T114	11		T86	13		T213	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T255	7		T264	20		T242	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T14	1		T177	9		T247	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T230	13		T241	8		T239	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T43	2		T142	14		T97	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T146	8		T211	13		T346	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	2		T14	1		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T163	2		T270	5		T252	16

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T147	15		T231	5		T249	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T146	13		T169	1		T249	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T347	1		T282	1		T193	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T9	21		T250	12		T270	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T4	1		T5	1		T9	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T108	13		T114	1		T88	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T144	6		T150	6		T189	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T110	13		T88	1		T232	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T149	1		T150	13		T175	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T13	15		T42	1		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	1		T8	1		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T14	1		T112	1		T88	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1535	1			T2	3		T4	1		T7	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T157	1		T147	13		T87	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T40	8		T44	12		T112	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T145	1		T143	16		T234	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T145	1		T42	1		T33	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T86	1		T35	8		T232	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T108	12		T169	1		T231	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T14	2		T114	2		T213	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	356	1			T8	1		T9	5		T40	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T43	15		T147	10		T142	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16853	1			T1	20		T3	15		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T241	8		T239	8		T235	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T146	8		T211	13		T318	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T282	6		T193	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T270	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T4	8		T112	12		T150	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T114	4		T152	8		T163	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T144	4		T150	10		T189	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T209	12		T18	1		T283	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T149	4		T150	8		T36	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T13	11		T159	14		T164	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T44	2		T16	3		T152	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T112	10		T142	14		T143	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	941	1			T2	21		T4	4		T7	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T233	12		T189	9		T241	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T40	3		T44	13		T112	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T145	15		T143	14		T152	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T145	10		T34	2		T144	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T86	13		T35	1		T144	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T264	5		T242	3		T22	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T14	1		T114	11		T213	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T230	13		T220	13		T255	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T43	2		T142	14		T97	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	2		T14	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T4	9		T5	1		T9	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T108	1		T110	1		T114	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T150	20		T189	14		T168	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T159	15		T232	1		T174	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T16	7		T149	5		T175	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T13	19		T42	1		T88	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1329	1			T2	24		T5	1		T7	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T14	1		T112	11		T142	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T4	5		T208	1		T177	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T157	1		T147	1		T87	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T145	11		T42	1		T33	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T145	16		T35	6		T143	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T40	4		T34	4		T83	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T114	12		T86	14		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T108	1		T169	1		T231	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T14	3		T147	1		T114	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T8	1		T40	1		T230	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T43	3		T142	16		T17	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T9	1		T281	1		T183	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T146	9		T345	1		T211	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17027	1			T1	20		T3	15		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T9	1		T163	3		T270	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	9		T146	4		T144	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T108	12		T110	12		T152	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T150	17		T189	12		T168	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T174	14		T167	11		T250	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T16	3		T36	2		T243	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	7		T143	9		T37	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1252	1			T12	12		T41	7		T44	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T142	19		T162	13		T249	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T177	2		T220	2		T257	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T147	12		T233	13		T189	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T33	1		T44	11		T189	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T35	3		T143	15		T152	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T40	7		T34	2		T144	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T213	9		T174	11		T144	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T108	11		T231	10		T255	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T147	9		T168	25		T177	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T40	9		T147	14		T148	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T43	14		T142	6		T176	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T9	4		T284	17		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T146	12		T211	10		T346	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T43	9		T103	16		T348	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T9	20		T163	6		T313	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T147	1		T231	1		T249	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T146	9		T169	1		T249	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T347	1		T282	7		T193	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T9	1		T250	1		T270	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T4	9		T5	1		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T108	1		T114	5		T88	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T144	5		T150	11		T189	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T110	1		T88	1		T232	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T149	5		T150	9		T175	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T13	19		T42	1		T159	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T5	1		T8	1		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T14	1		T112	11		T88	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T2	24		T4	5		T7	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T157	1		T147	1		T87	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T40	4		T44	14		T112	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T145	16		T143	15		T234	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T145	11		T42	1		T33	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T86	14		T35	6		T232	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T108	1		T169	1		T231	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T14	3		T114	13		T213	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T8	1		T9	1		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T43	3		T147	1		T142	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16970	1			T1	20		T3	15		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T147	14		T231	4		T249	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T146	12		T249	13		T211	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T193	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T9	20		T250	11		T262	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T9	9		T43	9		T146	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T108	12		T152	7		T163	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T144	5		T150	5		T189	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T110	12		T174	14		T167	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T150	12		T36	2		T247	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	7		T37	3		T248	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T44	10		T16	3		T110	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T142	19		T143	9		T162	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1208	1			T12	12		T41	7		T146	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T147	12		T233	13		T189	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T40	7		T44	11		T189	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T143	15		T152	19		T235	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T33	1		T34	2		T144	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T35	3		T174	11		T144	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T108	11		T231	10		T264	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T213	9		T163	12		T168	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T9	4		T40	9		T148	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T43	14		T147	9		T142	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21887

1

T1

20

T2

24

T3

15

auto[1]

auto[0]

4303

1

T9

33

T12

12

T13

7