Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26190

1

T1

20

T2

24

T3

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22697

1

T1

20

T2

24

T3

15

auto[ADC_CTRL_FILTER_COND_OUT]

3493

1

T4

5

T5

1

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19910

1

T1

20

T3

15

T5

1

auto[1]

6280

1

T2

24

T4

14

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22215

1

T1

20

T2

3

T3

15

auto[1]

3975

1

T2

21

T4

12

T7

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	352	1			T159	15		T110	14		T114	5
values[0]	54	1			T175	1		T240	19		T220	3
values[1]	547	1			T4	9		T110	13		T142	2
values[2]	2874	1			T2	24		T7	15		T12	14
values[3]	656	1			T11	1		T108	25		T86	14
values[4]	763	1			T145	16		T230	14		T44	25
values[5]	821	1			T4	5		T14	1		T43	17
values[6]	639	1			T5	1		T114	1		T144	10
values[7]	661	1			T8	2		T9	21		T145	11
values[8]	735	1			T5	1		T14	3		T42	1
values[9]	1118	1			T9	15		T13	26		T43	10
minimum	16970	1			T1	20		T3	15		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	673	1			T110	13		T88	1		T17	1
values[1]	2788	1			T2	24		T7	15		T12	14
values[2]	672	1			T11	1		T44	25		T108	25
values[3]	774	1			T14	1		T145	16		T230	14
values[4]	815	1			T4	5		T43	17		T112	17
values[5]	590	1			T5	1		T146	11		T147	15
values[6]	696	1			T8	2		T9	21		T145	11
values[7]	780	1			T5	1		T9	5		T14	3
values[8]	1088	1			T9	10		T43	10		T157	1
values[9]	162	1			T13	26		T110	14		T114	5
minimum	17152	1			T1	20		T3	15		T4	9

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21887

1

T1

20

T2

24

T3

15

auto[1]

4303

1

T9

33

T12

12

T13

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T110	13		T88	1		T37	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T17	1		T169	1		T143	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1515	1			T2	3		T7	2		T12	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T40	8		T33	5		T88	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T87	1		T149	1		T152	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T11	1		T44	12		T108	25
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T145	1		T146	13		T147	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	1		T230	1		T234	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T43	15		T112	1		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T4	1		T112	1		T169	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T146	7		T147	15		T232	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T5	1		T114	1		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T8	1		T9	21		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T8	1		T42	1		T16	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T5	1		T146	5		T147	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T9	5		T14	2		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T43	10		T157	1		T112	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T9	10		T159	1		T83	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T13	15		T110	14		T232	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T114	1		T178	1		T229	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16893	1			T1	20		T3	15		T4	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T36	4		T177	3		T220	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T37	1		T58	4		T166	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T143	14		T150	17		T163	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1001	1			T2	21		T7	13		T30	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T40	3		T213	8		T233	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T149	4		T152	8		T255	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T44	13		T86	13		T35	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T145	15		T146	8		T34	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T230	13		T189	9		T163	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T43	2		T112	5		T144	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T4	4		T112	10		T150	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T146	4		T167	10		T264	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T152	12		T164	15		T186	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T145	10		T144	4		T92	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T16	3		T143	11		T243	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T142	13		T144	14		T209	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T14	1		T44	2		T150	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T112	12		T114	11		T189	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T159	14		T142	14		T152	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T13	11		T283	9		T289	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T114	4		T229	4		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T4	8		T13	2		T14	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T36	2		T177	4		T211	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T110	14		T175	1		T105	20
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T159	1		T114	1		T142	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T175	1		T240	1		T182	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T220	3		T338	14		T333	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T4	1		T110	13		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T17	1		T150	17		T176	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1581	1			T2	3		T7	2		T12	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T40	8		T33	5		T88	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T87	1		T149	1		T152	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T11	1		T108	25		T86	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T145	1		T146	13		T147	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T230	1		T44	12		T234	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T43	15		T112	1		T148	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T4	1		T14	1		T112	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T144	6		T167	12		T249	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	1		T114	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T8	1		T9	21		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T8	1		T42	1		T16	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	1		T146	5		T147	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T14	2		T42	1		T88	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T13	15		T43	10		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T9	15		T44	11		T83	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16853	1			T1	20		T3	15		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T105	20		T283	9		T228	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T159	14		T114	4		T142	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T240	18		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T338	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T4	8		T142	1		T37	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T150	17		T36	2		T177	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	961	1			T2	21		T7	13		T30	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T40	3		T143	14		T163	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T149	4		T152	8		T19	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T86	13		T35	1		T213	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T145	15		T146	8		T34	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T230	13		T44	13		T189	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T43	2		T112	5		T164	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T4	4		T112	10		T150	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T144	4		T167	10		T264	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T152	12		T164	15		T186	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T145	10		T146	4		T144	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T16	3		T243	4		T105	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T142	13		T209	8		T92	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T14	1		T143	11		T177	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T13	11		T112	12		T114	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T44	2		T150	8		T152	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	2		T14	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T110	1		T88	1		T37	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T17	1		T169	1		T143	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1332	1			T2	24		T7	15		T12	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T40	4		T33	4		T88	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T87	1		T149	5		T152	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	1		T44	14		T108	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T145	16		T146	9		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T14	1		T230	14		T234	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T43	3		T112	6		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T4	5		T112	11		T169	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T146	5		T147	1		T232	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T5	1		T114	1		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T8	1		T9	1		T145	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T8	1		T42	1		T16	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	1		T146	1		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T9	1		T14	3		T42	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T43	1		T157	1		T112	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T9	1		T159	15		T83	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T13	19		T110	1		T232	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T114	5		T178	1		T229	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17043	1			T1	20		T3	15		T4	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T36	4		T177	5		T220	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T110	12		T58	1		T166	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T143	15		T150	16		T176	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1184	1			T12	12		T40	9		T41	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T40	7		T33	1		T213	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T152	7		T249	8		T250	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T44	11		T108	23		T35	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T146	12		T147	9		T34	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T189	10		T163	14		T248	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T43	14		T144	5		T176	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T150	5		T152	19		T243	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T146	6		T147	14		T167	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T152	9		T162	13		T164	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T9	20		T144	12		T249	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T16	3		T143	9		T243	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T146	4		T147	12		T142	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T9	4		T44	10		T150	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T43	9		T231	10		T189	25
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T9	9		T142	19		T241	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T13	7		T110	13		T283	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T231	4		T327	10		T349	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T36	2		T177	2		T220	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T110	1		T175	1		T105	21
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T159	15		T114	5		T142	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T175	1		T240	19		T182	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T220	1		T338	2		T333	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T4	9		T110	1		T142	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T17	1		T150	18		T176	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T2	24		T7	15		T12	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T40	4		T33	4		T88	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T87	1		T149	5		T152	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T11	1		T108	2		T86	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T145	16		T146	9		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T230	14		T44	14		T234	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T43	3		T112	6		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T4	5		T14	1		T112	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T144	5		T167	11		T249	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T5	1		T114	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T8	1		T9	1		T145	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T8	1		T42	1		T16	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	1		T146	1		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T14	3		T42	1		T88	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T13	19		T43	1		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T9	2		T44	3		T83	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16970	1			T1	20		T3	15		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T110	13		T105	19		T350	21
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T142	19		T336	13		T351	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T182	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T220	2		T338	13		T333	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T110	12		T231	4		T58	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T150	16		T176	8		T36	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1247	1			T12	12		T40	9		T41	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T40	7		T33	1		T174	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T152	7		T249	8		T250	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T108	23		T35	3		T213	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T146	12		T147	9		T34	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T44	11		T189	10		T163	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T43	14		T148	15		T176	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T150	5		T152	19		T243	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T144	5		T167	11		T249	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T152	9		T162	13		T164	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T9	20		T146	6		T147	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T16	3		T243	3		T294	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T146	4		T147	12		T142	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T143	9		T177	14		T241	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T13	7		T43	9		T144	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T9	13		T44	10		T150	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21887

1

T1

20

T2

24

T3

15

auto[1]

auto[0]

4303

1

T9

33

T12

12

T13

7