Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26190

1

T1

20

T2

24

T3

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22468

1

T1

20

T2

24

T3

15

auto[ADC_CTRL_FILTER_COND_OUT]

3722

1

T4

9

T5

1

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19820

1

T1

20

T3

15

T4

14

auto[1]

6370

1

T2

24

T5

1

T7

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22215

1

T1

20

T2

3

T3

15

auto[1]

3975

1

T2

21

T4

12

T7

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	341	1			T43	17		T83	1		T152	43
values[0]	62	1			T112	13		T204	20		T316	29
values[1]	544	1			T5	1		T42	1		T157	1
values[2]	715	1			T4	5		T40	11		T147	15
values[3]	725	1			T44	38		T146	21		T16	10
values[4]	735	1			T4	9		T9	31		T108	13
values[5]	688	1			T145	11		T34	6		T17	1
values[6]	624	1			T14	1		T40	10		T146	16
values[7]	586	1			T8	1		T11	1		T13	26
values[8]	734	1			T5	1		T9	5		T43	10
values[9]	3466	1			T2	24		T7	15		T8	1
minimum	16970	1			T1	20		T3	15		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	626	1			T5	1		T42	1		T147	10
values[1]	833	1			T4	5		T40	11		T44	25
values[2]	687	1			T4	9		T44	13		T146	21
values[3]	667	1			T9	31		T145	11		T34	6
values[4]	620	1			T17	1		T144	22		T234	1
values[5]	632	1			T8	1		T11	1		T14	1
values[6]	2772	1			T2	24		T7	15		T12	14
values[7]	866	1			T5	1		T8	1		T9	5
values[8]	1187	1			T145	16		T33	5		T108	12
values[9]	174	1			T43	17		T232	1		T143	21
minimum	17126	1			T1	20		T3	15		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21887

1

T1

20

T2

24

T3

15

auto[1]

4303

1

T9

33

T12

12

T13

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T42	1		T114	1		T35	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T5	1		T147	10		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T4	1		T40	8		T86	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T44	12		T147	15		T112	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T146	13		T16	7		T108	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T4	1		T44	11		T231	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T9	21		T232	1		T208	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T9	10		T145	1		T34	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T234	1		T189	11		T175	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T17	1		T144	8		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T11	1		T14	1		T40	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T8	1		T87	1		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1466	1			T2	3		T7	2		T12	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T42	1		T230	1		T110	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T5	1		T8	1		T9	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T43	10		T147	13		T142	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T145	1		T88	1		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	393	1			T33	5		T108	12		T83	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T43	15		T143	10		T209	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T232	1		T176	11		T294	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16898	1			T1	20		T3	15		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T157	1		T112	1		T350	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T35	1		T213	8		T240	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T159	14		T152	8		T220	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T4	4		T40	3		T86	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T44	13		T112	5		T189	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T146	8		T16	3		T112	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T4	8		T44	2		T150	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T167	10		T298	13		T58	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T145	10		T34	2		T189	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T189	9		T163	14		T92	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T144	14		T152	15		T255	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T146	4		T152	12		T239	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T264	12		T39	1		T307	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	920	1			T2	21		T7	13		T13	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T230	13		T238	1		T240	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T14	1		T114	11		T142	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T142	14		T144	8		T239	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T145	15		T255	6		T257	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T150	8		T152	23		T241	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T43	2		T143	11		T209	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T309	9		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T13	2		T14	1		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T112	12		T181	1		T348	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T43	15		T209	1		T250	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T83	1		T152	20		T176	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T316	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T112	1		T204	18		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T42	1		T114	1		T213	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T5	1		T157	1		T147	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T4	1		T40	8		T86	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T147	15		T112	1		T232	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T146	13		T16	7		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T44	23		T231	11		T175	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T9	21		T108	13		T112	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T4	1		T9	10		T150	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T208	1		T174	12		T234	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T145	1		T34	4		T17	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T14	1		T40	10		T146	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T87	1		T35	1		T174	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T11	1		T13	15		T114	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T8	1		T42	1		T230	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	1		T9	5		T110	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T43	10		T147	13		T144	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1703	1			T2	3		T7	2		T8	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	434	1			T33	5		T108	12		T88	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16853	1			T1	20		T3	15		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T43	2		T209	12		T257	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T152	23		T275	8		T308	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T316	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T112	12		T204	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T213	8		T240	18		T97	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T159	14		T220	13		T235	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T4	4		T40	3		T86	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T112	5		T189	5		T152	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T146	8		T16	3		T142	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T44	15		T177	9		T37	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T112	10		T149	4		T189	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T4	8		T150	10		T189	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T163	14		T92	7		T58	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T145	10		T34	2		T144	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T146	4		T152	12		T239	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T264	12		T39	1		T307	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T13	11		T114	4		T242	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T230	13		T238	1		T240	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T114	11		T142	13		T233	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T144	8		T239	8		T248	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1066	1			T2	21		T7	13		T14	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T142	14		T150	8		T241	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	2		T14	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T42	1		T114	1		T35	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	1		T147	1		T159	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T4	5		T40	4		T86	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T44	14		T147	1		T112	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T146	9		T16	7		T108	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T4	9		T44	3		T231	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T9	1		T232	1		T208	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T9	1		T145	11		T34	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T234	1		T189	10		T175	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T17	1		T144	15		T152	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	1		T14	1		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T8	1		T87	1		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1249	1			T2	24		T7	15		T12	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T42	1		T230	14		T110	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	1		T8	1		T9	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T43	1		T147	1		T142	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T145	16		T88	1		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T33	4		T108	1		T83	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T43	3		T143	12		T209	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T232	1		T176	1		T294	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17009	1			T1	20		T3	15		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T157	1		T112	13		T350	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T35	3		T213	9		T168	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T147	9		T152	7		T168	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T40	7		T162	13		T177	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T44	11		T147	14		T189	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T146	12		T16	3		T108	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T44	10		T231	10		T150	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T9	20		T174	11		T167	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T9	9		T34	2		T189	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T189	10		T163	12		T168	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T144	7		T255	8		T97	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T40	9		T146	10		T148	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T174	14		T231	4		T249	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1137	1			T12	12		T13	7		T41	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T110	13		T249	8		T18	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T9	4		T110	15		T142	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T43	9		T147	12		T142	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T162	11		T250	10		T220	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T33	1		T108	11		T150	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T43	14		T143	9		T190	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T176	10		T294	2		T309	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T97	19		T322	2		T267	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T350	21		T348	8		T318	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T43	3		T209	13		T250	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T83	1		T152	24		T176	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T316	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T112	13		T204	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T42	1		T114	1		T213	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T5	1		T157	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T4	5		T40	4		T86	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T147	1		T112	6		T232	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T146	9		T16	7		T142	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T44	17		T231	1		T175	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T9	1		T108	1		T112	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	9		T9	1		T150	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T208	1		T174	1		T234	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T145	11		T34	4		T17	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	1		T40	1		T146	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T87	1		T35	1		T174	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	1		T13	19		T114	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T8	1		T42	1		T230	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	1		T9	1		T110	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T43	1		T147	1		T144	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1425	1			T2	24		T7	15		T8	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T33	4		T108	1		T88	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16970	1			T1	20		T3	15		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T43	14		T250	10		T257	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T152	19		T176	10		T250	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T316	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T204	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T213	9		T94	12		T97	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T147	9		T168	16		T249	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T40	7		T35	3		T162	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T147	14		T189	13		T152	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T146	12		T16	3		T150	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T44	21		T231	10		T177	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T9	20		T108	12		T189	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T9	9		T150	5		T189	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T174	11		T176	8		T163	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T34	2		T144	7		T255	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T40	9		T146	10		T148	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T174	14		T249	8		T264	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T13	7		T103	2		T23	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T110	13		T231	4		T249	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	4		T110	15		T142	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T43	9		T147	12		T144	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1344	1			T12	12		T41	7		T160	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	370	1			T33	1		T108	11		T142	19

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21887

1

T1

20

T2

24

T3

15

auto[1]

auto[0]

4303

1

T9

33

T12

12

T13

7