Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T14	3		T33	4		T108	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T40	1		T230	14		T34	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T5	1		T8	1		T88	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1308	1			T2	24		T7	15		T12	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T9	1		T114	1		T35	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T40	4		T114	17		T150	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T44	3		T108	1		T110	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T208	1		T231	1		T150	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	19		T44	14		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T9	1		T11	1		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T145	16		T88	2		T152	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T42	1		T110	1		T232	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T4	5		T146	9		T112	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T213	9		T233	13		T209	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T42	1		T189	14		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T146	1		T147	1		T112	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T4	9		T9	1		T146	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T5	1		T8	1		T43	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T159	15		T92	8		T252	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T151	1		T235	11		T20	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16971	1			T1	20		T3	15		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T243	13		T254	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T33	1		T108	11		T110	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T40	9		T34	2		T142	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T144	7		T152	19		T162	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1253	1			T12	12		T41	7		T160	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	4		T35	3		T143	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T40	7		T150	12		T167	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T44	10		T108	12		T110	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T231	10		T150	5		T163	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	7		T44	11		T147	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T9	9		T142	19		T168	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T152	9		T239	8		T220	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T110	13		T249	8		T255	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T146	12		T174	25		T162	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T213	9		T233	13		T241	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T189	12		T153	16		T92	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T146	4		T147	9		T167	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T9	20		T146	6		T144	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T43	23		T147	14		T148	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T92	7		T266	19		T267	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T235	11		T268	16		T259	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T243	12		T254	11		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T92	6		T252	17		T260	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T253	1		T261	6		T262	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T14	3		T108	1		T143	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T40	1		T230	14		T34	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	1		T8	1		T33	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T231	1		T189	6		T152	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T9	1		T208	1		T169	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T40	4		T16	7		T114	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T44	3		T108	1		T114	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T208	1		T231	1		T163	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T13	19		T110	1		T250	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T11	1		T14	1		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T145	16		T44	14		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T9	1		T145	11		T110	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T146	9		T112	11		T174	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T42	1		T146	1		T213	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T4	5		T42	1		T174	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T147	2		T112	13		T233	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	448	1			T4	9		T9	1		T146	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1380	1			T2	24		T5	1		T7	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16970	1			T1	20		T3	15		T6	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T92	6		T269	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T253	11		T262	23		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T108	11		T143	15		T162	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T40	9		T34	2		T142	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T33	1		T110	12		T144	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T231	4		T189	13		T152	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T9	4		T144	12		T152	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T40	7		T16	3		T150	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T44	10		T108	12		T35	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T231	10		T163	14		T103	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	7		T110	3		T250	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T142	19		T150	5		T168	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T44	11		T147	12		T248	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T9	9		T110	13		T177	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T146	12		T174	11		T152	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T146	4		T213	9		T241	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T174	14		T150	16		T189	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T147	23		T233	13		T186	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T9	20		T146	6		T144	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1363	1			T12	12		T41	7		T43	23

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21887

1

T1

20

T2

24

T3

15

auto[1]

auto[0]

4303

1

T9

33

T12

12

T13

7