Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26190

1

T1

20

T2

24

T3

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22769

1

T1

20

T2

24

T3

15

auto[ADC_CTRL_FILTER_COND_OUT]

3421

1

T4

9

T8

1

T9

21

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20289

1

T1

20

T3

15

T4

5

auto[1]

5901

1

T2

24

T4

9

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22215

1

T1

20

T2

3

T3

15

auto[1]

3975

1

T2

21

T4

12

T7

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	158	1			T33	5		T112	13		T83	1
values[1]	787	1			T5	1		T40	10		T145	16
values[2]	794	1			T4	5		T42	1		T157	1
values[3]	698	1			T5	1		T34	6		T114	13
values[4]	612	1			T8	1		T43	27		T110	4
values[5]	2928	1			T2	24		T4	9		T7	15
values[6]	746	1			T8	1		T14	3		T42	1
values[7]	882	1			T9	31		T146	11		T147	13
values[8]	644	1			T11	1		T142	34		T208	1
values[9]	971	1			T13	26		T14	1		T146	21
minimum	16970	1			T1	20		T3	15		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	711	1			T5	1		T40	10		T145	16
values[1]	759	1			T4	5		T42	1		T147	15
values[2]	674	1			T5	1		T34	6		T110	4
values[3]	2814	1			T2	24		T7	15		T8	1
values[4]	761	1			T4	9		T9	5		T40	11
values[5]	834	1			T8	1		T14	3		T42	1
values[6]	750	1			T9	31		T11	1		T146	11
values[7]	617	1			T13	26		T142	34		T208	1
values[8]	920	1			T14	1		T33	5		T146	21
values[9]	90	1			T83	1		T234	1		T152	16
minimum	17260	1			T1	20		T3	15		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21887

1

T1

20

T2

24

T3

15

auto[1]

4303

1

T9

33

T12

12

T13

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T5	1		T40	10		T16	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T145	1		T146	5		T157	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T4	1		T42	1		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T147	15		T86	1		T233	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	1		T110	4		T114	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T34	4		T114	1		T148	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1614	1			T2	3		T7	2		T12	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T8	1		T17	1		T176	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T9	5		T40	8		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	1		T35	1		T174	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T8	1		T230	1		T147	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T14	2		T42	1		T35	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T9	10		T11	1		T146	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T9	21		T108	12		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T142	20		T38	2		T249	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T13	15		T208	1		T150	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T110	13		T114	1		T142	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T14	1		T33	5		T146	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T83	1		T234	1		T23	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T152	8		T241	4		T218	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16925	1			T1	20		T3	15		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T44	11		T169	1		T90	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T16	3		T112	5		T163	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T145	15		T144	14		T270	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T4	4		T159	14		T144	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T86	13		T233	12		T220	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T243	4		T271	6		T272	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T34	2		T114	11		T152	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	967	1			T2	21		T7	13		T30	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T264	7		T92	5		T58	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T40	3		T145	10		T143	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T4	8		T189	13		T272	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T230	13		T164	15		T240	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T14	1		T35	1		T143	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T146	4		T213	8		T255	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T142	1		T149	4		T150	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T142	14		T239	8		T247	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T13	11		T150	10		T177	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T114	4		T142	13		T144	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T146	8		T112	12		T37	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T23	5		T179	5		T204	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T152	8		T241	8		T273	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	2		T14	1		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T44	2		T274	13		T275	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T83	1		T241	1		T276	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T33	5		T112	1		T234	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	1		T40	10		T44	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T145	1		T44	11		T146	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T4	1		T42	1		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T157	1		T147	15		T169	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T5	1		T114	1		T144	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T34	4		T114	1		T86	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T43	25		T110	4		T88	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T8	1		T17	1		T176	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1638	1			T2	3		T7	2		T9	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T4	1		T35	1		T189	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T8	1		T230	1		T147	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T14	2		T42	1		T35	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T9	10		T146	7		T147	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T9	21		T108	12		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T11	1		T142	20		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T208	1		T149	1		T162	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T110	13		T114	1		T142	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T13	15		T14	1		T146	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16853	1			T1	20		T3	15		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T241	1		T277	1		T278	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T112	12		T152	8		T241	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T44	13		T189	5		T163	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T145	15		T44	2		T144	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T4	4		T159	14		T16	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T220	13		T247	9		T279	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T144	4		T36	2		T243	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T34	2		T114	11		T86	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T43	2		T37	8		T248	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T264	7		T92	5		T58	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1030	1			T2	21		T7	13		T30	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T4	8		T189	13		T272	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T230	13		T143	11		T152	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T14	1		T35	1		T164	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T146	4		T213	8		T164	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T142	1		T143	14		T150	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T142	14		T239	8		T257	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T149	4		T163	18		T177	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T114	4		T142	13		T144	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	11		T146	8		T150	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	2		T14	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T5	1		T40	1		T16	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T145	16		T146	1		T157	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T4	5		T42	1		T159	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T147	1		T86	14		T233	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T5	1		T110	1		T114	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T34	4		T114	12		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T2	24		T7	15		T12	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T8	1		T17	1		T176	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T9	1		T40	4		T145	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T4	9		T35	1		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T8	1		T230	14		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T14	3		T42	1		T35	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T9	1		T11	1		T146	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T9	1		T108	1		T142	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T142	15		T38	2		T249	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T13	19		T208	1		T150	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T110	1		T114	5		T142	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T14	1		T33	4		T146	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T83	1		T234	1		T23	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T152	9		T241	9		T218	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17050	1			T1	20		T3	15		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T44	3		T169	1		T90	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T40	9		T16	3		T174	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T146	4		T144	7		T231	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T144	5		T36	2		T168	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T147	14		T233	13		T231	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T110	3		T167	11		T168	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T34	2		T148	15		T152	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T12	12		T41	7		T43	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T176	10		T162	11		T171	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T9	4		T40	7		T143	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T174	11		T189	12		T168	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T147	9		T153	16		T164	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T35	3		T143	15		T186	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T9	9		T146	6		T147	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T9	20		T108	11		T150	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T142	19		T249	13		T239	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T13	7		T150	5		T177	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T110	12		T142	6		T144	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T33	1		T146	12		T108	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T23	3		T280	7		T204	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T152	7		T241	3		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T44	11		T189	13		T274	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T44	10		T90	2		T274	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T83	1		T241	2		T276	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T33	4		T112	13		T234	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T5	1		T40	1		T44	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T145	16		T44	3		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T4	5		T42	1		T159	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T157	1		T147	1		T169	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	1		T114	1		T144	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T34	4		T114	12		T86	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T43	4		T110	1		T88	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T8	1		T17	1		T176	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1374	1			T2	24		T7	15		T9	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T4	9		T35	1		T189	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T8	1		T230	14		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T14	3		T42	1		T35	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T9	1		T146	5		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T9	1		T108	1		T142	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	1		T142	15		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T208	1		T149	5		T162	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T110	1		T114	5		T142	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T13	19		T14	1		T146	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16970	1			T1	20		T3	15		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T280	7		T277	1		T278	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T33	1		T152	7		T241	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T40	9		T44	11		T174	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T44	10		T146	4		T144	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T16	3		T168	16		T250	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T147	14		T231	14		T247	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T144	5		T167	11		T36	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T34	2		T148	15		T233	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T43	23		T110	3		T37	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T176	10		T162	11		T249	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T9	4		T12	12		T40	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T189	12		T168	9		T171	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T147	9		T143	9		T152	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T35	3		T174	11		T186	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T9	9		T146	6		T147	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T9	20		T108	11		T143	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T142	19		T249	13		T239	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T162	13		T163	20		T177	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T110	12		T142	6		T144	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T13	7		T146	12		T108	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21887

1

T1

20

T2

24

T3

15

auto[1]

auto[0]

4303

1

T9

33

T12

12

T13

7