Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26190

1

T1

20

T2

24

T3

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22779

1

T1

20

T2

24

T3

15

auto[ADC_CTRL_FILTER_COND_OUT]

3411

1

T4

9

T8

2

T9

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20399

1

T1

20

T3

15

T6

20

auto[1]

5791

1

T2

24

T4

14

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22215

1

T1

20

T2

3

T3

15

auto[1]

3975

1

T2

21

T4

12

T7

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	8	1			T286	5		T287	3		-	-
values[0]	62	1			T288	1		T274	29		T289	10
values[1]	758	1			T5	1		T40	10		T145	16
values[2]	736	1			T4	5		T42	1		T157	1
values[3]	691	1			T5	1		T8	1		T159	15
values[4]	631	1			T43	10		T34	6		T110	4
values[5]	2912	1			T2	24		T4	9		T7	15
values[6]	745	1			T8	1		T9	5		T14	3
values[7]	890	1			T9	31		T42	1		T146	11
values[8]	693	1			T11	1		T142	34		T208	1
values[9]	1094	1			T13	26		T14	1		T33	5
minimum	16970	1			T1	20		T3	15		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	938	1			T4	5		T5	1		T40	10
values[1]	796	1			T42	1		T147	15		T159	15
values[2]	677	1			T5	1		T34	6		T110	4
values[3]	2831	1			T2	24		T7	15		T8	1
values[4]	734	1			T4	9		T9	5		T35	1
values[5]	918	1			T8	1		T14	3		T42	1
values[6]	718	1			T9	31		T11	1		T146	11
values[7]	636	1			T13	26		T142	34		T208	1
values[8]	792	1			T14	1		T33	5		T108	13
values[9]	166	1			T146	21		T83	1		T234	1
minimum	16984	1			T1	20		T3	15		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21887

1

T1

20

T2

24

T3

15

auto[1]

4303

1

T9

33

T12

12

T13

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T4	1		T5	1		T44	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T40	10		T145	1		T146	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T42	1		T159	1		T16	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T147	15		T233	14		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T5	1		T110	4		T114	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T34	4		T114	1		T148	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1602	1			T2	3		T7	2		T12	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T8	1		T17	1		T176	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T232	1		T150	17		T152	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T4	1		T9	5		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T42	1		T230	1		T147	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T8	1		T14	2		T143	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T9	10		T11	1		T146	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T9	21		T110	14		T35	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T142	20		T177	15		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T13	15		T208	1		T150	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T110	13		T114	1		T142	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T14	1		T33	5		T108	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T83	1		T189	11		T152	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T146	13		T234	1		T241	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16854	1			T1	20		T3	15		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T44	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T4	4		T44	13		T112	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T145	15		T144	14		T270	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T159	14		T16	3		T86	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T233	12		T220	13		T247	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T36	2		T241	15		T243	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T34	2		T114	11		T152	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	970	1			T2	21		T7	13		T30	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T264	7		T58	4		T21	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T150	17		T152	12		T177	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T4	8		T189	13		T19	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T230	13		T143	11		T152	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T14	1		T143	14		T164	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T146	4		T213	8		T163	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T35	1		T142	1		T149	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T142	14		T177	13		T239	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T13	11		T150	10		T283	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T114	4		T142	13		T144	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T112	12		T37	1		T235	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T189	9		T152	8		T23	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T146	8		T241	9		T273	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	2		T14	1		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T44	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T286	1		T287	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T274	16		T289	6		T290	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T288	1		T291	1		T292	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T5	1		T44	12		T87	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T40	10		T145	1		T44	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T4	1		T42	1		T16	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T157	1		T147	15		T114	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	1		T159	1		T114	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T8	1		T148	16		T233	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T43	10		T110	4		T88	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T34	4		T151	1		T176	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1635	1			T2	3		T7	2		T12	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T4	1		T35	1		T17	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T230	1		T147	10		T208	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T8	1		T9	5		T14	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T9	10		T42	1		T146	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T9	21		T110	14		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T11	1		T142	20		T163	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T208	1		T149	1		T162	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T110	13		T114	1		T83	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T13	15		T14	1		T33	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16853	1			T1	20		T3	15		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T286	4		T287	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T274	13		T289	4		T290	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T292	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T44	13		T189	5		T163	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T145	15		T44	2		T144	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T4	4		T16	3		T112	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T114	11		T220	13		T247	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T159	14		T86	13		T144	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T233	12		T152	23		T93	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T37	8		T241	15		T248	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T34	2		T209	12		T264	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1022	1			T2	21		T7	13		T30	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T4	8		T189	13		T19	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T230	13		T152	12		T238	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T14	1		T35	1		T164	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T146	4		T213	8		T152	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T142	1		T143	14		T150	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T142	14		T163	16		T177	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T149	4		T163	2		T238	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T114	4		T142	13		T144	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	11		T146	8		T112	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	2		T14	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T4	5		T5	1		T44	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T40	1		T145	16		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T42	1		T159	15		T16	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T147	1		T233	13		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	1		T110	1		T114	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T34	4		T114	12		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1317	1			T2	24		T7	15		T12	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T8	1		T17	1		T176	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T232	1		T150	18		T152	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T4	9		T9	1		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T42	1		T230	14		T147	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T8	1		T14	3		T143	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T9	1		T11	1		T146	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	1		T110	1		T35	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T142	15		T177	14		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T13	19		T208	1		T150	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T110	1		T114	5		T142	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T14	1		T33	4		T108	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T83	1		T189	10		T152	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T146	9		T234	1		T241	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16971	1			T1	20		T3	15		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T44	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T44	11		T174	14		T231	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T40	9		T146	4		T144	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T16	3		T144	5		T168	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T147	14		T233	13		T231	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T110	3		T36	2		T168	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T34	2		T148	15		T167	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1255	1			T12	12		T40	7		T41	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T176	10		T162	11		T171	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T150	16		T152	9		T177	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T9	4		T174	11		T189	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T147	21		T143	9		T153	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T143	15		T176	8		T177	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	9		T146	6		T108	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T9	20		T110	13		T35	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T142	19		T177	14		T249	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T13	7		T150	5		T220	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T110	12		T142	6		T144	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T33	1		T108	12		T235	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T189	10		T152	7		T23	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T146	12		T241	3		T293	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T44	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T286	5		T287	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T274	14		T289	5		T290	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T288	1		T291	1		T292	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T5	1		T44	14		T87	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T40	1		T145	16		T44	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T4	5		T42	1		T16	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T157	1		T147	1		T114	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	1		T159	15		T114	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T8	1		T148	1		T233	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T43	1		T110	1		T88	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T34	4		T151	1		T176	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1366	1			T2	24		T7	15		T12	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T4	9		T35	1		T17	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T230	14		T147	1		T208	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T8	1		T9	1		T14	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	1		T42	1		T146	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T9	1		T110	1		T142	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T11	1		T142	15		T163	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T208	1		T149	5		T162	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	358	1			T110	1		T114	5		T83	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T13	19		T14	1		T33	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16970	1			T1	20		T3	15		T6	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T274	15		T289	5		T290	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T44	11		T174	14		T189	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T40	9		T44	10		T146	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T16	3		T231	10		T168	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T147	14		T231	4		T247	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T144	5		T36	2		T168	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T148	15		T233	13		T167	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T43	9		T110	3		T37	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T34	2		T176	10		T162	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1291	1			T12	12		T40	7		T41	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T174	11		T189	12		T168	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T147	9		T152	9		T153	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T9	4		T35	3		T186	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T9	9		T146	6		T147	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T9	20		T110	13		T143	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T142	19		T163	14		T177	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T162	13		T163	6		T294	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T110	12		T142	6		T144	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T13	7		T33	1		T146	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21887

1

T1

20

T2

24

T3

15

auto[1]

auto[0]

4303

1

T9

33

T12

12

T13

7