Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26190

1

T1

20

T2

24

T3

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22649

1

T1

20

T2

24

T3

15

auto[ADC_CTRL_FILTER_COND_OUT]

3541

1

T4

9

T5

1

T13

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19842

1

T1

20

T3

15

T5

2

auto[1]

6348

1

T2

24

T4

14

T7

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22215

1

T1

20

T2

3

T3

15

auto[1]

3975

1

T2

21

T4

12

T7

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	413	1			T29	2		T46	4		T47	4
values[0]	53	1			T295	1		T296	1		T274	7
values[1]	767	1			T5	1		T8	1		T9	5
values[2]	2794	1			T2	24		T7	15		T12	14
values[3]	737	1			T40	11		T33	5		T110	14
values[4]	733	1			T8	1		T43	17		T16	10
values[5]	785	1			T14	3		T145	11		T43	10
values[6]	727	1			T4	9		T5	1		T9	21
values[7]	750	1			T4	5		T9	10		T146	21
values[8]	736	1			T114	5		T83	1		T208	1
values[9]	1138	1			T13	26		T230	14		T44	25
minimum	16557	1			T1	20		T3	15		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	948	1			T5	1		T8	1		T9	5
values[1]	2871	1			T2	24		T7	15		T12	14
values[2]	697	1			T8	1		T40	11		T43	17
values[3]	744	1			T145	11		T157	1		T110	13
values[4]	808	1			T4	9		T5	1		T9	21
values[5]	730	1			T44	13		T147	15		T112	11
values[6]	703	1			T4	5		T146	21		T159	15
values[7]	635	1			T9	10		T230	14		T114	5
values[8]	833	1			T13	26		T44	25		T108	13
values[9]	210	1			T114	12		T170	10		T297	1
minimum	17011	1			T1	20		T3	15		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21887

1

T1

20

T2

24

T3

15

auto[1]

4303

1

T9

33

T12

12

T13

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T5	1		T8	1		T9	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T14	1		T145	1		T42	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1593	1			T2	3		T7	2		T12	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T110	4		T114	1		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T8	1		T40	8		T33	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T43	15		T16	7		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T157	1		T110	13		T35	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T145	1		T174	12		T233	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T9	21		T14	2		T43	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T4	1		T5	1		T169	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T44	11		T174	15		T143	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T147	15		T112	1		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T4	1		T159	1		T208	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T146	13		T34	4		T86	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T9	10		T230	1		T114	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T83	1		T88	1		T150	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T44	12		T112	1		T88	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T13	15		T108	13		T213	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T170	10		T297	1		T235	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T114	1		T264	9		T96	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16856	1			T1	20		T3	15		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T146	7		T189	14		T107	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T163	2		T220	13		T264	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T145	15		T142	13		T152	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	974	1			T2	21		T7	13		T30	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T149	4		T189	9		T152	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T40	3		T35	1		T177	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T43	2		T16	3		T112	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T144	4		T167	10		T209	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T145	10		T233	12		T248	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T14	1		T143	11		T36	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T4	8		T152	15		T37	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T44	2		T143	14		T241	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T112	10		T142	1		T152	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T4	4		T159	14		T209	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T146	8		T34	2		T86	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T230	13		T114	4		T144	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T150	17		T163	14		T257	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T44	13		T112	5		T142	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T13	11		T213	8		T105	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T235	10		T298	13		T58	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T114	11		T264	7		T193	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	2		T14	1		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T146	4		T189	5		T107	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	413	1			T29	2		T46	4		T47	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T274	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T295	1		T296	1		T181	26
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T5	1		T8	1		T9	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T14	1		T145	1		T42	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1521	1			T2	3		T7	2		T12	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T147	23		T110	4		T114	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T40	8		T33	5		T110	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T112	1		T148	16		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T8	1		T108	12		T110	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T43	15		T16	7		T233	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T14	2		T43	10		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T145	1		T174	12		T169	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	21		T44	11		T174	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T4	1		T5	1		T147	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T4	1		T9	10		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T146	13		T34	4		T86	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T114	1		T208	1		T164	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T83	1		T231	11		T150	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	361	1			T230	1		T44	12		T112	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T13	15		T108	13		T114	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16440	1			T1	20		T3	15		T6	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T274	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T181	14		T107	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T163	2		T220	13		T264	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T145	15		T146	4		T142	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	929	1			T2	21		T7	13		T30	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T189	9		T240	18		T39	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T40	3		T35	1		T177	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T112	12		T149	4		T150	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T143	11		T144	4		T167	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T43	2		T16	3		T233	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T14	1		T209	12		T241	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T145	10		T37	8		T186	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T44	2		T143	14		T36	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T4	8		T112	10		T142	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T4	4		T159	14		T209	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T146	8		T34	2		T86	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T114	4		T235	16		T97	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T150	17		T163	14		T257	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T230	13		T44	13		T112	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T13	11		T114	11		T213	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	2		T14	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T5	1		T8	1		T9	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T14	1		T145	16		T42	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T2	24		T7	15		T12	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T110	1		T114	1		T149	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T8	1		T40	4		T33	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T43	3		T16	7		T112	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T157	1		T110	1		T35	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T145	11		T174	1		T233	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T9	1		T14	3		T43	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T4	9		T5	1		T169	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T44	3		T174	1		T143	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T147	1		T112	11		T142	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T4	5		T159	15		T208	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T146	9		T34	4		T86	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T9	1		T230	14		T114	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T83	1		T88	1		T150	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T44	14		T112	6		T88	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	19		T108	1		T213	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T170	1		T297	1		T235	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T114	12		T264	8		T96	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16971	1			T1	20		T3	15		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T146	5		T189	6		T107	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T9	4		T163	6		T250	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T147	21		T142	6		T231	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1257	1			T12	12		T40	9		T41	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T110	3		T189	10		T152	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T40	7		T33	1		T108	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T43	14		T16	3		T148	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T110	12		T144	12		T167	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T174	11		T233	13		T168	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T9	20		T43	9		T143	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T168	13		T37	3		T186	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T44	10		T174	14		T143	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T147	14		T167	11		T152	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T165	6		T22	2		T299	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T146	12		T34	2		T231	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T9	9		T144	5		T243	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T150	16		T163	12		T94	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T44	11		T142	19		T144	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T13	7		T108	12		T213	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T170	9		T235	11		T58	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T264	8		T96	4		T300	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T301	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T146	6		T189	13		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	413	1			T29	2		T46	4		T47	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T274	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T295	1		T296	1		T181	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T5	1		T8	1		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T14	1		T145	16		T42	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1250	1			T2	24		T7	15		T12	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T147	2		T110	1		T114	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T40	4		T33	4		T110	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T112	13		T148	1		T149	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T8	1		T108	1		T110	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T43	3		T16	7		T233	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T14	3		T43	1		T157	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T145	11		T174	1		T169	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T9	1		T44	3		T174	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T4	9		T5	1		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T4	5		T9	1		T159	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T146	9		T34	4		T86	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T114	5		T208	1		T164	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T83	1		T231	1		T150	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	357	1			T230	14		T44	14		T112	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T13	19		T108	1		T114	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16557	1			T1	20		T3	15		T6	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T274	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T181	25		T107	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T9	4		T40	9		T163	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T146	6		T142	6		T189	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1200	1			T12	12		T41	7		T146	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T147	21		T110	3		T231	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T40	7		T33	1		T110	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T148	15		T150	5		T189	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T108	11		T110	12		T143	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T43	14		T16	3		T233	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T43	9		T168	16		T241	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T174	11		T168	13		T37	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T9	20		T44	10		T174	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T147	14		T167	11		T152	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T9	9		T162	13		T165	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T146	12		T34	2		T162	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T97	15		T302	11		T299	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T231	10		T150	16		T163	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T44	11		T142	19		T144	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T13	7		T108	12		T213	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21887

1

T1

20

T2

24

T3

15

auto[1]

auto[0]

4303

1

T9

33

T12

12

T13

7