Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26190

1

T1

20

T2

24

T3

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22453

1

T1

20

T2

24

T3

15

auto[ADC_CTRL_FILTER_COND_OUT]

3737

1

T4

9

T5

1

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19897

1

T1

20

T3

15

T4

14

auto[1]

6293

1

T2

24

T5

1

T7

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22215

1

T1

20

T2

3

T3

15

auto[1]

3975

1

T2

21

T4

12

T7

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	32	1			T303	11		T304	21		-	-
values[0]	34	1			T112	13		T204	20		T305	1
values[1]	590	1			T5	1		T42	1		T157	1
values[2]	760	1			T4	5		T40	11		T44	13
values[3]	684	1			T44	25		T146	21		T142	2
values[4]	659	1			T4	9		T9	31		T34	6
values[5]	707	1			T145	11		T17	1		T208	1
values[6]	695	1			T14	1		T40	10		T42	1
values[7]	586	1			T8	1		T11	1		T13	26
values[8]	681	1			T5	1		T9	5		T43	10
values[9]	3792	1			T2	24		T7	15		T8	1
minimum	16970	1			T1	20		T3	15		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	707	1			T5	1		T42	1		T157	1
values[1]	886	1			T40	11		T44	25		T147	15
values[2]	720	1			T4	14		T44	13		T146	21
values[3]	631	1			T9	31		T145	11		T34	6
values[4]	664	1			T169	1		T144	22		T234	1
values[5]	597	1			T8	1		T11	1		T14	1
values[6]	2798	1			T2	24		T7	15		T12	14
values[7]	831	1			T5	1		T8	1		T9	5
values[8]	1165	1			T14	3		T145	16		T33	5
values[9]	215	1			T43	17		T143	21		T176	11
minimum	16976	1			T1	20		T3	15		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21887

1

T1

20

T2

24

T3

15

auto[1]

4303

1

T9

33

T12

12

T13

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T42	1		T114	1		T35	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T5	1		T157	1		T147	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T40	8		T86	1		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T44	12		T147	15		T112	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T4	1		T146	13		T16	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T4	1		T44	11		T232	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T112	1		T232	1		T208	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T9	31		T145	1		T34	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T169	1		T234	1		T189	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T144	8		T152	1		T176	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T11	1		T14	1		T40	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T8	1		T87	1		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1480	1			T2	3		T7	2		T12	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T42	1		T110	14		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	1		T8	1		T9	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T230	1		T147	13		T142	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T14	2		T145	1		T88	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	367	1			T33	5		T108	12		T114	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T43	15		T143	10		T209	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T176	11		T38	1		T294	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16854	1			T1	20		T3	15		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T306	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T35	1		T213	8		T240	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T159	14		T112	12		T152	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T40	3		T86	13		T142	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T44	13		T112	5		T189	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T4	4		T146	8		T16	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T4	8		T44	2		T150	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T112	10		T167	10		T37	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T145	10		T34	2		T189	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T189	9		T163	14		T92	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T144	14		T152	15		T255	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T152	12		T239	7		T39	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T264	12		T307	1		T210	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	954	1			T2	21		T7	13		T13	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T238	1		T240	10		T18	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T142	13		T233	12		T238	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T230	13		T142	14		T143	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T14	1		T145	15		T255	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T114	11		T150	8		T152	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T43	2		T143	11		T209	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T274	4		T308	4		T309	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	2		T14	1		T33	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T303	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T304	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T305	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T112	1		T204	18		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T42	1		T114	1		T213	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T5	1		T157	1		T147	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T4	1		T40	8		T16	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T44	11		T147	15		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T146	13		T142	1		T150	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T44	12		T169	1		T231	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T108	13		T112	1		T232	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T4	1		T9	31		T34	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T208	1		T234	1		T189	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T145	1		T17	1		T174	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T14	1		T40	10		T146	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T42	1		T87	1		T35	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T11	1		T13	15		T242	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T8	1		T230	1		T110	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	1		T9	5		T43	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T147	13		T114	1		T143	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1784	1			T2	3		T7	2		T8	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	533	1			T33	5		T108	12		T83	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16853	1			T1	20		T3	15		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T303	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T304	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T112	12		T204	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T213	8		T240	18		T220	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T159	14		T235	16		T257	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T4	4		T40	3		T16	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T44	2		T112	5		T189	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T146	8		T142	1		T150	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T44	13		T164	12		T177	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T112	10		T149	4		T37	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T4	8		T34	2		T150	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T189	9		T167	10		T163	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T145	10		T144	14		T255	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T146	4		T114	4		T152	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T152	15		T264	12		T307	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T13	11		T242	3		T210	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T230	13		T238	1		T240	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T142	13		T233	12		T238	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T114	11		T143	14		T144	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1132	1			T2	21		T7	13		T14	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T142	14		T150	8		T152	23
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	2		T14	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T42	1		T114	1		T35	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	1		T157	1		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T40	4		T86	14		T142	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T44	14		T147	1		T112	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T4	5		T146	9		T16	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T4	9		T44	3		T232	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T112	11		T232	1		T208	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T9	2		T145	11		T34	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T169	1		T234	1		T189	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T144	15		T152	16		T176	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T11	1		T14	1		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T8	1		T87	1		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T2	24		T7	15		T12	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T42	1		T110	1		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	1		T8	1		T9	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T230	14		T147	1		T142	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T14	3		T145	16		T88	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T33	4		T108	1		T114	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T43	3		T143	12		T209	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T176	1		T38	1		T294	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16971	1			T1	20		T3	15		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T306	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T35	3		T213	9		T168	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T147	9		T152	7		T168	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T40	7		T162	13		T177	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T44	11		T147	14		T189	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T146	12		T16	3		T108	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T44	10		T231	10		T150	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T167	11		T171	3		T58	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T9	29		T34	2		T174	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T189	10		T163	12		T168	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T144	7		T176	8		T255	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T40	9		T146	4		T148	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T231	4		T249	8		T264	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1148	1			T12	12		T13	7		T41	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T110	13		T249	8		T18	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T9	4		T43	9		T110	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T147	12		T142	19		T143	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T162	11		T220	2		T255	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T33	1		T108	11		T150	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T43	14		T143	9		T190	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T176	10		T294	2		T274	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T306	4		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T303	11		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T304	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T305	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T112	13		T204	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T42	1		T114	1		T213	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	1		T157	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T4	5		T40	4		T16	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T44	3		T147	1		T112	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T146	9		T142	2		T150	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T44	14		T169	1		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T108	1		T112	11		T232	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T4	9		T9	2		T34	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T208	1		T234	1		T189	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T145	11		T17	1		T174	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T14	1		T40	1		T146	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T42	1		T87	1		T35	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T11	1		T13	19		T242	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T8	1		T230	14		T110	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T5	1		T9	1		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T147	1		T114	12		T143	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1508	1			T2	24		T7	15		T8	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	425	1			T33	4		T108	1		T83	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16970	1			T1	20		T3	15		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T304	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T204	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T213	9		T170	9		T94	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T147	9		T168	16		T249	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T40	7		T16	3		T35	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T44	10		T147	14		T189	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T146	12		T150	16		T162	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T44	11		T231	10		T177	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T108	12		T90	2		T92	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T9	29		T34	2		T150	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T189	10		T167	11		T163	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T174	11		T144	7		T255	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T40	9		T146	10		T148	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T249	8		T264	12		T307	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T13	7		T103	2		T310	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T110	13		T231	4		T249	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T9	4		T43	9		T110	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T147	12		T143	15		T144	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1408	1			T12	12		T41	7		T43	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	451	1			T33	1		T108	11		T142	19

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21887

1

T1

20

T2

24

T3

15

auto[1]

auto[0]

4303

1

T9

33

T12

12

T13

7