Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26190

1

T1

20

T2

24

T3

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22576

1

T1

20

T2

24

T3

15

auto[ADC_CTRL_FILTER_COND_OUT]

3614

1

T4

9

T5

2

T8

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20241

1

T1

20

T3

15

T4

14

auto[1]

5949

1

T2

24

T5

1

T7

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22215

1

T1

20

T2

3

T3

15

auto[1]

3975

1

T2

21

T4

12

T7

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	194	1			T44	25		T86	14		T87	1
values[0]	25	1			T228	16		T251	6		T287	3
values[1]	850	1			T4	5		T44	13		T146	11
values[2]	716	1			T9	10		T40	10		T146	5
values[3]	685	1			T40	11		T145	16		T43	17
values[4]	2953	1			T2	24		T7	15		T12	14
values[5]	764	1			T4	9		T9	26		T13	26
values[6]	664	1			T11	1		T157	1		T16	10
values[7]	733	1			T5	2		T42	1		T147	15
values[8]	730	1			T14	3		T145	11		T146	21
values[9]	906	1			T8	2		T42	1		T43	10
minimum	16970	1			T1	20		T3	15		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	916	1			T4	5		T9	10		T44	13
values[1]	652	1			T40	10		T145	16		T43	17
values[2]	677	1			T40	11		T230	14		T114	6
values[3]	3021	1			T2	24		T4	9		T7	15
values[4]	716	1			T9	26		T157	1		T16	10
values[5]	598	1			T5	1		T11	1		T83	1
values[6]	848	1			T5	1		T42	1		T147	15
values[7]	615	1			T8	1		T14	3		T145	11
values[8]	941	1			T8	1		T42	1		T43	10
values[9]	59	1			T44	25		T235	22		T311	1
minimum	17147	1			T1	20		T3	15		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21887

1

T1

20

T2

24

T3

15

auto[1]

4303

1

T9

33

T12

12

T13

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T4	1		T9	10		T44	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T146	7		T110	14		T232	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T145	1		T108	12		T143	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T40	10		T43	15		T146	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T40	8		T142	20		T233	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T230	1		T114	2		T174	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1576	1			T2	3		T7	2		T12	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T4	1		T147	13		T112	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T144	8		T234	1		T209	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T9	26		T157	1		T16	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	1		T83	1		T144	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	1		T174	15		T234	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T42	1		T147	15		T142	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T5	1		T112	1		T88	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T34	4		T35	8		T17	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T8	1		T14	2		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T42	1		T114	1		T87	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T8	1		T43	10		T86	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T235	12		T236	9		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T44	12		T311	1		T312	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16894	1			T1	20		T3	15		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T105	13		T270	1		T307	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T4	4		T44	2		T150	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T146	4		T177	9		T238	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T145	15		T143	11		T163	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T43	2		T159	14		T239	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T40	3		T142	14		T233	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T230	13		T114	4		T152	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	914	1			T2	21		T7	13		T13	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T4	8		T112	12		T167	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T144	14		T209	8		T39	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T16	3		T149	4		T143	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T144	4		T37	8		T241	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T152	12		T164	15		T241	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T142	13		T213	8		T240	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T112	10		T150	17		T189	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T34	2		T35	1		T242	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T14	1		T145	10		T146	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T114	11		T142	1		T150	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T86	13		T243	12		T166	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T235	10		T236	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T44	13		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T13	2		T14	1		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T105	13		T270	5		T307	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T87	1		T232	1		T151	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T44	12		T86	1		T311	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T228	1		T251	4		T287	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T4	1		T44	11		T112	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T146	7		T110	14		T232	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T9	10		T108	25		T143	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T40	10		T146	5		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T40	8		T145	1		T142	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T43	15		T114	2		T174	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1612	1			T2	3		T7	2		T12	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T230	1		T112	1		T167	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T13	15		T234	1		T176	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T4	1		T9	26		T147	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	1		T83	1		T144	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T157	1		T16	7		T110	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T42	1		T147	15		T142	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T5	2		T234	1		T189	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T34	4		T35	8		T17	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T14	2		T145	1		T146	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T42	1		T114	1		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T8	2		T43	10		T33	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16853	1			T1	20		T3	15		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T235	10		T313	12		T314	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T44	13		T86	13		T229	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T228	15		T251	2		T287	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T4	4		T44	2		T112	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T146	4		T177	9		T97	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T143	11		T163	2		T164	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T159	14		T238	6		T239	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T40	3		T145	15		T142	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T43	2		T114	4		T152	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	903	1			T2	21		T7	13		T30	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T230	13		T112	12		T167	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T13	11		T177	4		T209	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T4	8		T149	4		T143	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T144	14		T37	8		T241	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T16	3		T152	12		T164	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T142	13		T213	8		T144	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T189	5		T152	23		T238	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T34	2		T35	1		T242	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T14	1		T145	10		T146	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T114	11		T142	1		T150	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T243	12		T166	4		T315	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	2		T14	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T4	5		T9	1		T44	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T146	5		T110	1		T232	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T145	16		T108	1		T143	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T40	1		T43	3		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T40	4		T142	15		T233	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T230	14		T114	6		T174	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1249	1			T2	24		T7	15		T12	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T4	9		T147	1		T112	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T144	15		T234	1		T209	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T9	2		T157	1		T16	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	1		T83	1		T144	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	1		T174	1		T234	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T42	1		T147	1		T142	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T5	1		T112	11		T88	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T34	4		T35	6		T17	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T8	1		T14	3		T145	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T42	1		T114	12		T87	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T8	1		T43	1		T86	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T235	11		T236	8		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T44	14		T311	1		T312	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17054	1			T1	20		T3	15		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T105	14		T270	6		T307	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T9	9		T44	10		T108	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T146	6		T110	13		T177	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T108	11		T143	9		T153	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T40	9		T43	14		T146	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T40	7		T142	19		T233	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T174	11		T152	7		T162	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1241	1			T12	12		T13	7		T41	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T147	12		T167	11		T163	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T144	7		T220	2		T92	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T9	24		T16	3		T110	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T144	5		T167	11		T37	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T174	14		T152	9		T162	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T147	14		T142	6		T213	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T150	16		T189	13		T152	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T34	2		T35	3		T105	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T33	1		T146	12		T147	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T150	12		T249	8		T93	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T43	9		T231	4		T250	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T235	11		T236	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T44	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T245	14		T251	3		T316	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T105	12		T307	1		T289	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T87	1		T232	1		T151	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T44	14		T86	14		T311	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T228	16		T251	3		T287	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T4	5		T44	3		T112	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T146	5		T110	1		T232	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T9	1		T108	2		T143	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T40	1		T146	1		T159	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T40	4		T145	16		T142	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T43	3		T114	6		T174	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1236	1			T2	24		T7	15		T12	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T230	14		T112	13		T167	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T13	19		T234	1		T176	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T4	9		T9	2		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T11	1		T83	1		T144	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T157	1		T16	7		T110	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T42	1		T147	1		T142	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	2		T234	1		T189	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T34	4		T35	6		T17	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T14	3		T145	11		T146	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T42	1		T114	12		T142	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T8	2		T43	1		T33	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16970	1			T1	20		T3	15		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T235	11		T313	14		T280	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T44	11		T301	2		T229	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T251	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T44	10		T150	5		T189	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T146	6		T110	13		T177	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T9	9		T108	23		T143	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T40	9		T146	4		T148	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T40	7		T142	19		T233	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T43	14		T174	11		T152	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1279	1			T12	12		T41	7		T160	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T167	11		T163	14		T250	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T13	7		T176	10		T177	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T9	24		T147	12		T143	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T144	7		T167	11		T37	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T16	3		T110	3		T174	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T147	14		T142	6		T213	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T189	13		T152	19		T162	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T34	2		T35	3		T105	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T146	12		T147	9		T150	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T150	12		T249	8		T93	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T43	9		T33	1		T231	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21887

1

T1

20

T2

24

T3

15

auto[1]

auto[0]

4303

1

T9

33

T12

12

T13

7