Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26190

1

T1

20

T2

24

T3

15

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20476

1

T1

20

T3

15

T4

14

auto[ADC_CTRL_FILTER_COND_OUT]

5714

1

T2

24

T5

1

T7

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20080

1

T1

20

T3

15

T4

14

auto[1]

6110

1

T2

24

T5

1

T7

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22215

1

T1

20

T2

3

T3

15

auto[1]

3975

1

T2

21

T4

12

T7

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	219	1			T43	10		T159	15		T35	1
values[0]	27	1			T317	22		T260	1		T269	4
values[1]	765	1			T14	3		T40	10		T230	14
values[2]	674	1			T5	1		T8	1		T110	13
values[3]	739	1			T9	5		T40	11		T16	10
values[4]	580	1			T44	13		T108	13		T114	1
values[5]	798	1			T9	10		T11	1		T13	26
values[6]	522	1			T145	27		T147	13		T110	14
values[7]	845	1			T42	1		T146	21		T112	11
values[8]	691	1			T4	5		T42	1		T146	5
values[9]	3360	1			T2	24		T4	9		T5	1
minimum	16970	1			T1	20		T3	15		T6	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	724	1			T14	3		T40	10		T33	5
values[1]	2930	1			T2	24		T5	1		T7	15
values[2]	621	1			T9	5		T40	11		T114	18
values[3]	659	1			T44	13		T108	13		T110	4
values[4]	804	1			T9	10		T11	1		T13	26
values[5]	488	1			T145	16		T42	1		T110	14
values[6]	811	1			T4	5		T146	21		T112	11
values[7]	801	1			T42	1		T146	5		T147	10
values[8]	1001	1			T4	9		T5	1		T8	1
values[9]	162	1			T159	15		T151	1		T176	9
minimum	17189	1			T1	20		T3	15		T6	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21887

1

T1

20

T2

24

T3

15

auto[1]

4303

1

T9

33

T12

12

T13

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T14	2		T33	5		T108	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T40	10		T149	1		T152	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T5	1		T8	1		T88	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1577	1			T2	3		T7	2		T12	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T9	5		T114	1		T35	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T40	8		T114	2		T150	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T44	11		T108	13		T110	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T231	11		T163	15		T177	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T13	15		T44	12		T147	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T9	10		T11	1		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T145	1		T88	2		T152	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T42	1		T110	14		T232	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T4	1		T146	13		T112	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T213	10		T233	14		T234	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T42	1		T189	13		T153	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T146	5		T147	10		T112	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	357	1			T4	1		T9	21		T146	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T5	1		T8	1		T43	25
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T159	1		T92	8		T252	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T151	1		T176	9		T235	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16869	1			T1	20		T3	15		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T230	1		T34	4		T297	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T14	1		T86	13		T142	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T149	4		T152	8		T239	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T144	14		T152	23		T163	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	970	1			T2	21		T7	13		T30	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T35	1		T143	11		T144	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T40	3		T114	15		T150	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T44	2		T164	12		T37	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T163	16		T177	13		T166	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T13	11		T44	13		T248	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T145	10		T112	5		T142	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T145	15		T152	12		T240	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T255	13		T58	4		T256	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T4	4		T146	8		T112	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T213	8		T233	12		T209	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T189	13		T177	9		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T112	12		T167	10		T186	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T4	8		T146	4		T142	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T43	2		T189	9		T257	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T159	14		T92	7		T252	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T235	10		T318	11		T319	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T13	2		T14	1		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T230	13		T34	2		T243	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T159	1		T252	1		T268	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T43	10		T35	1		T189	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T317	10		T260	1		T269	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T14	2		T33	5		T108	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T40	10		T230	1		T34	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T5	1		T8	1		T110	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T231	5		T189	14		T175	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T9	5		T35	8		T208	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T40	8		T16	7		T114	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T44	11		T108	13		T114	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T231	11		T163	15		T103	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T13	15		T44	12		T110	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T9	10		T11	1		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T145	1		T147	13		T88	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T145	1		T110	14		T112	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T146	13		T112	1		T174	27
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T42	1		T213	10		T234	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T4	1		T42	1		T189	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T146	5		T147	10		T112	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	399	1			T4	1		T9	21		T146	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1655	1			T2	3		T5	1		T7	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16853	1			T1	20		T3	15		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T159	14		T252	16		T320	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T189	9		T321	12		T322	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T317	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T14	1		T142	13		T143	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T230	13		T34	2		T149	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T86	13		T144	14		T163	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T189	5		T152	8		T263	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T35	1		T144	4		T152	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T40	3		T16	3		T114	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T44	2		T143	11		T164	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T163	16		T166	7		T22	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	11		T44	13		T264	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T142	14		T150	10		T177	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T145	15		T241	1		T248	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T145	10		T112	5		T177	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T146	8		T112	10		T152	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T213	8		T209	8		T241	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T4	4		T189	13		T177	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T112	12		T233	12		T186	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T4	8		T146	4		T142	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	964	1			T2	21		T7	13		T30	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	2		T14	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T14	3		T33	4		T108	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T40	1		T149	5		T152	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T5	1		T8	1		T88	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1301	1			T2	24		T7	15		T12	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	1		T114	1		T35	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T40	4		T114	17		T150	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T44	3		T108	1		T110	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T231	1		T163	17		T177	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T13	19		T44	14		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T9	1		T11	1		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T145	16		T88	2		T152	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T42	1		T110	1		T232	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	5		T146	9		T112	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T213	9		T233	13		T234	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T42	1		T189	14		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T146	1		T147	1		T112	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	357	1			T4	9		T9	1		T146	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	1		T8	1		T43	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T159	15		T92	8		T252	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T151	1		T176	1		T235	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17004	1			T1	20		T3	15		T6	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T230	14		T34	4		T297	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T33	1		T108	11		T110	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T40	9		T152	7		T93	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T144	7		T152	19		T162	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1246	1			T12	12		T41	7		T160	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	4		T35	3		T143	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T40	7		T150	12		T167	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T44	10		T108	12		T110	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T231	10		T163	14		T177	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T13	7		T44	11		T147	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T9	9		T142	19		T150	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T152	9		T239	8		T220	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T110	13		T249	8		T255	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T146	12		T174	25		T162	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T213	9		T233	13		T241	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T189	12		T153	16		T177	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T146	4		T147	9		T167	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T9	20		T146	6		T144	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T43	23		T147	14		T148	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T92	7		T267	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T176	8		T235	11		T268	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T317	9		T269	3		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T34	2		T243	12		T97	19

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T159	15		T252	17		T268	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T43	1		T35	1		T189	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T317	13		T260	1		T269	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T14	3		T33	4		T108	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T40	1		T230	14		T34	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T5	1		T8	1		T110	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T231	1		T189	6		T175	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T9	1		T35	6		T208	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T40	4		T16	7		T114	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T44	3		T108	1		T114	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T231	1		T163	17		T103	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T13	19		T44	14		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T9	1		T11	1		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T145	16		T147	1		T88	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T145	11		T110	1		T112	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T146	9		T112	11		T174	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T42	1		T213	9		T234	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T4	5		T42	1		T189	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T146	1		T147	1		T112	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	414	1			T4	9		T9	1		T146	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1303	1			T2	24		T5	1		T7	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16970	1			T1	20		T3	15		T6	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T268	2		T320	3		T323	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T43	9		T189	10		T176	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T317	9		T269	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T33	1		T108	11		T142	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T40	9		T34	2		T243	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T110	12		T144	7		T162	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T231	4		T189	13		T152	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T9	4		T35	3		T144	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T40	7		T16	3		T150	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T44	10		T108	12		T143	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T231	10		T163	14		T103	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T13	7		T44	11		T110	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T9	9		T142	19		T150	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T147	12		T248	6		T324	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T110	13		T177	2		T249	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T146	12		T174	25		T152	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T213	9		T241	17		T255	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T189	12		T177	10		T315	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T146	4		T147	9		T233	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T9	20		T146	6		T144	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1316	1			T12	12		T41	7		T43	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21887

1

T1

20

T2

24

T3

15

auto[1]

auto[0]

4303

1

T9

33

T12

12

T13

7