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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.72 99.07 96.67 100.00 100.00 98.83 98.33 91.17


Total test records in report: 920
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T799 /workspace/coverage/default/20.adc_ctrl_alert_test.2347662915 Jun 27 07:07:45 PM PDT 24 Jun 27 07:07:48 PM PDT 24 499789802 ps
T800 /workspace/coverage/default/10.adc_ctrl_clock_gating.1985377964 Jun 27 07:06:57 PM PDT 24 Jun 27 07:08:31 PM PDT 24 443667535974 ps
T801 /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3389267829 Jun 27 07:09:28 PM PDT 24 Jun 27 07:10:30 PM PDT 24 28379173261 ps
T330 /workspace/coverage/default/29.adc_ctrl_clock_gating.1760337702 Jun 27 07:09:02 PM PDT 24 Jun 27 07:13:37 PM PDT 24 505693546034 ps
T802 /workspace/coverage/default/25.adc_ctrl_filters_polled.4135461151 Jun 27 07:08:18 PM PDT 24 Jun 27 07:20:29 PM PDT 24 339639137752 ps
T51 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.194777782 Jun 27 06:33:39 PM PDT 24 Jun 27 06:34:12 PM PDT 24 26584866329 ps
T59 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.255205691 Jun 27 06:33:32 PM PDT 24 Jun 27 06:33:35 PM PDT 24 558794795 ps
T803 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2852518112 Jun 27 06:34:04 PM PDT 24 Jun 27 06:34:07 PM PDT 24 366653211 ps
T132 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3883517631 Jun 27 06:33:38 PM PDT 24 Jun 27 06:33:43 PM PDT 24 364206552 ps
T804 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1429699401 Jun 27 06:33:40 PM PDT 24 Jun 27 06:33:45 PM PDT 24 555005492 ps
T805 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.800270183 Jun 27 06:34:16 PM PDT 24 Jun 27 06:34:19 PM PDT 24 417814046 ps
T60 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2097444342 Jun 27 06:33:45 PM PDT 24 Jun 27 06:33:50 PM PDT 24 532216743 ps
T66 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3624772250 Jun 27 06:33:38 PM PDT 24 Jun 27 06:33:43 PM PDT 24 293551189 ps
T138 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2730010171 Jun 27 06:33:42 PM PDT 24 Jun 27 06:33:49 PM PDT 24 830436996 ps
T806 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.499020272 Jun 27 06:34:17 PM PDT 24 Jun 27 06:34:18 PM PDT 24 552591889 ps
T75 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.917237966 Jun 27 06:33:46 PM PDT 24 Jun 27 06:33:50 PM PDT 24 398540813 ps
T807 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.405193781 Jun 27 06:33:44 PM PDT 24 Jun 27 06:33:49 PM PDT 24 419194387 ps
T68 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1402829218 Jun 27 06:33:42 PM PDT 24 Jun 27 06:33:49 PM PDT 24 583950145 ps
T808 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2993202816 Jun 27 06:34:06 PM PDT 24 Jun 27 06:34:10 PM PDT 24 471142599 ps
T809 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4245253147 Jun 27 06:34:22 PM PDT 24 Jun 27 06:34:30 PM PDT 24 305563569 ps
T55 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.4074048533 Jun 27 06:34:05 PM PDT 24 Jun 27 06:34:20 PM PDT 24 4268927314 ps
T73 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3492762876 Jun 27 06:33:46 PM PDT 24 Jun 27 06:33:51 PM PDT 24 546522470 ps
T56 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3690486615 Jun 27 06:34:02 PM PDT 24 Jun 27 06:34:08 PM PDT 24 10112196311 ps
T52 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3626216054 Jun 27 06:33:44 PM PDT 24 Jun 27 06:33:50 PM PDT 24 2677648914 ps
T139 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3148320498 Jun 27 06:34:02 PM PDT 24 Jun 27 06:34:04 PM PDT 24 624936185 ps
T67 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.722731431 Jun 27 06:33:46 PM PDT 24 Jun 27 06:33:52 PM PDT 24 587537686 ps
T117 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.4268436654 Jun 27 06:33:38 PM PDT 24 Jun 27 06:33:46 PM PDT 24 965307499 ps
T69 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.139617793 Jun 27 06:33:40 PM PDT 24 Jun 27 06:33:47 PM PDT 24 616958164 ps
T140 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3886474386 Jun 27 06:33:46 PM PDT 24 Jun 27 06:33:51 PM PDT 24 743986478 ps
T810 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2915947692 Jun 27 06:34:23 PM PDT 24 Jun 27 06:34:31 PM PDT 24 306329108 ps
T811 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.942935281 Jun 27 06:33:37 PM PDT 24 Jun 27 06:33:41 PM PDT 24 344440445 ps
T57 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1222707952 Jun 27 06:33:46 PM PDT 24 Jun 27 06:34:01 PM PDT 24 4209558276 ps
T61 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2579650128 Jun 27 06:34:03 PM PDT 24 Jun 27 06:34:08 PM PDT 24 4794961248 ps
T54 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2715522603 Jun 27 06:34:04 PM PDT 24 Jun 27 06:34:08 PM PDT 24 2629314562 ps
T62 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2253901734 Jun 27 06:33:37 PM PDT 24 Jun 27 06:33:51 PM PDT 24 4170134114 ps
T118 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2343956443 Jun 27 06:33:44 PM PDT 24 Jun 27 06:33:49 PM PDT 24 422187748 ps
T141 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3254808454 Jun 27 06:33:44 PM PDT 24 Jun 27 06:33:49 PM PDT 24 434501320 ps
T76 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2427969653 Jun 27 06:34:07 PM PDT 24 Jun 27 06:34:17 PM PDT 24 8944867876 ps
T53 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2246695051 Jun 27 06:34:05 PM PDT 24 Jun 27 06:34:10 PM PDT 24 2694798471 ps
T74 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3749189662 Jun 27 06:34:02 PM PDT 24 Jun 27 06:34:07 PM PDT 24 419057559 ps
T133 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2965743721 Jun 27 06:33:40 PM PDT 24 Jun 27 06:33:51 PM PDT 24 4932574294 ps
T812 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1273642579 Jun 27 06:33:39 PM PDT 24 Jun 27 06:33:45 PM PDT 24 568366423 ps
T134 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.4243623192 Jun 27 06:34:04 PM PDT 24 Jun 27 06:34:08 PM PDT 24 679762476 ps
T119 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3088995317 Jun 27 06:33:46 PM PDT 24 Jun 27 06:33:51 PM PDT 24 448563079 ps
T135 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1862459396 Jun 27 06:33:36 PM PDT 24 Jun 27 06:33:40 PM PDT 24 438525980 ps
T813 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.4153401560 Jun 27 06:34:04 PM PDT 24 Jun 27 06:34:10 PM PDT 24 574357623 ps
T814 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.938602823 Jun 27 06:33:38 PM PDT 24 Jun 27 06:33:46 PM PDT 24 4314811391 ps
T815 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2358946273 Jun 27 06:34:06 PM PDT 24 Jun 27 06:34:10 PM PDT 24 448215133 ps
T120 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4106468075 Jun 27 06:33:43 PM PDT 24 Jun 27 06:33:49 PM PDT 24 385466696 ps
T816 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.4164793017 Jun 27 06:34:22 PM PDT 24 Jun 27 06:34:32 PM PDT 24 502529459 ps
T817 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2161476813 Jun 27 06:33:39 PM PDT 24 Jun 27 06:33:55 PM PDT 24 4173275346 ps
T77 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.180473977 Jun 27 06:34:06 PM PDT 24 Jun 27 06:34:21 PM PDT 24 8508488777 ps
T818 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1848246179 Jun 27 06:33:39 PM PDT 24 Jun 27 06:33:43 PM PDT 24 353140606 ps
T819 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.285728465 Jun 27 06:34:22 PM PDT 24 Jun 27 06:34:30 PM PDT 24 500837307 ps
T121 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3505294671 Jun 27 06:34:04 PM PDT 24 Jun 27 06:34:08 PM PDT 24 398646529 ps
T820 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.112489068 Jun 27 06:34:18 PM PDT 24 Jun 27 06:34:21 PM PDT 24 431771600 ps
T821 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2203992490 Jun 27 06:34:04 PM PDT 24 Jun 27 06:34:08 PM PDT 24 573784755 ps
T822 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2830515241 Jun 27 06:33:45 PM PDT 24 Jun 27 06:33:50 PM PDT 24 535176657 ps
T823 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.4288198018 Jun 27 06:33:46 PM PDT 24 Jun 27 06:33:50 PM PDT 24 421020206 ps
T824 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2859110104 Jun 27 06:33:37 PM PDT 24 Jun 27 06:33:41 PM PDT 24 300228049 ps
T136 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3508333777 Jun 27 06:33:39 PM PDT 24 Jun 27 06:33:45 PM PDT 24 317600914 ps
T825 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3976964167 Jun 27 06:34:21 PM PDT 24 Jun 27 06:34:28 PM PDT 24 457405139 ps
T122 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1890497824 Jun 27 06:33:43 PM PDT 24 Jun 27 06:34:19 PM PDT 24 45513007108 ps
T137 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3491832824 Jun 27 06:33:39 PM PDT 24 Jun 27 06:33:50 PM PDT 24 2877524822 ps
T826 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1301650698 Jun 27 06:34:19 PM PDT 24 Jun 27 06:34:22 PM PDT 24 537847027 ps
T827 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.4211168274 Jun 27 06:34:04 PM PDT 24 Jun 27 06:34:09 PM PDT 24 987669115 ps
T828 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1235582001 Jun 27 06:33:44 PM PDT 24 Jun 27 06:33:50 PM PDT 24 541470942 ps
T829 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2780994326 Jun 27 06:34:22 PM PDT 24 Jun 27 06:34:30 PM PDT 24 525967772 ps
T830 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1672431230 Jun 27 06:33:40 PM PDT 24 Jun 27 06:33:45 PM PDT 24 534211060 ps
T831 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1853435039 Jun 27 06:34:04 PM PDT 24 Jun 27 06:34:16 PM PDT 24 4388411819 ps
T832 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2827041048 Jun 27 06:34:21 PM PDT 24 Jun 27 06:34:28 PM PDT 24 346947918 ps
T833 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3015872708 Jun 27 06:34:05 PM PDT 24 Jun 27 06:34:11 PM PDT 24 2061704752 ps
T834 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2192972300 Jun 27 06:34:22 PM PDT 24 Jun 27 06:34:31 PM PDT 24 405907816 ps
T123 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2958773937 Jun 27 06:33:37 PM PDT 24 Jun 27 06:33:44 PM PDT 24 835635948 ps
T835 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.196531340 Jun 27 06:33:41 PM PDT 24 Jun 27 06:33:55 PM PDT 24 3028756375 ps
T836 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3119235232 Jun 27 06:34:17 PM PDT 24 Jun 27 06:34:20 PM PDT 24 514070516 ps
T837 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3090973401 Jun 27 06:34:18 PM PDT 24 Jun 27 06:34:21 PM PDT 24 386671062 ps
T838 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1690848146 Jun 27 06:33:45 PM PDT 24 Jun 27 06:33:52 PM PDT 24 523068437 ps
T839 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1373765150 Jun 27 06:33:44 PM PDT 24 Jun 27 06:33:49 PM PDT 24 347853085 ps
T840 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.668680734 Jun 27 06:34:02 PM PDT 24 Jun 27 06:34:06 PM PDT 24 529556698 ps
T841 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.994480080 Jun 27 06:34:06 PM PDT 24 Jun 27 06:34:13 PM PDT 24 2764151634 ps
T842 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.4068123809 Jun 27 06:33:40 PM PDT 24 Jun 27 06:33:46 PM PDT 24 437259253 ps
T843 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3501192947 Jun 27 06:34:22 PM PDT 24 Jun 27 06:34:29 PM PDT 24 358615039 ps
T844 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3752275476 Jun 27 06:34:03 PM PDT 24 Jun 27 06:34:06 PM PDT 24 331334816 ps
T845 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.543913100 Jun 27 06:33:40 PM PDT 24 Jun 27 06:33:46 PM PDT 24 775742244 ps
T124 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.216060794 Jun 27 06:33:42 PM PDT 24 Jun 27 06:33:50 PM PDT 24 1267759921 ps
T846 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2187329871 Jun 27 06:33:43 PM PDT 24 Jun 27 06:33:49 PM PDT 24 504731413 ps
T847 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.4017403175 Jun 27 06:34:22 PM PDT 24 Jun 27 06:34:30 PM PDT 24 392515020 ps
T848 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2716771784 Jun 27 06:34:06 PM PDT 24 Jun 27 06:34:09 PM PDT 24 436269679 ps
T78 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3439568523 Jun 27 06:33:39 PM PDT 24 Jun 27 06:33:48 PM PDT 24 4098830213 ps
T125 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1995978325 Jun 27 06:34:07 PM PDT 24 Jun 27 06:34:10 PM PDT 24 445496151 ps
T849 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3715990881 Jun 27 06:33:46 PM PDT 24 Jun 27 06:33:56 PM PDT 24 2191991265 ps
T850 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1314503733 Jun 27 06:33:46 PM PDT 24 Jun 27 06:33:51 PM PDT 24 973705064 ps
T851 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1226905356 Jun 27 06:33:39 PM PDT 24 Jun 27 06:33:43 PM PDT 24 352096293 ps
T852 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1678426838 Jun 27 06:34:21 PM PDT 24 Jun 27 06:34:26 PM PDT 24 544074182 ps
T853 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.309078867 Jun 27 06:33:45 PM PDT 24 Jun 27 06:33:50 PM PDT 24 521523858 ps
T854 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.223855710 Jun 27 06:34:21 PM PDT 24 Jun 27 06:34:27 PM PDT 24 341422850 ps
T855 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2631900539 Jun 27 06:34:17 PM PDT 24 Jun 27 06:34:20 PM PDT 24 317513656 ps
T856 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1846768967 Jun 27 06:33:44 PM PDT 24 Jun 27 06:33:52 PM PDT 24 4166872443 ps
T857 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1448591745 Jun 27 06:34:20 PM PDT 24 Jun 27 06:34:24 PM PDT 24 507725674 ps
T858 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.132129561 Jun 27 06:33:39 PM PDT 24 Jun 27 06:33:44 PM PDT 24 351544211 ps
T859 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1083661905 Jun 27 06:33:38 PM PDT 24 Jun 27 06:34:01 PM PDT 24 8894054018 ps
T126 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.570211319 Jun 27 06:33:39 PM PDT 24 Jun 27 06:33:45 PM PDT 24 1477709022 ps
T860 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3233166255 Jun 27 06:34:03 PM PDT 24 Jun 27 06:34:06 PM PDT 24 443526814 ps
T861 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.690759545 Jun 27 06:33:44 PM PDT 24 Jun 27 06:33:49 PM PDT 24 361309042 ps
T862 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1039105825 Jun 27 06:33:44 PM PDT 24 Jun 27 06:33:49 PM PDT 24 701262669 ps
T863 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.4278458525 Jun 27 06:34:18 PM PDT 24 Jun 27 06:34:20 PM PDT 24 514704003 ps
T864 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2982535758 Jun 27 06:33:38 PM PDT 24 Jun 27 06:33:44 PM PDT 24 407444946 ps
T865 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.616986966 Jun 27 06:33:38 PM PDT 24 Jun 27 06:33:42 PM PDT 24 402807791 ps
T866 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2930900506 Jun 27 06:34:20 PM PDT 24 Jun 27 06:34:26 PM PDT 24 412537390 ps
T867 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4194223133 Jun 27 06:33:37 PM PDT 24 Jun 27 06:33:41 PM PDT 24 595357001 ps
T868 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3414757449 Jun 27 06:34:20 PM PDT 24 Jun 27 06:34:25 PM PDT 24 339997637 ps
T869 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2950914328 Jun 27 06:34:23 PM PDT 24 Jun 27 06:34:33 PM PDT 24 466815809 ps
T870 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1970729550 Jun 27 06:34:21 PM PDT 24 Jun 27 06:34:27 PM PDT 24 417564401 ps
T871 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1010391177 Jun 27 06:34:23 PM PDT 24 Jun 27 06:34:32 PM PDT 24 286115981 ps
T872 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3337703362 Jun 27 06:34:06 PM PDT 24 Jun 27 06:34:13 PM PDT 24 2186517692 ps
T873 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.416433377 Jun 27 06:34:21 PM PDT 24 Jun 27 06:34:30 PM PDT 24 2307505886 ps
T127 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.803498465 Jun 27 06:33:44 PM PDT 24 Jun 27 06:33:53 PM PDT 24 2199973921 ps
T874 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1109230204 Jun 27 06:33:44 PM PDT 24 Jun 27 06:33:52 PM PDT 24 8469833777 ps
T875 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1568791133 Jun 27 06:33:30 PM PDT 24 Jun 27 06:33:34 PM PDT 24 526958167 ps
T876 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3905159086 Jun 27 06:33:45 PM PDT 24 Jun 27 06:34:10 PM PDT 24 8485229373 ps
T877 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.543617757 Jun 27 06:34:20 PM PDT 24 Jun 27 06:34:26 PM PDT 24 365898382 ps
T128 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3360390348 Jun 27 06:33:37 PM PDT 24 Jun 27 06:34:06 PM PDT 24 11349387828 ps
T878 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1081089525 Jun 27 06:34:22 PM PDT 24 Jun 27 06:34:31 PM PDT 24 547523908 ps
T879 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1097528480 Jun 27 06:34:03 PM PDT 24 Jun 27 06:34:06 PM PDT 24 579471608 ps
T880 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.261433766 Jun 27 06:34:05 PM PDT 24 Jun 27 06:34:09 PM PDT 24 328568860 ps
T881 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1734907028 Jun 27 06:33:45 PM PDT 24 Jun 27 06:33:50 PM PDT 24 360601338 ps
T882 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1473485024 Jun 27 06:33:39 PM PDT 24 Jun 27 06:33:53 PM PDT 24 2336826666 ps
T883 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2139735768 Jun 27 06:33:33 PM PDT 24 Jun 27 06:33:37 PM PDT 24 763912692 ps
T129 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1013365158 Jun 27 06:33:42 PM PDT 24 Jun 27 06:33:48 PM PDT 24 322536166 ps
T884 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1983568105 Jun 27 06:34:03 PM PDT 24 Jun 27 06:34:10 PM PDT 24 8414794709 ps
T885 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.44096096 Jun 27 06:34:22 PM PDT 24 Jun 27 06:34:31 PM PDT 24 456516859 ps
T886 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.936668555 Jun 27 06:33:48 PM PDT 24 Jun 27 06:33:54 PM PDT 24 5202246338 ps
T887 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2994338296 Jun 27 06:34:03 PM PDT 24 Jun 27 06:34:05 PM PDT 24 314329874 ps
T888 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.393935345 Jun 27 06:34:20 PM PDT 24 Jun 27 06:34:26 PM PDT 24 419694659 ps
T889 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1114684758 Jun 27 06:33:39 PM PDT 24 Jun 27 06:33:43 PM PDT 24 416263692 ps
T890 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.302943410 Jun 27 06:33:39 PM PDT 24 Jun 27 06:33:44 PM PDT 24 480013539 ps
T891 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.803442348 Jun 27 06:33:39 PM PDT 24 Jun 27 06:33:54 PM PDT 24 2624297921 ps
T892 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1987633746 Jun 27 06:34:05 PM PDT 24 Jun 27 06:34:10 PM PDT 24 547932455 ps
T893 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.939825761 Jun 27 06:34:08 PM PDT 24 Jun 27 06:34:11 PM PDT 24 360429824 ps
T894 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3732508193 Jun 27 06:33:42 PM PDT 24 Jun 27 06:33:49 PM PDT 24 781844569 ps
T130 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2099156530 Jun 27 06:33:37 PM PDT 24 Jun 27 06:34:15 PM PDT 24 25956086808 ps
T895 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.728708734 Jun 27 06:33:30 PM PDT 24 Jun 27 06:33:40 PM PDT 24 4981833267 ps
T896 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1122707537 Jun 27 06:33:45 PM PDT 24 Jun 27 06:33:50 PM PDT 24 388880868 ps
T897 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1158348660 Jun 27 06:34:03 PM PDT 24 Jun 27 06:34:06 PM PDT 24 508488101 ps
T898 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3827914258 Jun 27 06:33:38 PM PDT 24 Jun 27 06:33:43 PM PDT 24 393020942 ps
T131 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.4150715883 Jun 27 06:34:07 PM PDT 24 Jun 27 06:34:11 PM PDT 24 464070835 ps
T899 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2201039228 Jun 27 06:34:05 PM PDT 24 Jun 27 06:34:11 PM PDT 24 818642090 ps
T900 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1450225969 Jun 27 06:33:37 PM PDT 24 Jun 27 06:33:58 PM PDT 24 4726465674 ps
T901 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1759245970 Jun 27 06:33:39 PM PDT 24 Jun 27 06:33:44 PM PDT 24 449832605 ps
T902 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1454672853 Jun 27 06:34:13 PM PDT 24 Jun 27 06:34:16 PM PDT 24 403753800 ps
T903 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2710904204 Jun 27 06:34:18 PM PDT 24 Jun 27 06:34:20 PM PDT 24 698493867 ps
T904 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1573406715 Jun 27 06:33:42 PM PDT 24 Jun 27 06:33:49 PM PDT 24 544248781 ps
T905 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1462722602 Jun 27 06:33:45 PM PDT 24 Jun 27 06:34:02 PM PDT 24 5007652301 ps
T906 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.932100254 Jun 27 06:33:39 PM PDT 24 Jun 27 06:33:46 PM PDT 24 527316739 ps
T907 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2340718317 Jun 27 06:33:43 PM PDT 24 Jun 27 06:33:54 PM PDT 24 2400600479 ps
T908 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2788371062 Jun 27 06:33:37 PM PDT 24 Jun 27 06:33:47 PM PDT 24 2483902345 ps
T909 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1707275060 Jun 27 06:34:04 PM PDT 24 Jun 27 06:34:09 PM PDT 24 576692759 ps
T910 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2943885899 Jun 27 06:33:39 PM PDT 24 Jun 27 06:33:57 PM PDT 24 8414465157 ps
T911 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3469712052 Jun 27 06:34:03 PM PDT 24 Jun 27 06:34:18 PM PDT 24 3905144720 ps
T912 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3444703657 Jun 27 06:33:45 PM PDT 24 Jun 27 06:33:50 PM PDT 24 479903607 ps
T913 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3037646 Jun 27 06:33:33 PM PDT 24 Jun 27 06:33:38 PM PDT 24 562044148 ps
T914 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3640812396 Jun 27 06:34:04 PM PDT 24 Jun 27 06:34:07 PM PDT 24 481116297 ps
T915 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3247313168 Jun 27 06:33:42 PM PDT 24 Jun 27 06:33:58 PM PDT 24 8129019542 ps
T355 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.4081167112 Jun 27 06:33:40 PM PDT 24 Jun 27 06:33:56 PM PDT 24 8380299086 ps
T916 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2067120870 Jun 27 06:33:44 PM PDT 24 Jun 27 06:33:58 PM PDT 24 4582329613 ps
T917 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1462357112 Jun 27 06:33:38 PM PDT 24 Jun 27 06:33:43 PM PDT 24 374778428 ps
T918 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.956553564 Jun 27 06:33:44 PM PDT 24 Jun 27 06:33:50 PM PDT 24 480232985 ps
T919 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.937707349 Jun 27 06:33:39 PM PDT 24 Jun 27 06:33:43 PM PDT 24 351802183 ps
T920 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2375225638 Jun 27 06:33:32 PM PDT 24 Jun 27 06:33:37 PM PDT 24 548652844 ps

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.743384954
Short name T9
Test name
Test status
Simulation time 646344561753 ps
CPU time 202.14 seconds
Started Jun 27 07:09:58 PM PDT 24
Finished Jun 27 07:13:36 PM PDT 24
Peak memory 202092 kb
Host smart-200dd6c5-6aa8-4f72-b2fe-f678e924ab48
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743384954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_
wakeup.743384954
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.1601318003
Short name T14
Test name
Test status
Simulation time 24209635183 ps
CPU time 53.2 seconds
Started Jun 27 07:07:41 PM PDT 24
Finished Jun 27 07:08:35 PM PDT 24
Peak memory 210224 kb
Host smart-7ad30229-7935-480a-9542-b5db94cffb81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601318003 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.1601318003
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.3378829083
Short name T50
Test name
Test status
Simulation time 125340309771 ps
CPU time 517.81 seconds
Started Jun 27 07:08:35 PM PDT 24
Finished Jun 27 07:17:14 PM PDT 24
Peak memory 202192 kb
Host smart-b5991c1e-c8a5-4365-ad25-a2d6fef336e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378829083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.3378829083
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.428771218
Short name T152
Test name
Test status
Simulation time 725748394012 ps
CPU time 444.87 seconds
Started Jun 27 07:07:29 PM PDT 24
Finished Jun 27 07:14:57 PM PDT 24
Peak memory 201816 kb
Host smart-60010b6f-535e-45bd-b413-8c7ca6f16e1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428771218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.
428771218
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.2084028157
Short name T40
Test name
Test status
Simulation time 408965520399 ps
CPU time 930.49 seconds
Started Jun 27 07:06:41 PM PDT 24
Finished Jun 27 07:22:21 PM PDT 24
Peak memory 201872 kb
Host smart-773f6cba-ba9e-4c4c-9959-43f2bfd41b01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084028157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
2084028157
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.4188925766
Short name T163
Test name
Test status
Simulation time 489035991047 ps
CPU time 301.15 seconds
Started Jun 27 07:07:29 PM PDT 24
Finished Jun 27 07:12:33 PM PDT 24
Peak memory 201928 kb
Host smart-93ded957-dffb-4937-84a0-06062c8bb012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188925766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.4188925766
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.41121342
Short name T144
Test name
Test status
Simulation time 576408144380 ps
CPU time 516.28 seconds
Started Jun 27 07:11:33 PM PDT 24
Finished Jun 27 07:20:42 PM PDT 24
Peak memory 201884 kb
Host smart-24ea0227-f021-4090-99a9-a818033c15ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41121342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.41121342
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.934936325
Short name T146
Test name
Test status
Simulation time 535849776921 ps
CPU time 1244.61 seconds
Started Jun 27 07:08:13 PM PDT 24
Finished Jun 27 07:28:59 PM PDT 24
Peak memory 201828 kb
Host smart-b5213abd-00f6-4158-9b5e-65ca6cadca18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934936325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.
934936325
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.4062970789
Short name T189
Test name
Test status
Simulation time 498835223029 ps
CPU time 1210.7 seconds
Started Jun 27 07:06:40 PM PDT 24
Finished Jun 27 07:26:59 PM PDT 24
Peak memory 201884 kb
Host smart-feb44855-fe1e-4943-a5d8-1843a04a0550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062970789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.4062970789
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.196976585
Short name T58
Test name
Test status
Simulation time 96773847642 ps
CPU time 243.39 seconds
Started Jun 27 07:07:31 PM PDT 24
Finished Jun 27 07:11:37 PM PDT 24
Peak memory 211380 kb
Host smart-6607a7fe-970a-4c14-a55c-4d4fed9429c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196976585 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.196976585
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.4144899244
Short name T37
Test name
Test status
Simulation time 499455217340 ps
CPU time 613.41 seconds
Started Jun 27 07:07:43 PM PDT 24
Finished Jun 27 07:17:59 PM PDT 24
Peak memory 210560 kb
Host smart-dc55bf6e-2998-45b3-8c4e-865db83dd999
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144899244 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.4144899244
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.420008091
Short name T63
Test name
Test status
Simulation time 7898106236 ps
CPU time 18.71 seconds
Started Jun 27 07:06:39 PM PDT 24
Finished Jun 27 07:07:06 PM PDT 24
Peak memory 218216 kb
Host smart-e81e4951-dcae-4ec5-896b-d02d0b192deb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420008091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.420008091
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.1046991351
Short name T209
Test name
Test status
Simulation time 495318859977 ps
CPU time 238.08 seconds
Started Jun 27 07:11:04 PM PDT 24
Finished Jun 27 07:15:04 PM PDT 24
Peak memory 201856 kb
Host smart-0f25ab18-61ab-4b45-849a-371bb523c96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046991351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.1046991351
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1117350267
Short name T13
Test name
Test status
Simulation time 170003359472 ps
CPU time 187.75 seconds
Started Jun 27 07:13:13 PM PDT 24
Finished Jun 27 07:18:12 PM PDT 24
Peak memory 210220 kb
Host smart-dd7a6e88-2074-4349-b853-2e2bbc5d943e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117350267 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1117350267
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1621792772
Short name T142
Test name
Test status
Simulation time 549767848373 ps
CPU time 953.35 seconds
Started Jun 27 07:11:30 PM PDT 24
Finished Jun 27 07:27:45 PM PDT 24
Peak memory 201872 kb
Host smart-c2639707-eb02-49d8-b61c-58f80bf0fffb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621792772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1621792772
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.2048464061
Short name T231
Test name
Test status
Simulation time 380206765319 ps
CPU time 820.97 seconds
Started Jun 27 07:08:33 PM PDT 24
Finished Jun 27 07:22:15 PM PDT 24
Peak memory 201820 kb
Host smart-29b890b9-3e14-40de-bd60-16e290fd97e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048464061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.2048464061
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.456484098
Short name T243
Test name
Test status
Simulation time 336426719910 ps
CPU time 158.02 seconds
Started Jun 27 07:12:33 PM PDT 24
Finished Jun 27 07:16:52 PM PDT 24
Peak memory 201864 kb
Host smart-137b6e53-b795-48d5-b1fb-e0608b59230c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456484098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.456484098
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3505294671
Short name T121
Test name
Test status
Simulation time 398646529 ps
CPU time 1.73 seconds
Started Jun 27 06:34:04 PM PDT 24
Finished Jun 27 06:34:08 PM PDT 24
Peak memory 201512 kb
Host smart-e4e7249e-bddd-4101-b80b-09c954a639a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505294671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3505294671
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1245558882
Short name T241
Test name
Test status
Simulation time 563821656716 ps
CPU time 1223.35 seconds
Started Jun 27 07:07:56 PM PDT 24
Finished Jun 27 07:28:20 PM PDT 24
Peak memory 201964 kb
Host smart-166fd57a-36be-4c49-a689-545f3d12f778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245558882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1245558882
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3624772250
Short name T66
Test name
Test status
Simulation time 293551189 ps
CPU time 2.12 seconds
Started Jun 27 06:33:38 PM PDT 24
Finished Jun 27 06:33:43 PM PDT 24
Peak memory 201784 kb
Host smart-3d7889ef-def5-4a5f-833d-2d7125a56e90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624772250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3624772250
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.2009219101
Short name T274
Test name
Test status
Simulation time 567271338844 ps
CPU time 343.43 seconds
Started Jun 27 07:09:30 PM PDT 24
Finished Jun 27 07:15:15 PM PDT 24
Peak memory 201892 kb
Host smart-e5fdeb17-6651-4f65-bb06-204f34481744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009219101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2009219101
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.919872321
Short name T30
Test name
Test status
Simulation time 322691805606 ps
CPU time 108.84 seconds
Started Jun 27 07:08:48 PM PDT 24
Finished Jun 27 07:10:40 PM PDT 24
Peak memory 201836 kb
Host smart-f1eb81b1-011a-422b-acf6-8623911a1fa2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=919872321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrup
t_fixed.919872321
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.2015307721
Short name T264
Test name
Test status
Simulation time 491190626209 ps
CPU time 238.47 seconds
Started Jun 27 07:07:27 PM PDT 24
Finished Jun 27 07:11:27 PM PDT 24
Peak memory 201868 kb
Host smart-d3e74426-ea42-48ac-a8fb-702f361a50e5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015307721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.2015307721
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.669465117
Short name T110
Test name
Test status
Simulation time 600558063683 ps
CPU time 360.78 seconds
Started Jun 27 07:11:03 PM PDT 24
Finished Jun 27 07:17:06 PM PDT 24
Peak memory 201928 kb
Host smart-339efb85-869b-44b9-b30d-e7dbc0702cdd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669465117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.669465117
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.3086256125
Short name T235
Test name
Test status
Simulation time 326829096798 ps
CPU time 773.22 seconds
Started Jun 27 07:12:41 PM PDT 24
Finished Jun 27 07:28:10 PM PDT 24
Peak memory 201956 kb
Host smart-aa85e9be-294e-4230-861f-768323de07cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086256125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.3086256125
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2770011996
Short name T220
Test name
Test status
Simulation time 404801343606 ps
CPU time 1031.42 seconds
Started Jun 27 07:07:16 PM PDT 24
Finished Jun 27 07:24:31 PM PDT 24
Peak memory 210316 kb
Host smart-a3b0c37d-bc46-4bc1-9bd6-16888d9a7f3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770011996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2770011996
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.760259626
Short name T112
Test name
Test status
Simulation time 492494975061 ps
CPU time 280.47 seconds
Started Jun 27 07:12:15 PM PDT 24
Finished Jun 27 07:18:15 PM PDT 24
Peak memory 201876 kb
Host smart-c5d3faf1-df34-4b38-9643-c38fb732077f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760259626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.760259626
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.3733843315
Short name T229
Test name
Test status
Simulation time 1500860251940 ps
CPU time 1967.69 seconds
Started Jun 27 07:12:19 PM PDT 24
Finished Jun 27 07:46:30 PM PDT 24
Peak memory 210316 kb
Host smart-19d18212-19a5-4ad5-8c2a-b5036fb37dfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733843315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.3733843315
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3277093432
Short name T250
Test name
Test status
Simulation time 372940116469 ps
CPU time 872.39 seconds
Started Jun 27 07:07:43 PM PDT 24
Finished Jun 27 07:22:18 PM PDT 24
Peak memory 201888 kb
Host smart-0757b7ec-bee7-4c4a-aea7-52f63e631053
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277093432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3277093432
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.1124381625
Short name T92
Test name
Test status
Simulation time 500139466190 ps
CPU time 113.42 seconds
Started Jun 27 07:07:43 PM PDT 24
Finished Jun 27 07:09:38 PM PDT 24
Peak memory 201868 kb
Host smart-ea035598-3c8c-4d60-9294-664bc40d6925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124381625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.1124381625
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.1738050996
Short name T395
Test name
Test status
Simulation time 324886194 ps
CPU time 1.44 seconds
Started Jun 27 07:07:16 PM PDT 24
Finished Jun 27 07:07:21 PM PDT 24
Peak memory 201032 kb
Host smart-e942df3d-203d-4e74-9304-34a1831e6873
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738050996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.1738050996
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2427969653
Short name T76
Test name
Test status
Simulation time 8944867876 ps
CPU time 8.18 seconds
Started Jun 27 06:34:07 PM PDT 24
Finished Jun 27 06:34:17 PM PDT 24
Peak memory 201784 kb
Host smart-5e21defd-687e-4dac-a53b-5a118c917f8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427969653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2427969653
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.1417612622
Short name T150
Test name
Test status
Simulation time 539325631208 ps
CPU time 654.33 seconds
Started Jun 27 07:06:38 PM PDT 24
Finished Jun 27 07:17:39 PM PDT 24
Peak memory 201896 kb
Host smart-4c4c0f9e-f6ba-4e60-adc2-12e2e2b4983d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417612622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1417612622
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3626216054
Short name T52
Test name
Test status
Simulation time 2677648914 ps
CPU time 2.09 seconds
Started Jun 27 06:33:44 PM PDT 24
Finished Jun 27 06:33:50 PM PDT 24
Peak memory 201652 kb
Host smart-51d93984-8b63-4256-a29a-195ab995bcea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626216054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.3626216054
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3335916421
Short name T107
Test name
Test status
Simulation time 845931747626 ps
CPU time 705.43 seconds
Started Jun 27 07:09:29 PM PDT 24
Finished Jun 27 07:21:16 PM PDT 24
Peak memory 210552 kb
Host smart-5768a06d-b238-4ca8-a935-be715727e355
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335916421 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3335916421
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.2469765199
Short name T228
Test name
Test status
Simulation time 329190073271 ps
CPU time 374.57 seconds
Started Jun 27 07:13:30 PM PDT 24
Finished Jun 27 07:21:35 PM PDT 24
Peak memory 201880 kb
Host smart-358c3261-ed4a-4498-b2e1-2c111867231d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469765199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2469765199
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2819748882
Short name T48
Test name
Test status
Simulation time 123113746309 ps
CPU time 502.18 seconds
Started Jun 27 07:07:30 PM PDT 24
Finished Jun 27 07:15:55 PM PDT 24
Peak memory 202204 kb
Host smart-10c99418-c051-4bad-a7c6-0f2f66a4e116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819748882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2819748882
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.517144901
Short name T44
Test name
Test status
Simulation time 331008706549 ps
CPU time 817.84 seconds
Started Jun 27 07:09:15 PM PDT 24
Finished Jun 27 07:22:53 PM PDT 24
Peak memory 201876 kb
Host smart-7763c4cd-b961-48db-a5cf-f4f491e2754d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517144901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.517144901
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.3393839800
Short name T105
Test name
Test status
Simulation time 538951663191 ps
CPU time 625 seconds
Started Jun 27 07:13:19 PM PDT 24
Finished Jun 27 07:25:30 PM PDT 24
Peak memory 201940 kb
Host smart-3cd2b32c-46fe-4157-b587-ca3ba83006e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393839800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3393839800
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2962691787
Short name T317
Test name
Test status
Simulation time 375821498077 ps
CPU time 352.84 seconds
Started Jun 27 07:06:49 PM PDT 24
Finished Jun 27 07:12:49 PM PDT 24
Peak memory 201828 kb
Host smart-cdccaef4-4633-46f9-92c6-27a4edb2a2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962691787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2962691787
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.2446705001
Short name T213
Test name
Test status
Simulation time 191260048556 ps
CPU time 98.19 seconds
Started Jun 27 07:07:27 PM PDT 24
Finished Jun 27 07:09:08 PM PDT 24
Peak memory 201868 kb
Host smart-8135d17a-5255-44c8-bbf2-94e6eaa07c12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446705001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.2446705001
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.1760337702
Short name T330
Test name
Test status
Simulation time 505693546034 ps
CPU time 273.61 seconds
Started Jun 27 07:09:02 PM PDT 24
Finished Jun 27 07:13:37 PM PDT 24
Peak memory 201856 kb
Host smart-afc09854-1639-488a-bdce-b0ef214743db
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760337702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.1760337702
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.71825179
Short name T193
Test name
Test status
Simulation time 379625084481 ps
CPU time 58.45 seconds
Started Jun 27 07:13:30 PM PDT 24
Finished Jun 27 07:16:27 PM PDT 24
Peak memory 201844 kb
Host smart-6c2b236a-fab7-466e-bc70-b7a2f3c060d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71825179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.71825179
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2706227871
Short name T277
Test name
Test status
Simulation time 42019919837 ps
CPU time 129.21 seconds
Started Jun 27 07:08:14 PM PDT 24
Finished Jun 27 07:10:25 PM PDT 24
Peak memory 210544 kb
Host smart-89e2cb48-7327-4f50-88bf-1f2a56be2184
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706227871 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.2706227871
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2817828362
Short name T43
Test name
Test status
Simulation time 365472045958 ps
CPU time 775.71 seconds
Started Jun 27 07:06:39 PM PDT 24
Finished Jun 27 07:19:42 PM PDT 24
Peak memory 201884 kb
Host smart-65e7fcc1-911b-483c-8c45-c5fec0e1dea9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817828362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2817828362
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.4042592523
Short name T204
Test name
Test status
Simulation time 324555999909 ps
CPU time 190.06 seconds
Started Jun 27 07:11:16 PM PDT 24
Finished Jun 27 07:14:29 PM PDT 24
Peak memory 201844 kb
Host smart-45d71a38-a4c6-4593-8c27-d60a77340606
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042592523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.4042592523
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.2958564944
Short name T286
Test name
Test status
Simulation time 320559194467 ps
CPU time 788.1 seconds
Started Jun 27 07:06:39 PM PDT 24
Finished Jun 27 07:19:55 PM PDT 24
Peak memory 201836 kb
Host smart-ad7815b0-f3cb-47e1-9c22-704073ce7787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958564944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2958564944
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1273642579
Short name T812
Test name
Test status
Simulation time 568366423 ps
CPU time 2.25 seconds
Started Jun 27 06:33:39 PM PDT 24
Finished Jun 27 06:33:45 PM PDT 24
Peak memory 201736 kb
Host smart-44c1aaa0-6baa-4d19-9393-ae9714bb47df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273642579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1273642579
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.2335195644
Short name T309
Test name
Test status
Simulation time 350345203520 ps
CPU time 207.44 seconds
Started Jun 27 07:06:40 PM PDT 24
Finished Jun 27 07:10:17 PM PDT 24
Peak memory 201908 kb
Host smart-41eaf3d5-c7dc-4aaa-9566-3aa7027cbadd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335195644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.2335195644
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.251600784
Short name T316
Test name
Test status
Simulation time 368799592996 ps
CPU time 402.86 seconds
Started Jun 27 07:10:32 PM PDT 24
Finished Jun 27 07:17:19 PM PDT 24
Peak memory 201780 kb
Host smart-0ef9c318-9c7e-4866-a65f-f001c35ce85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251600784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.251600784
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.569122980
Short name T147
Test name
Test status
Simulation time 549300577012 ps
CPU time 619.84 seconds
Started Jun 27 07:07:43 PM PDT 24
Finished Jun 27 07:18:05 PM PDT 24
Peak memory 201880 kb
Host smart-022bdd6f-7294-406e-98a9-c091ab2cfea7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569122980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_
wakeup.569122980
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.2343308900
Short name T304
Test name
Test status
Simulation time 347645820386 ps
CPU time 178.56 seconds
Started Jun 27 07:11:46 PM PDT 24
Finished Jun 27 07:15:25 PM PDT 24
Peak memory 201876 kb
Host smart-9dfaa20b-0ac5-4262-b130-8d30371ebd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343308900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2343308900
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2223560692
Short name T240
Test name
Test status
Simulation time 489851203178 ps
CPU time 1040.82 seconds
Started Jun 27 07:08:12 PM PDT 24
Finished Jun 27 07:25:34 PM PDT 24
Peak memory 201928 kb
Host smart-a261fa87-c29c-4b77-a4de-670478d5a095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223560692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2223560692
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.434359404
Short name T292
Test name
Test status
Simulation time 929144183680 ps
CPU time 1103.73 seconds
Started Jun 27 07:08:40 PM PDT 24
Finished Jun 27 07:27:05 PM PDT 24
Peak memory 210440 kb
Host smart-379aaf1a-a92b-4d60-a5b7-a7a859ea6d78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434359404 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.434359404
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.2671560786
Short name T300
Test name
Test status
Simulation time 358175654688 ps
CPU time 823.24 seconds
Started Jun 27 07:11:31 PM PDT 24
Finished Jun 27 07:25:41 PM PDT 24
Peak memory 201960 kb
Host smart-8290423e-0530-48dc-b373-2babc7e07d50
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671560786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.2671560786
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.281066741
Short name T253
Test name
Test status
Simulation time 575559869702 ps
CPU time 1224.16 seconds
Started Jun 27 07:06:56 PM PDT 24
Finished Jun 27 07:27:24 PM PDT 24
Peak memory 201888 kb
Host smart-aafc5dd7-ebb1-4ed6-b907-31cd20962fce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281066741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.281066741
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.3800742149
Short name T332
Test name
Test status
Simulation time 350548206074 ps
CPU time 746.42 seconds
Started Jun 27 07:07:02 PM PDT 24
Finished Jun 27 07:19:30 PM PDT 24
Peak memory 201932 kb
Host smart-e2d8cb1a-550a-421f-bd4c-ac748ad18a49
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800742149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.3800742149
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.1330982709
Short name T251
Test name
Test status
Simulation time 157012812831 ps
CPU time 75.05 seconds
Started Jun 27 07:07:13 PM PDT 24
Finished Jun 27 07:08:30 PM PDT 24
Peak memory 210192 kb
Host smart-58687df3-7b56-4edd-9569-de4ee6d79a3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330982709 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.1330982709
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2216841981
Short name T256
Test name
Test status
Simulation time 289504960622 ps
CPU time 518.27 seconds
Started Jun 27 07:07:27 PM PDT 24
Finished Jun 27 07:16:07 PM PDT 24
Peak memory 210376 kb
Host smart-8c32c508-af32-4e6d-b606-895afcd37e8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216841981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2216841981
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.1800395083
Short name T341
Test name
Test status
Simulation time 493425400758 ps
CPU time 178.06 seconds
Started Jun 27 07:07:43 PM PDT 24
Finished Jun 27 07:10:44 PM PDT 24
Peak memory 201856 kb
Host smart-6a07e2cc-6e54-44c0-b69b-d2822447a69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800395083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.1800395083
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1870694522
Short name T303
Test name
Test status
Simulation time 161839686604 ps
CPU time 200.2 seconds
Started Jun 27 07:07:42 PM PDT 24
Finished Jun 27 07:11:05 PM PDT 24
Peak memory 201876 kb
Host smart-7314f615-0776-4d5f-859b-140c9bead19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870694522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1870694522
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2214453086
Short name T338
Test name
Test status
Simulation time 389622262959 ps
CPU time 141.26 seconds
Started Jun 27 07:09:14 PM PDT 24
Finished Jun 27 07:11:37 PM PDT 24
Peak memory 202068 kb
Host smart-6163b638-25f1-404b-80c7-3f315488c0ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214453086 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2214453086
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2568483327
Short name T18
Test name
Test status
Simulation time 91193484682 ps
CPU time 109.18 seconds
Started Jun 27 07:07:57 PM PDT 24
Finished Jun 27 07:09:48 PM PDT 24
Peak memory 210548 kb
Host smart-d3c7ea51-d58d-4c1f-af48-0a8e1dc9aae0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568483327 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.2568483327
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.3598506426
Short name T306
Test name
Test status
Simulation time 541043048452 ps
CPU time 1021.21 seconds
Started Jun 27 07:06:52 PM PDT 24
Finished Jun 27 07:23:58 PM PDT 24
Peak memory 201908 kb
Host smart-e810ee4e-11f2-453d-859f-c8cc60ef8c80
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598506426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.3598506426
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.8594496
Short name T339
Test name
Test status
Simulation time 73521106186 ps
CPU time 178.33 seconds
Started Jun 27 07:06:55 PM PDT 24
Finished Jun 27 07:09:57 PM PDT 24
Peak memory 212240 kb
Host smart-fa59bf08-b204-4a05-8593-5fa9a9620180
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8594496 -assert nopost
proc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.8594496
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.494131325
Short name T377
Test name
Test status
Simulation time 202978832561 ps
CPU time 233 seconds
Started Jun 27 07:07:01 PM PDT 24
Finished Jun 27 07:10:56 PM PDT 24
Peak memory 201792 kb
Host smart-ca7bb477-042f-4341-a5bd-767757eae687
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494131325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
adc_ctrl_filters_wakeup_fixed.494131325
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.4216708216
Short name T35
Test name
Test status
Simulation time 304592669103 ps
CPU time 216.29 seconds
Started Jun 27 07:07:30 PM PDT 24
Finished Jun 27 07:11:10 PM PDT 24
Peak memory 218072 kb
Host smart-2762945e-de2f-4552-90b1-ee0c1d15811b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216708216 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.4216708216
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.2773717769
Short name T305
Test name
Test status
Simulation time 498566274053 ps
CPU time 1063.02 seconds
Started Jun 27 07:08:13 PM PDT 24
Finished Jun 27 07:25:58 PM PDT 24
Peak memory 201852 kb
Host smart-36f3d160-ff33-4bea-872a-6fad33e067ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773717769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.2773717769
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1222707952
Short name T57
Test name
Test status
Simulation time 4209558276 ps
CPU time 11.4 seconds
Started Jun 27 06:33:46 PM PDT 24
Finished Jun 27 06:34:01 PM PDT 24
Peak memory 201776 kb
Host smart-2a2a8ce4-446b-405e-b0a3-12834bf84f49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222707952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1222707952
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.2330847100
Short name T360
Test name
Test status
Simulation time 98850952915 ps
CPU time 402.09 seconds
Started Jun 27 07:07:14 PM PDT 24
Finished Jun 27 07:14:00 PM PDT 24
Peak memory 202212 kb
Host smart-9ecf4eb3-9d23-40ef-93b9-c2ae8574f952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330847100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2330847100
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.4265099523
Short name T190
Test name
Test status
Simulation time 372870962546 ps
CPU time 249.57 seconds
Started Jun 27 07:07:13 PM PDT 24
Finished Jun 27 07:11:24 PM PDT 24
Peak memory 201884 kb
Host smart-3e653891-d0e5-4440-beb7-e44954bb0507
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265099523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.4265099523
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.3228352196
Short name T722
Test name
Test status
Simulation time 87144264816 ps
CPU time 368.93 seconds
Started Jun 27 07:07:15 PM PDT 24
Finished Jun 27 07:13:27 PM PDT 24
Peak memory 210664 kb
Host smart-74d7a86f-5079-45e7-99aa-3fccdeed75d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228352196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.3228352196
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.3243503151
Short name T301
Test name
Test status
Simulation time 616889009048 ps
CPU time 650.08 seconds
Started Jun 27 07:07:16 PM PDT 24
Finished Jun 27 07:18:10 PM PDT 24
Peak memory 201836 kb
Host smart-2806fb2a-3f93-4767-be25-7fb9c3936563
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243503151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.3243503151
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.2645768976
Short name T270
Test name
Test status
Simulation time 164885949419 ps
CPU time 184.06 seconds
Started Jun 27 07:07:27 PM PDT 24
Finished Jun 27 07:10:33 PM PDT 24
Peak memory 201888 kb
Host smart-2724e4cb-1429-421b-a1df-4990c522cdb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645768976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2645768976
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.1143020153
Short name T182
Test name
Test status
Simulation time 552953560577 ps
CPU time 155.7 seconds
Started Jun 27 07:08:49 PM PDT 24
Finished Jun 27 07:11:27 PM PDT 24
Peak memory 201888 kb
Host smart-dac76d14-e25f-4322-abf8-5534834cb4b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143020153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.1143020153
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.3160806287
Short name T187
Test name
Test status
Simulation time 254652857359 ps
CPU time 873.17 seconds
Started Jun 27 07:09:44 PM PDT 24
Finished Jun 27 07:24:19 PM PDT 24
Peak memory 202184 kb
Host smart-50b83687-77be-471b-879b-620032cc58a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160806287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.3160806287
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1833974904
Short name T223
Test name
Test status
Simulation time 88199115539 ps
CPU time 443.85 seconds
Started Jun 27 07:11:16 PM PDT 24
Finished Jun 27 07:18:43 PM PDT 24
Peak memory 202276 kb
Host smart-45de7897-2919-4e00-b3da-8544fc18d9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833974904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1833974904
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.4054175746
Short name T114
Test name
Test status
Simulation time 488287645901 ps
CPU time 1025.28 seconds
Started Jun 27 07:11:14 PM PDT 24
Finished Jun 27 07:28:21 PM PDT 24
Peak memory 201872 kb
Host smart-46fb953a-0d51-4c6a-8c2f-f509d37bee27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054175746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.4054175746
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1242541429
Short name T245
Test name
Test status
Simulation time 448409701598 ps
CPU time 1020.58 seconds
Started Jun 27 07:12:15 PM PDT 24
Finished Jun 27 07:30:35 PM PDT 24
Peak memory 201876 kb
Host smart-9db7b5f6-4f9f-4e45-86e7-70a4793fb022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242541429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1242541429
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.513324685
Short name T261
Test name
Test status
Simulation time 327237495078 ps
CPU time 197.86 seconds
Started Jun 27 07:06:58 PM PDT 24
Finished Jun 27 07:10:19 PM PDT 24
Peak memory 201724 kb
Host smart-1a77efef-6cc6-4904-8f6d-aee49c38ad66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513324685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.513324685
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.1312918147
Short name T357
Test name
Test status
Simulation time 146229934856 ps
CPU time 578.9 seconds
Started Jun 27 07:06:55 PM PDT 24
Finished Jun 27 07:16:37 PM PDT 24
Peak memory 202136 kb
Host smart-1e2a5422-d8ef-4e8c-add0-93baab3e21ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312918147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1312918147
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.1973599669
Short name T252
Test name
Test status
Simulation time 491094157259 ps
CPU time 1044.41 seconds
Started Jun 27 07:06:59 PM PDT 24
Finished Jun 27 07:24:26 PM PDT 24
Peak memory 201780 kb
Host smart-3c9bbb1e-0258-40fe-99c7-c4f53d979fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973599669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.1973599669
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2139735768
Short name T883
Test name
Test status
Simulation time 763912692 ps
CPU time 1.87 seconds
Started Jun 27 06:33:33 PM PDT 24
Finished Jun 27 06:33:37 PM PDT 24
Peak memory 201636 kb
Host smart-6a539891-5258-43fd-8c39-b9bf97a379ba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139735768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.2139735768
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.194777782
Short name T51
Test name
Test status
Simulation time 26584866329 ps
CPU time 29.22 seconds
Started Jun 27 06:33:39 PM PDT 24
Finished Jun 27 06:34:12 PM PDT 24
Peak memory 201860 kb
Host smart-c6176bed-d202-4d05-938a-3f95d4eeef06
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194777782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_b
ash.194777782
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.543913100
Short name T845
Test name
Test status
Simulation time 775742244 ps
CPU time 2.04 seconds
Started Jun 27 06:33:40 PM PDT 24
Finished Jun 27 06:33:46 PM PDT 24
Peak memory 201488 kb
Host smart-718cc95d-3c63-4cbb-a5d2-3fd25736be49
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543913100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_re
set.543913100
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1314503733
Short name T850
Test name
Test status
Simulation time 973705064 ps
CPU time 1.43 seconds
Started Jun 27 06:33:46 PM PDT 24
Finished Jun 27 06:33:51 PM PDT 24
Peak memory 201764 kb
Host smart-e8de466d-4279-495c-842c-56781a980e43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314503733 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1314503733
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1672431230
Short name T830
Test name
Test status
Simulation time 534211060 ps
CPU time 1.12 seconds
Started Jun 27 06:33:40 PM PDT 24
Finished Jun 27 06:33:45 PM PDT 24
Peak memory 201532 kb
Host smart-8e82c406-7bc4-48b9-8dee-7a24843647c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672431230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1672431230
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1429699401
Short name T804
Test name
Test status
Simulation time 555005492 ps
CPU time 0.98 seconds
Started Jun 27 06:33:40 PM PDT 24
Finished Jun 27 06:33:45 PM PDT 24
Peak memory 201412 kb
Host smart-0a6bb77c-ddd8-4d5d-9243-f53435fe614e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429699401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1429699401
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3715990881
Short name T849
Test name
Test status
Simulation time 2191991265 ps
CPU time 7.05 seconds
Started Jun 27 06:33:46 PM PDT 24
Finished Jun 27 06:33:56 PM PDT 24
Peak memory 201584 kb
Host smart-50d84824-0cbf-465c-b636-7e00a189f98c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715990881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.3715990881
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.4081167112
Short name T355
Test name
Test status
Simulation time 8380299086 ps
CPU time 11.44 seconds
Started Jun 27 06:33:40 PM PDT 24
Finished Jun 27 06:33:56 PM PDT 24
Peak memory 201796 kb
Host smart-1d861ebf-bf88-4dfc-8133-727503187f6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081167112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.4081167112
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.216060794
Short name T124
Test name
Test status
Simulation time 1267759921 ps
CPU time 3 seconds
Started Jun 27 06:33:42 PM PDT 24
Finished Jun 27 06:33:50 PM PDT 24
Peak memory 201676 kb
Host smart-4465e8fe-5f48-434d-82c6-2354e23ceefd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216060794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alias
ing.216060794
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.803498465
Short name T127
Test name
Test status
Simulation time 2199973921 ps
CPU time 4.82 seconds
Started Jun 27 06:33:44 PM PDT 24
Finished Jun 27 06:33:53 PM PDT 24
Peak memory 201804 kb
Host smart-fca1d111-8042-46a5-89c4-225bd47cd87f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803498465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_b
ash.803498465
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1039105825
Short name T862
Test name
Test status
Simulation time 701262669 ps
CPU time 1.28 seconds
Started Jun 27 06:33:44 PM PDT 24
Finished Jun 27 06:33:49 PM PDT 24
Peak memory 201488 kb
Host smart-610d4a96-0a5e-4cf7-b5d4-dff0f6cb414e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039105825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.1039105825
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1235582001
Short name T828
Test name
Test status
Simulation time 541470942 ps
CPU time 1.48 seconds
Started Jun 27 06:33:44 PM PDT 24
Finished Jun 27 06:33:50 PM PDT 24
Peak memory 201612 kb
Host smart-8d7eb1f3-52ad-45e2-8d02-ecc18a78bffd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235582001 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.1235582001
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.690759545
Short name T861
Test name
Test status
Simulation time 361309042 ps
CPU time 1.49 seconds
Started Jun 27 06:33:44 PM PDT 24
Finished Jun 27 06:33:49 PM PDT 24
Peak memory 201528 kb
Host smart-c0fd679b-f734-4660-b1a7-4f0b3a37981c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690759545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.690759545
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.4288198018
Short name T823
Test name
Test status
Simulation time 421020206 ps
CPU time 0.72 seconds
Started Jun 27 06:33:46 PM PDT 24
Finished Jun 27 06:33:50 PM PDT 24
Peak memory 201432 kb
Host smart-54332e0c-ab5f-43d0-b746-7ef85aad9e4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288198018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.4288198018
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2340718317
Short name T907
Test name
Test status
Simulation time 2400600479 ps
CPU time 6 seconds
Started Jun 27 06:33:43 PM PDT 24
Finished Jun 27 06:33:54 PM PDT 24
Peak memory 201664 kb
Host smart-cad01b44-7eb4-47c8-9f03-78494f4f20ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340718317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.2340718317
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.139617793
Short name T69
Test name
Test status
Simulation time 616958164 ps
CPU time 2.27 seconds
Started Jun 27 06:33:40 PM PDT 24
Finished Jun 27 06:33:47 PM PDT 24
Peak memory 201840 kb
Host smart-d763ea2b-fa49-4ce8-ba83-7491ae3f0705
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139617793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.139617793
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2097444342
Short name T60
Test name
Test status
Simulation time 532216743 ps
CPU time 1.21 seconds
Started Jun 27 06:33:45 PM PDT 24
Finished Jun 27 06:33:50 PM PDT 24
Peak memory 201512 kb
Host smart-ea1c1c73-ef2d-460a-973f-81685ef40e43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097444342 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.2097444342
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1013365158
Short name T129
Test name
Test status
Simulation time 322536166 ps
CPU time 1.06 seconds
Started Jun 27 06:33:42 PM PDT 24
Finished Jun 27 06:33:48 PM PDT 24
Peak memory 201476 kb
Host smart-f20192ec-dfa1-4b7f-b1bc-1dde995d466c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013365158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.1013365158
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1848246179
Short name T818
Test name
Test status
Simulation time 353140606 ps
CPU time 0.88 seconds
Started Jun 27 06:33:39 PM PDT 24
Finished Jun 27 06:33:43 PM PDT 24
Peak memory 201436 kb
Host smart-22e44af6-d126-4e7f-a236-a4c6bf20792f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848246179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.1848246179
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1846768967
Short name T856
Test name
Test status
Simulation time 4166872443 ps
CPU time 3.31 seconds
Started Jun 27 06:33:44 PM PDT 24
Finished Jun 27 06:33:52 PM PDT 24
Peak memory 201780 kb
Host smart-f07ae220-8fc3-4c50-b292-b7ed0460cf2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846768967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.1846768967
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1690848146
Short name T838
Test name
Test status
Simulation time 523068437 ps
CPU time 3.24 seconds
Started Jun 27 06:33:45 PM PDT 24
Finished Jun 27 06:33:52 PM PDT 24
Peak memory 209888 kb
Host smart-c281a687-0ff6-42d5-ad3c-b1db9f70946b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690848146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.1690848146
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2253901734
Short name T62
Test name
Test status
Simulation time 4170134114 ps
CPU time 10.29 seconds
Started Jun 27 06:33:37 PM PDT 24
Finished Jun 27 06:33:51 PM PDT 24
Peak memory 201800 kb
Host smart-81704d6c-aa01-4f02-9038-2b6e8937e0ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253901734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.2253901734
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1568791133
Short name T875
Test name
Test status
Simulation time 526958167 ps
CPU time 1.51 seconds
Started Jun 27 06:33:30 PM PDT 24
Finished Jun 27 06:33:34 PM PDT 24
Peak memory 201552 kb
Host smart-18b5d638-e889-49ba-a300-9c7200ff7d41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568791133 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1568791133
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1462357112
Short name T917
Test name
Test status
Simulation time 374778428 ps
CPU time 1.03 seconds
Started Jun 27 06:33:38 PM PDT 24
Finished Jun 27 06:33:43 PM PDT 24
Peak memory 201400 kb
Host smart-2952b641-1c39-4717-9cb9-71b0886a4251
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462357112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1462357112
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2859110104
Short name T824
Test name
Test status
Simulation time 300228049 ps
CPU time 1.49 seconds
Started Jun 27 06:33:37 PM PDT 24
Finished Jun 27 06:33:41 PM PDT 24
Peak memory 201440 kb
Host smart-dcc86c48-4d80-44de-a770-caaf2878bff7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859110104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2859110104
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2788371062
Short name T908
Test name
Test status
Simulation time 2483902345 ps
CPU time 6.32 seconds
Started Jun 27 06:33:37 PM PDT 24
Finished Jun 27 06:33:47 PM PDT 24
Peak memory 201660 kb
Host smart-66fe8112-3745-4702-9e29-f3c82b1017a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788371062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2788371062
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3827914258
Short name T898
Test name
Test status
Simulation time 393020942 ps
CPU time 1.79 seconds
Started Jun 27 06:33:38 PM PDT 24
Finished Jun 27 06:33:43 PM PDT 24
Peak memory 201796 kb
Host smart-697461da-a67f-4ad6-8e7c-78a2cb90e675
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827914258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.3827914258
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.938602823
Short name T814
Test name
Test status
Simulation time 4314811391 ps
CPU time 4.18 seconds
Started Jun 27 06:33:38 PM PDT 24
Finished Jun 27 06:33:46 PM PDT 24
Peak memory 201872 kb
Host smart-35f022c1-d4a9-4ea7-8d34-cf7870d02b57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938602823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_in
tg_err.938602823
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4194223133
Short name T867
Test name
Test status
Simulation time 595357001 ps
CPU time 1.15 seconds
Started Jun 27 06:33:37 PM PDT 24
Finished Jun 27 06:33:41 PM PDT 24
Peak memory 201576 kb
Host smart-21b6f1d2-0b69-4ad4-bfe2-63c3515f1e47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194223133 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.4194223133
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1862459396
Short name T135
Test name
Test status
Simulation time 438525980 ps
CPU time 1.19 seconds
Started Jun 27 06:33:36 PM PDT 24
Finished Jun 27 06:33:40 PM PDT 24
Peak memory 201504 kb
Host smart-5d7635c8-34f6-4bd7-a442-65ec62e53bda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862459396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1862459396
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.942935281
Short name T811
Test name
Test status
Simulation time 344440445 ps
CPU time 1.39 seconds
Started Jun 27 06:33:37 PM PDT 24
Finished Jun 27 06:33:41 PM PDT 24
Peak memory 201436 kb
Host smart-52926c35-88ee-4403-9dd8-adee31fe1bb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942935281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.942935281
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.728708734
Short name T895
Test name
Test status
Simulation time 4981833267 ps
CPU time 6.66 seconds
Started Jun 27 06:33:30 PM PDT 24
Finished Jun 27 06:33:40 PM PDT 24
Peak memory 201840 kb
Host smart-ab33ce3d-069a-4f6a-a856-1e7989714857
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728708734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.728708734
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2982535758
Short name T864
Test name
Test status
Simulation time 407444946 ps
CPU time 2.54 seconds
Started Jun 27 06:33:38 PM PDT 24
Finished Jun 27 06:33:44 PM PDT 24
Peak memory 201792 kb
Host smart-2fd9247f-f1fc-4051-99fc-ca20eb03e2fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982535758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.2982535758
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3247313168
Short name T915
Test name
Test status
Simulation time 8129019542 ps
CPU time 10.94 seconds
Started Jun 27 06:33:42 PM PDT 24
Finished Jun 27 06:33:58 PM PDT 24
Peak memory 201796 kb
Host smart-cd4fbd21-cb35-4a48-b08c-c1eb5df7e111
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247313168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3247313168
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2358946273
Short name T815
Test name
Test status
Simulation time 448215133 ps
CPU time 1.75 seconds
Started Jun 27 06:34:06 PM PDT 24
Finished Jun 27 06:34:10 PM PDT 24
Peak memory 201572 kb
Host smart-013ec6d7-1f7d-47b2-bf4d-bd00be779ae8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358946273 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.2358946273
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.4243623192
Short name T134
Test name
Test status
Simulation time 679762476 ps
CPU time 0.89 seconds
Started Jun 27 06:34:04 PM PDT 24
Finished Jun 27 06:34:08 PM PDT 24
Peak memory 201516 kb
Host smart-c4de0eed-3f85-4802-ad34-31ca05bd3773
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243623192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.4243623192
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3752275476
Short name T844
Test name
Test status
Simulation time 331334816 ps
CPU time 1.05 seconds
Started Jun 27 06:34:03 PM PDT 24
Finished Jun 27 06:34:06 PM PDT 24
Peak memory 201432 kb
Host smart-6b025dd9-9427-4489-bd9d-7f5a2f625786
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752275476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3752275476
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2246695051
Short name T53
Test name
Test status
Simulation time 2694798471 ps
CPU time 2.5 seconds
Started Jun 27 06:34:05 PM PDT 24
Finished Jun 27 06:34:10 PM PDT 24
Peak memory 201836 kb
Host smart-f6bf984e-6bec-4302-95e4-ca2be8fb8875
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246695051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2246695051
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1983568105
Short name T884
Test name
Test status
Simulation time 8414794709 ps
CPU time 6.25 seconds
Started Jun 27 06:34:03 PM PDT 24
Finished Jun 27 06:34:10 PM PDT 24
Peak memory 201872 kb
Host smart-ab939b77-a058-4c3d-a425-f251f390a567
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983568105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1983568105
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1158348660
Short name T897
Test name
Test status
Simulation time 508488101 ps
CPU time 1.24 seconds
Started Jun 27 06:34:03 PM PDT 24
Finished Jun 27 06:34:06 PM PDT 24
Peak memory 201508 kb
Host smart-8bceaa9c-a156-47c8-82d6-a1d05a271cbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158348660 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.1158348660
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3233166255
Short name T860
Test name
Test status
Simulation time 443526814 ps
CPU time 1.31 seconds
Started Jun 27 06:34:03 PM PDT 24
Finished Jun 27 06:34:06 PM PDT 24
Peak memory 201520 kb
Host smart-6045f64d-6bda-4f83-961d-7a2b80c93d82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233166255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.3233166255
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2994338296
Short name T887
Test name
Test status
Simulation time 314329874 ps
CPU time 0.97 seconds
Started Jun 27 06:34:03 PM PDT 24
Finished Jun 27 06:34:05 PM PDT 24
Peak memory 201424 kb
Host smart-e15950fd-6726-44a5-8fa9-17e89ada9041
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994338296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2994338296
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2715522603
Short name T54
Test name
Test status
Simulation time 2629314562 ps
CPU time 1.81 seconds
Started Jun 27 06:34:04 PM PDT 24
Finished Jun 27 06:34:08 PM PDT 24
Peak memory 201640 kb
Host smart-ab9a7bda-d7ee-42a3-8fe9-1c1db3b46218
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715522603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2715522603
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.4211168274
Short name T827
Test name
Test status
Simulation time 987669115 ps
CPU time 2.81 seconds
Started Jun 27 06:34:04 PM PDT 24
Finished Jun 27 06:34:09 PM PDT 24
Peak memory 217668 kb
Host smart-5810edab-24f0-4ea4-ade6-4b3b6d77c764
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211168274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.4211168274
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3640812396
Short name T914
Test name
Test status
Simulation time 481116297 ps
CPU time 1.1 seconds
Started Jun 27 06:34:04 PM PDT 24
Finished Jun 27 06:34:07 PM PDT 24
Peak memory 201548 kb
Host smart-cb10cc74-10f9-4565-b9ca-697d6cec51b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640812396 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3640812396
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.4150715883
Short name T131
Test name
Test status
Simulation time 464070835 ps
CPU time 1.34 seconds
Started Jun 27 06:34:07 PM PDT 24
Finished Jun 27 06:34:11 PM PDT 24
Peak memory 201444 kb
Host smart-47040fa9-d8fb-4d12-8533-042b5325aaa0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150715883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.4150715883
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2852518112
Short name T803
Test name
Test status
Simulation time 366653211 ps
CPU time 1.12 seconds
Started Jun 27 06:34:04 PM PDT 24
Finished Jun 27 06:34:07 PM PDT 24
Peak memory 201632 kb
Host smart-c5cdb101-99f5-4cb2-a1b0-a0f148ec59e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852518112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.2852518112
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3337703362
Short name T872
Test name
Test status
Simulation time 2186517692 ps
CPU time 4.96 seconds
Started Jun 27 06:34:06 PM PDT 24
Finished Jun 27 06:34:13 PM PDT 24
Peak memory 201640 kb
Host smart-139c709a-0f27-41a5-bb6b-aeb42f700158
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337703362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.3337703362
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1987633746
Short name T892
Test name
Test status
Simulation time 547932455 ps
CPU time 2.74 seconds
Started Jun 27 06:34:05 PM PDT 24
Finished Jun 27 06:34:10 PM PDT 24
Peak memory 201768 kb
Host smart-379a21b1-b69b-4f65-bbdb-087aa035e106
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987633746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1987633746
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1853435039
Short name T831
Test name
Test status
Simulation time 4388411819 ps
CPU time 10.71 seconds
Started Jun 27 06:34:04 PM PDT 24
Finished Jun 27 06:34:16 PM PDT 24
Peak memory 201760 kb
Host smart-9eedbf2e-6657-43dc-9bc0-10325c627584
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853435039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.1853435039
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2203992490
Short name T821
Test name
Test status
Simulation time 573784755 ps
CPU time 2.09 seconds
Started Jun 27 06:34:04 PM PDT 24
Finished Jun 27 06:34:08 PM PDT 24
Peak memory 201580 kb
Host smart-4f049cfd-46bb-4695-93ed-27ca4ae068ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203992490 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2203992490
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3148320498
Short name T139
Test name
Test status
Simulation time 624936185 ps
CPU time 1.09 seconds
Started Jun 27 06:34:02 PM PDT 24
Finished Jun 27 06:34:04 PM PDT 24
Peak memory 201476 kb
Host smart-5088323f-65ed-498d-8165-0ab918392635
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148320498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3148320498
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2993202816
Short name T808
Test name
Test status
Simulation time 471142599 ps
CPU time 1.76 seconds
Started Jun 27 06:34:06 PM PDT 24
Finished Jun 27 06:34:10 PM PDT 24
Peak memory 201436 kb
Host smart-28ad5a05-72d5-4616-8d65-5562893a3bd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993202816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.2993202816
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.994480080
Short name T841
Test name
Test status
Simulation time 2764151634 ps
CPU time 4.04 seconds
Started Jun 27 06:34:06 PM PDT 24
Finished Jun 27 06:34:13 PM PDT 24
Peak memory 201636 kb
Host smart-1047cdf2-4239-4693-b374-0b5019fa6b04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994480080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c
trl_same_csr_outstanding.994480080
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.668680734
Short name T840
Test name
Test status
Simulation time 529556698 ps
CPU time 2.91 seconds
Started Jun 27 06:34:02 PM PDT 24
Finished Jun 27 06:34:06 PM PDT 24
Peak memory 201764 kb
Host smart-fdb05bb6-0e58-456e-8500-8debaa777059
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668680734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.668680734
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.4074048533
Short name T55
Test name
Test status
Simulation time 4268927314 ps
CPU time 12.1 seconds
Started Jun 27 06:34:05 PM PDT 24
Finished Jun 27 06:34:20 PM PDT 24
Peak memory 201760 kb
Host smart-22103243-ac3c-4914-804d-66d0d5505416
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074048533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.4074048533
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1097528480
Short name T879
Test name
Test status
Simulation time 579471608 ps
CPU time 1.37 seconds
Started Jun 27 06:34:03 PM PDT 24
Finished Jun 27 06:34:06 PM PDT 24
Peak memory 201572 kb
Host smart-c4f457d4-cb75-4776-81d9-d7cfa6aa1949
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097528480 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.1097528480
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1995978325
Short name T125
Test name
Test status
Simulation time 445496151 ps
CPU time 0.95 seconds
Started Jun 27 06:34:07 PM PDT 24
Finished Jun 27 06:34:10 PM PDT 24
Peak memory 201444 kb
Host smart-ff19013a-ed68-4c27-8b39-cc0aedb9f656
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995978325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1995978325
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.261433766
Short name T880
Test name
Test status
Simulation time 328568860 ps
CPU time 1.38 seconds
Started Jun 27 06:34:05 PM PDT 24
Finished Jun 27 06:34:09 PM PDT 24
Peak memory 201396 kb
Host smart-c12d72b2-c400-4096-844b-4a05e7672e52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261433766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.261433766
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3015872708
Short name T833
Test name
Test status
Simulation time 2061704752 ps
CPU time 3.17 seconds
Started Jun 27 06:34:05 PM PDT 24
Finished Jun 27 06:34:11 PM PDT 24
Peak memory 201528 kb
Host smart-caf7109b-b372-436a-ab97-fcc5d8f55893
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015872708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.3015872708
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2201039228
Short name T899
Test name
Test status
Simulation time 818642090 ps
CPU time 3.24 seconds
Started Jun 27 06:34:05 PM PDT 24
Finished Jun 27 06:34:11 PM PDT 24
Peak memory 218040 kb
Host smart-7ae310f8-a0c3-427c-a395-d90c22bbe7ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201039228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2201039228
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.180473977
Short name T77
Test name
Test status
Simulation time 8508488777 ps
CPU time 12.34 seconds
Started Jun 27 06:34:06 PM PDT 24
Finished Jun 27 06:34:21 PM PDT 24
Peak memory 201800 kb
Host smart-a7322d2d-77be-45ee-871e-26a8313e80df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180473977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_in
tg_err.180473977
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1707275060
Short name T909
Test name
Test status
Simulation time 576692759 ps
CPU time 1.68 seconds
Started Jun 27 06:34:04 PM PDT 24
Finished Jun 27 06:34:09 PM PDT 24
Peak memory 201508 kb
Host smart-29bbcfb2-37ea-4763-a751-b28a1b775e4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707275060 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.1707275060
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.939825761
Short name T893
Test name
Test status
Simulation time 360429824 ps
CPU time 1.02 seconds
Started Jun 27 06:34:08 PM PDT 24
Finished Jun 27 06:34:11 PM PDT 24
Peak memory 201448 kb
Host smart-f09e32b2-fda8-47f1-9d85-0e66c135f4e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939825761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.939825761
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3469712052
Short name T911
Test name
Test status
Simulation time 3905144720 ps
CPU time 13.5 seconds
Started Jun 27 06:34:03 PM PDT 24
Finished Jun 27 06:34:18 PM PDT 24
Peak memory 201884 kb
Host smart-40675c26-aa70-48dd-b134-07cc8977ade9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469712052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.3469712052
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.4153401560
Short name T813
Test name
Test status
Simulation time 574357623 ps
CPU time 3.66 seconds
Started Jun 27 06:34:04 PM PDT 24
Finished Jun 27 06:34:10 PM PDT 24
Peak memory 218032 kb
Host smart-6daad437-aae8-4785-9db2-e18f1ddbb5fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153401560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.4153401560
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3690486615
Short name T56
Test name
Test status
Simulation time 10112196311 ps
CPU time 3.97 seconds
Started Jun 27 06:34:02 PM PDT 24
Finished Jun 27 06:34:08 PM PDT 24
Peak memory 201828 kb
Host smart-139b955c-2078-4607-b70e-4c0fe09a83b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690486615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.3690486615
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2930900506
Short name T866
Test name
Test status
Simulation time 412537390 ps
CPU time 1.84 seconds
Started Jun 27 06:34:20 PM PDT 24
Finished Jun 27 06:34:26 PM PDT 24
Peak memory 201572 kb
Host smart-a212b3a3-d808-485c-8c46-46fbbb53f9df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930900506 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2930900506
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2710904204
Short name T903
Test name
Test status
Simulation time 698493867 ps
CPU time 0.95 seconds
Started Jun 27 06:34:18 PM PDT 24
Finished Jun 27 06:34:20 PM PDT 24
Peak memory 201508 kb
Host smart-3232f5ae-0515-4917-b19d-7f722b7ca504
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710904204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2710904204
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2716771784
Short name T848
Test name
Test status
Simulation time 436269679 ps
CPU time 0.92 seconds
Started Jun 27 06:34:06 PM PDT 24
Finished Jun 27 06:34:09 PM PDT 24
Peak memory 201452 kb
Host smart-ae2bec68-4449-479d-af87-3348da269976
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716771784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2716771784
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.416433377
Short name T873
Test name
Test status
Simulation time 2307505886 ps
CPU time 2.96 seconds
Started Jun 27 06:34:21 PM PDT 24
Finished Jun 27 06:34:30 PM PDT 24
Peak memory 201652 kb
Host smart-f7852b0d-c701-40b8-ae84-d002425b74ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416433377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.416433377
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3749189662
Short name T74
Test name
Test status
Simulation time 419057559 ps
CPU time 3.47 seconds
Started Jun 27 06:34:02 PM PDT 24
Finished Jun 27 06:34:07 PM PDT 24
Peak memory 201816 kb
Host smart-26c1c69e-a633-47d7-9987-79011c4d61bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749189662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3749189662
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2579650128
Short name T61
Test name
Test status
Simulation time 4794961248 ps
CPU time 4.07 seconds
Started Jun 27 06:34:03 PM PDT 24
Finished Jun 27 06:34:08 PM PDT 24
Peak memory 201836 kb
Host smart-d0710404-bc4a-44ac-bd23-b5690f279075
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579650128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.2579650128
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2730010171
Short name T138
Test name
Test status
Simulation time 830436996 ps
CPU time 2.03 seconds
Started Jun 27 06:33:42 PM PDT 24
Finished Jun 27 06:33:49 PM PDT 24
Peak memory 201656 kb
Host smart-03d068e4-1c63-49f4-8740-f89ca048a83f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730010171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.2730010171
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1890497824
Short name T122
Test name
Test status
Simulation time 45513007108 ps
CPU time 32 seconds
Started Jun 27 06:33:43 PM PDT 24
Finished Jun 27 06:34:19 PM PDT 24
Peak memory 201812 kb
Host smart-5747db6e-00c1-40e6-8581-8d838114e8a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890497824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.1890497824
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3732508193
Short name T894
Test name
Test status
Simulation time 781844569 ps
CPU time 1.78 seconds
Started Jun 27 06:33:42 PM PDT 24
Finished Jun 27 06:33:49 PM PDT 24
Peak memory 201476 kb
Host smart-e8a2cf27-f955-4453-997a-ad094fffd159
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732508193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.3732508193
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.309078867
Short name T853
Test name
Test status
Simulation time 521523858 ps
CPU time 1.86 seconds
Started Jun 27 06:33:45 PM PDT 24
Finished Jun 27 06:33:50 PM PDT 24
Peak memory 201512 kb
Host smart-0e22eaa3-9724-4a26-832d-ac2f9d086257
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309078867 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.309078867
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3088995317
Short name T119
Test name
Test status
Simulation time 448563079 ps
CPU time 1.68 seconds
Started Jun 27 06:33:46 PM PDT 24
Finished Jun 27 06:33:51 PM PDT 24
Peak memory 201380 kb
Host smart-ba434f3b-146f-4f27-8457-8633d0e30dea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088995317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3088995317
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1734907028
Short name T881
Test name
Test status
Simulation time 360601338 ps
CPU time 1.06 seconds
Started Jun 27 06:33:45 PM PDT 24
Finished Jun 27 06:33:50 PM PDT 24
Peak memory 201476 kb
Host smart-29a7538b-6210-43bb-b55a-2aab64dcac32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734907028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1734907028
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1450225969
Short name T900
Test name
Test status
Simulation time 4726465674 ps
CPU time 18.73 seconds
Started Jun 27 06:33:37 PM PDT 24
Finished Jun 27 06:33:58 PM PDT 24
Peak memory 201864 kb
Host smart-d2c822ce-c2c2-4288-aa42-c7b5e70935a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450225969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.1450225969
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1402829218
Short name T68
Test name
Test status
Simulation time 583950145 ps
CPU time 1.83 seconds
Started Jun 27 06:33:42 PM PDT 24
Finished Jun 27 06:33:49 PM PDT 24
Peak memory 201740 kb
Host smart-f96267e5-22d1-484e-989f-01091e28cd0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402829218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1402829218
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3905159086
Short name T876
Test name
Test status
Simulation time 8485229373 ps
CPU time 21.7 seconds
Started Jun 27 06:33:45 PM PDT 24
Finished Jun 27 06:34:10 PM PDT 24
Peak memory 201848 kb
Host smart-d26ca69a-4306-4571-84eb-c2569c179f1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905159086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.3905159086
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2950914328
Short name T869
Test name
Test status
Simulation time 466815809 ps
CPU time 1.77 seconds
Started Jun 27 06:34:23 PM PDT 24
Finished Jun 27 06:34:33 PM PDT 24
Peak memory 201424 kb
Host smart-29de1589-9e3a-4d61-9f26-29116944c3a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950914328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2950914328
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4245253147
Short name T809
Test name
Test status
Simulation time 305563569 ps
CPU time 1.38 seconds
Started Jun 27 06:34:22 PM PDT 24
Finished Jun 27 06:34:30 PM PDT 24
Peak memory 201368 kb
Host smart-1bab7a9b-95b0-4d59-8ff2-1fde38543c5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245253147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.4245253147
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3119235232
Short name T836
Test name
Test status
Simulation time 514070516 ps
CPU time 0.92 seconds
Started Jun 27 06:34:17 PM PDT 24
Finished Jun 27 06:34:20 PM PDT 24
Peak memory 201444 kb
Host smart-e0f4ff7f-06f2-43a2-83c0-84c40d66bbab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119235232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.3119235232
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3976964167
Short name T825
Test name
Test status
Simulation time 457405139 ps
CPU time 1.73 seconds
Started Jun 27 06:34:21 PM PDT 24
Finished Jun 27 06:34:28 PM PDT 24
Peak memory 201432 kb
Host smart-bbb43a02-7ad9-418e-a0ae-e08aaef9c3c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976964167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3976964167
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1970729550
Short name T870
Test name
Test status
Simulation time 417564401 ps
CPU time 0.84 seconds
Started Jun 27 06:34:21 PM PDT 24
Finished Jun 27 06:34:27 PM PDT 24
Peak memory 201452 kb
Host smart-b292ff32-9b57-4ffe-b5fc-cabd3aef072a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970729550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.1970729550
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.543617757
Short name T877
Test name
Test status
Simulation time 365898382 ps
CPU time 1.52 seconds
Started Jun 27 06:34:20 PM PDT 24
Finished Jun 27 06:34:26 PM PDT 24
Peak memory 201436 kb
Host smart-7d49650f-1424-4226-9fc1-11d5a35aa2b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543617757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.543617757
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1448591745
Short name T857
Test name
Test status
Simulation time 507725674 ps
CPU time 0.72 seconds
Started Jun 27 06:34:20 PM PDT 24
Finished Jun 27 06:34:24 PM PDT 24
Peak memory 201436 kb
Host smart-da33a1c3-3a53-4aa1-ad95-7784c8f6b546
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448591745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.1448591745
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.223855710
Short name T854
Test name
Test status
Simulation time 341422850 ps
CPU time 1.46 seconds
Started Jun 27 06:34:21 PM PDT 24
Finished Jun 27 06:34:27 PM PDT 24
Peak memory 201392 kb
Host smart-572a41a3-f721-4b96-9d73-63cd5e4f75bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223855710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.223855710
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1010391177
Short name T871
Test name
Test status
Simulation time 286115981 ps
CPU time 1.35 seconds
Started Jun 27 06:34:23 PM PDT 24
Finished Jun 27 06:34:32 PM PDT 24
Peak memory 201416 kb
Host smart-fa44a7e5-d6ea-4298-84c4-f3b146aa39ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010391177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.1010391177
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1454672853
Short name T902
Test name
Test status
Simulation time 403753800 ps
CPU time 1.5 seconds
Started Jun 27 06:34:13 PM PDT 24
Finished Jun 27 06:34:16 PM PDT 24
Peak memory 201432 kb
Host smart-d65c43d5-30f3-48ca-995e-4f87a01b3083
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454672853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1454672853
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2958773937
Short name T123
Test name
Test status
Simulation time 835635948 ps
CPU time 4.27 seconds
Started Jun 27 06:33:37 PM PDT 24
Finished Jun 27 06:33:44 PM PDT 24
Peak memory 201676 kb
Host smart-b2744e04-2c3a-40ed-9ee1-6ebc4e71aaff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958773937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2958773937
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3360390348
Short name T128
Test name
Test status
Simulation time 11349387828 ps
CPU time 26.7 seconds
Started Jun 27 06:33:37 PM PDT 24
Finished Jun 27 06:34:06 PM PDT 24
Peak memory 201832 kb
Host smart-62a448aa-9c0f-4b9a-8e98-f00c7a559e3a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360390348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3360390348
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3886474386
Short name T140
Test name
Test status
Simulation time 743986478 ps
CPU time 1.57 seconds
Started Jun 27 06:33:46 PM PDT 24
Finished Jun 27 06:33:51 PM PDT 24
Peak memory 201452 kb
Host smart-3569d3d0-05aa-4ffa-a2f4-58a0bd1640bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886474386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.3886474386
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.255205691
Short name T59
Test name
Test status
Simulation time 558794795 ps
CPU time 1.36 seconds
Started Jun 27 06:33:32 PM PDT 24
Finished Jun 27 06:33:35 PM PDT 24
Peak memory 201560 kb
Host smart-fb507061-6cb0-42c4-9e78-abb4fcc90e03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255205691 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.255205691
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1122707537
Short name T896
Test name
Test status
Simulation time 388880868 ps
CPU time 1.81 seconds
Started Jun 27 06:33:45 PM PDT 24
Finished Jun 27 06:33:50 PM PDT 24
Peak memory 201452 kb
Host smart-21801f7b-bd45-4c65-a342-9becc6a97820
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122707537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1122707537
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1226905356
Short name T851
Test name
Test status
Simulation time 352096293 ps
CPU time 0.82 seconds
Started Jun 27 06:33:39 PM PDT 24
Finished Jun 27 06:33:43 PM PDT 24
Peak memory 201424 kb
Host smart-b8a50ae4-3d26-41da-811f-9703a5946d3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226905356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.1226905356
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1473485024
Short name T882
Test name
Test status
Simulation time 2336826666 ps
CPU time 9.39 seconds
Started Jun 27 06:33:39 PM PDT 24
Finished Jun 27 06:33:53 PM PDT 24
Peak memory 201624 kb
Host smart-23f774ba-4e54-40f9-82d5-5dda29d81e65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473485024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.1473485024
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2830515241
Short name T822
Test name
Test status
Simulation time 535176657 ps
CPU time 1.68 seconds
Started Jun 27 06:33:45 PM PDT 24
Finished Jun 27 06:33:50 PM PDT 24
Peak memory 201752 kb
Host smart-c6d5b34d-62d5-42c6-b822-1f6d756b956d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830515241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2830515241
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1462722602
Short name T905
Test name
Test status
Simulation time 5007652301 ps
CPU time 13.19 seconds
Started Jun 27 06:33:45 PM PDT 24
Finished Jun 27 06:34:02 PM PDT 24
Peak memory 201760 kb
Host smart-b5a26a4c-c1ae-427b-8b28-7034b503b175
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462722602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.1462722602
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.4278458525
Short name T863
Test name
Test status
Simulation time 514704003 ps
CPU time 0.94 seconds
Started Jun 27 06:34:18 PM PDT 24
Finished Jun 27 06:34:20 PM PDT 24
Peak memory 201444 kb
Host smart-18a03cae-4a38-4c39-af63-46a9702b5c95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278458525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.4278458525
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.44096096
Short name T885
Test name
Test status
Simulation time 456516859 ps
CPU time 1.79 seconds
Started Jun 27 06:34:22 PM PDT 24
Finished Jun 27 06:34:31 PM PDT 24
Peak memory 201440 kb
Host smart-d5c7931e-cc7d-41a4-81b3-d1bae34425f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44096096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.44096096
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.112489068
Short name T820
Test name
Test status
Simulation time 431771600 ps
CPU time 1.57 seconds
Started Jun 27 06:34:18 PM PDT 24
Finished Jun 27 06:34:21 PM PDT 24
Peak memory 201412 kb
Host smart-aac14c89-5df6-4a0a-88dd-162371c63cf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112489068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.112489068
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2631900539
Short name T855
Test name
Test status
Simulation time 317513656 ps
CPU time 1.41 seconds
Started Jun 27 06:34:17 PM PDT 24
Finished Jun 27 06:34:20 PM PDT 24
Peak memory 201436 kb
Host smart-c4045a9d-be0b-4d28-9588-492025d9f23c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631900539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2631900539
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1081089525
Short name T878
Test name
Test status
Simulation time 547523908 ps
CPU time 0.88 seconds
Started Jun 27 06:34:22 PM PDT 24
Finished Jun 27 06:34:31 PM PDT 24
Peak memory 201436 kb
Host smart-f950754f-2734-4cb7-94a1-7e513bf92967
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081089525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1081089525
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1301650698
Short name T826
Test name
Test status
Simulation time 537847027 ps
CPU time 1.23 seconds
Started Jun 27 06:34:19 PM PDT 24
Finished Jun 27 06:34:22 PM PDT 24
Peak memory 201372 kb
Host smart-202f4e93-fb52-4c2f-86ec-1a782120c46d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301650698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1301650698
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1678426838
Short name T852
Test name
Test status
Simulation time 544074182 ps
CPU time 0.92 seconds
Started Jun 27 06:34:21 PM PDT 24
Finished Jun 27 06:34:26 PM PDT 24
Peak memory 201436 kb
Host smart-c08c32d6-c431-47c5-a275-a59fcd75c0bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678426838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.1678426838
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2827041048
Short name T832
Test name
Test status
Simulation time 346947918 ps
CPU time 1.37 seconds
Started Jun 27 06:34:21 PM PDT 24
Finished Jun 27 06:34:28 PM PDT 24
Peak memory 201344 kb
Host smart-f9e111d7-bc8e-43cd-a500-512a9e80b917
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827041048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.2827041048
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3501192947
Short name T843
Test name
Test status
Simulation time 358615039 ps
CPU time 0.79 seconds
Started Jun 27 06:34:22 PM PDT 24
Finished Jun 27 06:34:29 PM PDT 24
Peak memory 201440 kb
Host smart-90dfde51-71d3-4686-9138-e1f3044d2249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501192947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3501192947
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.285728465
Short name T819
Test name
Test status
Simulation time 500837307 ps
CPU time 1.12 seconds
Started Jun 27 06:34:22 PM PDT 24
Finished Jun 27 06:34:30 PM PDT 24
Peak memory 201440 kb
Host smart-a9d188e8-b5b3-454f-9056-06f60cdfeaa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285728465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.285728465
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.4268436654
Short name T117
Test name
Test status
Simulation time 965307499 ps
CPU time 4.51 seconds
Started Jun 27 06:33:38 PM PDT 24
Finished Jun 27 06:33:46 PM PDT 24
Peak memory 201732 kb
Host smart-82ad0308-7e8f-4848-8c61-eaa5db634a93
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268436654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.4268436654
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2099156530
Short name T130
Test name
Test status
Simulation time 25956086808 ps
CPU time 35 seconds
Started Jun 27 06:33:37 PM PDT 24
Finished Jun 27 06:34:15 PM PDT 24
Peak memory 201860 kb
Host smart-f557304f-4b27-416c-9a75-94d54fb86a7c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099156530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2099156530
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.570211319
Short name T126
Test name
Test status
Simulation time 1477709022 ps
CPU time 1.77 seconds
Started Jun 27 06:33:39 PM PDT 24
Finished Jun 27 06:33:45 PM PDT 24
Peak memory 201500 kb
Host smart-46d988c3-ebad-4401-baed-2b17c15640f9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570211319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_re
set.570211319
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.4068123809
Short name T842
Test name
Test status
Simulation time 437259253 ps
CPU time 1.97 seconds
Started Jun 27 06:33:40 PM PDT 24
Finished Jun 27 06:33:46 PM PDT 24
Peak memory 201536 kb
Host smart-20371602-0ca1-498b-b60f-eb9df3ae35a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068123809 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.4068123809
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3883517631
Short name T132
Test name
Test status
Simulation time 364206552 ps
CPU time 1.69 seconds
Started Jun 27 06:33:38 PM PDT 24
Finished Jun 27 06:33:43 PM PDT 24
Peak memory 201436 kb
Host smart-77f9b749-6218-42c6-9f25-b14c3751db8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883517631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3883517631
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.616986966
Short name T865
Test name
Test status
Simulation time 402807791 ps
CPU time 0.77 seconds
Started Jun 27 06:33:38 PM PDT 24
Finished Jun 27 06:33:42 PM PDT 24
Peak memory 201328 kb
Host smart-a0ee787d-1cd7-4493-a991-4246f9e1b840
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616986966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.616986966
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3491832824
Short name T137
Test name
Test status
Simulation time 2877524822 ps
CPU time 6.88 seconds
Started Jun 27 06:33:39 PM PDT 24
Finished Jun 27 06:33:50 PM PDT 24
Peak memory 201792 kb
Host smart-cc8bed3a-3c31-441c-bfa3-87cfec228171
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491832824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.3491832824
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2375225638
Short name T920
Test name
Test status
Simulation time 548652844 ps
CPU time 2.64 seconds
Started Jun 27 06:33:32 PM PDT 24
Finished Jun 27 06:33:37 PM PDT 24
Peak memory 201828 kb
Host smart-cba01a6d-3bf5-4521-9aaa-f116f9856ef9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375225638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2375225638
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1083661905
Short name T859
Test name
Test status
Simulation time 8894054018 ps
CPU time 19.96 seconds
Started Jun 27 06:33:38 PM PDT 24
Finished Jun 27 06:34:01 PM PDT 24
Peak memory 201772 kb
Host smart-d5189a9e-ad46-4165-bf4a-aa005ca4d4b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083661905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.1083661905
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.4164793017
Short name T816
Test name
Test status
Simulation time 502529459 ps
CPU time 1.87 seconds
Started Jun 27 06:34:22 PM PDT 24
Finished Jun 27 06:34:32 PM PDT 24
Peak memory 201420 kb
Host smart-6ec2834d-da6c-4363-b6ff-ce18830c792e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164793017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.4164793017
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3414757449
Short name T868
Test name
Test status
Simulation time 339997637 ps
CPU time 1.35 seconds
Started Jun 27 06:34:20 PM PDT 24
Finished Jun 27 06:34:25 PM PDT 24
Peak memory 201424 kb
Host smart-51a4c9ca-6b31-4621-9569-5e627be818fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414757449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.3414757449
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3090973401
Short name T837
Test name
Test status
Simulation time 386671062 ps
CPU time 0.88 seconds
Started Jun 27 06:34:18 PM PDT 24
Finished Jun 27 06:34:21 PM PDT 24
Peak memory 201456 kb
Host smart-afb7e140-7e3f-4bbe-85b6-b77e553ee195
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090973401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.3090973401
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2780994326
Short name T829
Test name
Test status
Simulation time 525967772 ps
CPU time 1.39 seconds
Started Jun 27 06:34:22 PM PDT 24
Finished Jun 27 06:34:30 PM PDT 24
Peak memory 201452 kb
Host smart-b9c5cd2e-79cb-4e2e-a8e5-9abc560ab59b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780994326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2780994326
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2915947692
Short name T810
Test name
Test status
Simulation time 306329108 ps
CPU time 1.06 seconds
Started Jun 27 06:34:23 PM PDT 24
Finished Jun 27 06:34:31 PM PDT 24
Peak memory 201416 kb
Host smart-c8d26d3c-a163-43e1-a927-86e978a5aff0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915947692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2915947692
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2192972300
Short name T834
Test name
Test status
Simulation time 405907816 ps
CPU time 0.95 seconds
Started Jun 27 06:34:22 PM PDT 24
Finished Jun 27 06:34:31 PM PDT 24
Peak memory 201368 kb
Host smart-48885832-9adc-4fe8-b44e-0535c4b4738f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192972300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2192972300
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.800270183
Short name T805
Test name
Test status
Simulation time 417814046 ps
CPU time 1.59 seconds
Started Jun 27 06:34:16 PM PDT 24
Finished Jun 27 06:34:19 PM PDT 24
Peak memory 201436 kb
Host smart-5df2d50e-45b9-41e9-b5b7-e778a7641853
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800270183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.800270183
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.4017403175
Short name T847
Test name
Test status
Simulation time 392515020 ps
CPU time 1.13 seconds
Started Jun 27 06:34:22 PM PDT 24
Finished Jun 27 06:34:30 PM PDT 24
Peak memory 201420 kb
Host smart-4243aaba-6159-4381-bb3c-6e76ec6c51a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017403175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.4017403175
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.393935345
Short name T888
Test name
Test status
Simulation time 419694659 ps
CPU time 0.91 seconds
Started Jun 27 06:34:20 PM PDT 24
Finished Jun 27 06:34:26 PM PDT 24
Peak memory 201388 kb
Host smart-9cdede48-d2f4-407d-9489-a5b438391b00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393935345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.393935345
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.499020272
Short name T806
Test name
Test status
Simulation time 552591889 ps
CPU time 0.72 seconds
Started Jun 27 06:34:17 PM PDT 24
Finished Jun 27 06:34:18 PM PDT 24
Peak memory 201620 kb
Host smart-ee4c5fb7-1067-405a-8a55-3b3b6b0918fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499020272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.499020272
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3492762876
Short name T73
Test name
Test status
Simulation time 546522470 ps
CPU time 1.3 seconds
Started Jun 27 06:33:46 PM PDT 24
Finished Jun 27 06:33:51 PM PDT 24
Peak memory 201568 kb
Host smart-84aa0021-3014-48dc-ad1f-bc06ab69e09c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492762876 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.3492762876
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3508333777
Short name T136
Test name
Test status
Simulation time 317600914 ps
CPU time 1.47 seconds
Started Jun 27 06:33:39 PM PDT 24
Finished Jun 27 06:33:45 PM PDT 24
Peak memory 201476 kb
Host smart-a2c44b2b-e5ff-421d-9873-740b46b91a27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508333777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3508333777
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1114684758
Short name T889
Test name
Test status
Simulation time 416263692 ps
CPU time 0.87 seconds
Started Jun 27 06:33:39 PM PDT 24
Finished Jun 27 06:33:43 PM PDT 24
Peak memory 201436 kb
Host smart-76a9320e-4088-4148-85c0-6c34012d3729
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114684758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1114684758
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2965743721
Short name T133
Test name
Test status
Simulation time 4932574294 ps
CPU time 7.08 seconds
Started Jun 27 06:33:40 PM PDT 24
Finished Jun 27 06:33:51 PM PDT 24
Peak memory 201792 kb
Host smart-b6f25a18-45aa-48a9-b2aa-5f14c5115a18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965743721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.2965743721
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.302943410
Short name T890
Test name
Test status
Simulation time 480013539 ps
CPU time 1.46 seconds
Started Jun 27 06:33:39 PM PDT 24
Finished Jun 27 06:33:44 PM PDT 24
Peak memory 201528 kb
Host smart-6db941a1-0e67-43db-8510-99b76fd043b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302943410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.302943410
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3439568523
Short name T78
Test name
Test status
Simulation time 4098830213 ps
CPU time 4.05 seconds
Started Jun 27 06:33:39 PM PDT 24
Finished Jun 27 06:33:48 PM PDT 24
Peak memory 201816 kb
Host smart-64c709ae-690c-481a-8d23-e4d625e175cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439568523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3439568523
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3444703657
Short name T912
Test name
Test status
Simulation time 479903607 ps
CPU time 1.44 seconds
Started Jun 27 06:33:45 PM PDT 24
Finished Jun 27 06:33:50 PM PDT 24
Peak memory 212080 kb
Host smart-3e3a7c15-df8d-499a-a630-880c131683c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444703657 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.3444703657
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.937707349
Short name T919
Test name
Test status
Simulation time 351802183 ps
CPU time 0.95 seconds
Started Jun 27 06:33:39 PM PDT 24
Finished Jun 27 06:33:43 PM PDT 24
Peak memory 201488 kb
Host smart-0e23b081-b211-4dd3-999e-0e33abebb64f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937707349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.937707349
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1759245970
Short name T901
Test name
Test status
Simulation time 449832605 ps
CPU time 0.93 seconds
Started Jun 27 06:33:39 PM PDT 24
Finished Jun 27 06:33:44 PM PDT 24
Peak memory 201416 kb
Host smart-c4a5698f-0a52-468d-a756-044ce430ad9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759245970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1759245970
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.803442348
Short name T891
Test name
Test status
Simulation time 2624297921 ps
CPU time 9.64 seconds
Started Jun 27 06:33:39 PM PDT 24
Finished Jun 27 06:33:54 PM PDT 24
Peak memory 201656 kb
Host smart-ded5c7d1-022d-4541-93e4-106db033d5cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803442348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ct
rl_same_csr_outstanding.803442348
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.932100254
Short name T906
Test name
Test status
Simulation time 527316739 ps
CPU time 2.56 seconds
Started Jun 27 06:33:39 PM PDT 24
Finished Jun 27 06:33:46 PM PDT 24
Peak memory 201788 kb
Host smart-6bc3df71-1c99-45d1-8b09-ea1a72ed6fcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932100254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.932100254
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2943885899
Short name T910
Test name
Test status
Simulation time 8414465157 ps
CPU time 14.02 seconds
Started Jun 27 06:33:39 PM PDT 24
Finished Jun 27 06:33:57 PM PDT 24
Peak memory 201832 kb
Host smart-26d6adb8-0c93-47c7-9770-2cc4845b918d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943885899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.2943885899
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.917237966
Short name T75
Test name
Test status
Simulation time 398540813 ps
CPU time 1.08 seconds
Started Jun 27 06:33:46 PM PDT 24
Finished Jun 27 06:33:50 PM PDT 24
Peak memory 201432 kb
Host smart-b025797d-30a8-4d61-8d60-3a3f7b03ba31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917237966 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.917237966
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3254808454
Short name T141
Test name
Test status
Simulation time 434501320 ps
CPU time 1.66 seconds
Started Jun 27 06:33:44 PM PDT 24
Finished Jun 27 06:33:49 PM PDT 24
Peak memory 201528 kb
Host smart-7d05a26a-4981-4692-baaf-4d8c13984ea7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254808454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3254808454
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.132129561
Short name T858
Test name
Test status
Simulation time 351544211 ps
CPU time 1.25 seconds
Started Jun 27 06:33:39 PM PDT 24
Finished Jun 27 06:33:44 PM PDT 24
Peak memory 201452 kb
Host smart-941c3973-d16f-4072-9abc-a3877e963dd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132129561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.132129561
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.196531340
Short name T835
Test name
Test status
Simulation time 3028756375 ps
CPU time 9.68 seconds
Started Jun 27 06:33:41 PM PDT 24
Finished Jun 27 06:33:55 PM PDT 24
Peak memory 201584 kb
Host smart-9b448d3c-03e3-4c37-8ef3-3999306af5e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196531340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ct
rl_same_csr_outstanding.196531340
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.722731431
Short name T67
Test name
Test status
Simulation time 587537686 ps
CPU time 3.24 seconds
Started Jun 27 06:33:46 PM PDT 24
Finished Jun 27 06:33:52 PM PDT 24
Peak memory 201756 kb
Host smart-5fa5d9dd-9d19-4a08-88f6-770b7c997d8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722731431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.722731431
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2161476813
Short name T817
Test name
Test status
Simulation time 4173275346 ps
CPU time 11.48 seconds
Started Jun 27 06:33:39 PM PDT 24
Finished Jun 27 06:33:55 PM PDT 24
Peak memory 201872 kb
Host smart-a61e6301-922c-4a36-b423-702327c44c81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161476813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2161476813
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.956553564
Short name T918
Test name
Test status
Simulation time 480232985 ps
CPU time 1.83 seconds
Started Jun 27 06:33:44 PM PDT 24
Finished Jun 27 06:33:50 PM PDT 24
Peak memory 201600 kb
Host smart-204bc95e-5990-4294-b307-f236ceaea4d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956553564 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.956553564
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2343956443
Short name T118
Test name
Test status
Simulation time 422187748 ps
CPU time 1.05 seconds
Started Jun 27 06:33:44 PM PDT 24
Finished Jun 27 06:33:49 PM PDT 24
Peak memory 201444 kb
Host smart-d53174a2-4156-4942-80ab-9719817355fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343956443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2343956443
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1373765150
Short name T839
Test name
Test status
Simulation time 347853085 ps
CPU time 0.87 seconds
Started Jun 27 06:33:44 PM PDT 24
Finished Jun 27 06:33:49 PM PDT 24
Peak memory 201352 kb
Host smart-ef893def-54b1-424a-9a2b-46a883e26635
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373765150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1373765150
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1573406715
Short name T904
Test name
Test status
Simulation time 544248781 ps
CPU time 2.46 seconds
Started Jun 27 06:33:42 PM PDT 24
Finished Jun 27 06:33:49 PM PDT 24
Peak memory 209940 kb
Host smart-cf4fe1f6-d93a-471c-a264-b59637a5a742
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573406715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1573406715
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1109230204
Short name T874
Test name
Test status
Simulation time 8469833777 ps
CPU time 4.25 seconds
Started Jun 27 06:33:44 PM PDT 24
Finished Jun 27 06:33:52 PM PDT 24
Peak memory 201892 kb
Host smart-51f7c632-4c43-4d4a-8ed7-cca088e036e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109230204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1109230204
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3037646
Short name T913
Test name
Test status
Simulation time 562044148 ps
CPU time 2.33 seconds
Started Jun 27 06:33:33 PM PDT 24
Finished Jun 27 06:33:38 PM PDT 24
Peak memory 201576 kb
Host smart-9d773808-1f76-474e-883d-e6252811faf1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037646 -assert nopostproc +UVM_TESTNAME=ad
c_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.3037646
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4106468075
Short name T120
Test name
Test status
Simulation time 385466696 ps
CPU time 1.15 seconds
Started Jun 27 06:33:43 PM PDT 24
Finished Jun 27 06:33:49 PM PDT 24
Peak memory 201544 kb
Host smart-8747ecda-a3dc-45f5-a004-96e518f93f04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106468075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.4106468075
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.405193781
Short name T807
Test name
Test status
Simulation time 419194387 ps
CPU time 1.13 seconds
Started Jun 27 06:33:44 PM PDT 24
Finished Jun 27 06:33:49 PM PDT 24
Peak memory 201400 kb
Host smart-caf61dd5-a361-44b2-9c2a-771d24b2f5be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405193781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.405193781
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2067120870
Short name T916
Test name
Test status
Simulation time 4582329613 ps
CPU time 10.06 seconds
Started Jun 27 06:33:44 PM PDT 24
Finished Jun 27 06:33:58 PM PDT 24
Peak memory 201848 kb
Host smart-77c57e4f-608b-4cdc-81d7-7489cb737dd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067120870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2067120870
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2187329871
Short name T846
Test name
Test status
Simulation time 504731413 ps
CPU time 1.56 seconds
Started Jun 27 06:33:43 PM PDT 24
Finished Jun 27 06:33:49 PM PDT 24
Peak memory 201728 kb
Host smart-292294ec-5203-49b5-940b-1a46094a562e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187329871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2187329871
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.936668555
Short name T886
Test name
Test status
Simulation time 5202246338 ps
CPU time 3.36 seconds
Started Jun 27 06:33:48 PM PDT 24
Finished Jun 27 06:33:54 PM PDT 24
Peak memory 201812 kb
Host smart-7bf90ca4-8809-4d46-922c-86733922638c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936668555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_int
g_err.936668555
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.3957330887
Short name T584
Test name
Test status
Simulation time 384745173 ps
CPU time 0.86 seconds
Started Jun 27 07:06:40 PM PDT 24
Finished Jun 27 07:06:50 PM PDT 24
Peak memory 201660 kb
Host smart-3bb4e145-5c75-4a92-adca-d85ec3c3b724
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957330887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.3957330887
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.1398834851
Short name T263
Test name
Test status
Simulation time 163913171128 ps
CPU time 190.13 seconds
Started Jun 27 07:06:39 PM PDT 24
Finished Jun 27 07:09:56 PM PDT 24
Peak memory 201880 kb
Host smart-5ed40834-7a7c-44ac-8ac0-da4f9eb1a82a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398834851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.1398834851
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.2519079885
Short name T689
Test name
Test status
Simulation time 323402398733 ps
CPU time 187.69 seconds
Started Jun 27 07:06:40 PM PDT 24
Finished Jun 27 07:09:57 PM PDT 24
Peak memory 201968 kb
Host smart-3fb96f4c-f97e-4741-8c83-7542d625c972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519079885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.2519079885
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.4087276238
Short name T282
Test name
Test status
Simulation time 497496419514 ps
CPU time 1119.43 seconds
Started Jun 27 07:06:33 PM PDT 24
Finished Jun 27 07:25:15 PM PDT 24
Peak memory 201844 kb
Host smart-9edffbd2-fc27-49fc-8ba9-13f6bad22d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087276238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.4087276238
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2413669453
Short name T367
Test name
Test status
Simulation time 324087827703 ps
CPU time 766.27 seconds
Started Jun 27 07:06:39 PM PDT 24
Finished Jun 27 07:19:34 PM PDT 24
Peak memory 201840 kb
Host smart-03bd3e97-4d34-4348-a1d0-f704ed3158cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413669453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.2413669453
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.3386648810
Short name T169
Test name
Test status
Simulation time 333169006042 ps
CPU time 810.79 seconds
Started Jun 27 07:06:40 PM PDT 24
Finished Jun 27 07:20:20 PM PDT 24
Peak memory 201892 kb
Host smart-443a7cb4-bd62-4088-91c8-ca68ead9208b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386648810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.3386648810
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3329070777
Short name T413
Test name
Test status
Simulation time 326607887761 ps
CPU time 110.46 seconds
Started Jun 27 07:06:37 PM PDT 24
Finished Jun 27 07:08:33 PM PDT 24
Peak memory 201792 kb
Host smart-295884b4-ebe1-4732-9c2a-fff9e8d47ea0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329070777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3329070777
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.2568208997
Short name T284
Test name
Test status
Simulation time 350738719070 ps
CPU time 196.54 seconds
Started Jun 27 07:06:38 PM PDT 24
Finished Jun 27 07:10:02 PM PDT 24
Peak memory 201944 kb
Host smart-e512c27c-5102-4714-9eef-9737d48de4d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568208997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.2568208997
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2226008564
Short name T461
Test name
Test status
Simulation time 421738895109 ps
CPU time 878.89 seconds
Started Jun 27 07:06:34 PM PDT 24
Finished Jun 27 07:21:15 PM PDT 24
Peak memory 201852 kb
Host smart-ce1fbf7d-d048-4009-9bb1-3453f5c73ac1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226008564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2226008564
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.4118333441
Short name T511
Test name
Test status
Simulation time 112783931293 ps
CPU time 448.63 seconds
Started Jun 27 07:06:39 PM PDT 24
Finished Jun 27 07:14:16 PM PDT 24
Peak memory 202272 kb
Host smart-153fc7e4-1351-4647-986f-143a251c671b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118333441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.4118333441
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.988242026
Short name T567
Test name
Test status
Simulation time 22427389567 ps
CPU time 27.92 seconds
Started Jun 27 07:06:35 PM PDT 24
Finished Jun 27 07:07:07 PM PDT 24
Peak memory 201660 kb
Host smart-1805eb73-6616-45a3-81e0-17b5d1b30347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988242026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.988242026
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.1040249185
Short name T364
Test name
Test status
Simulation time 4989600611 ps
CPU time 2.78 seconds
Started Jun 27 07:06:39 PM PDT 24
Finished Jun 27 07:06:50 PM PDT 24
Peak memory 201656 kb
Host smart-b8713d0a-03eb-46ea-ac33-63830c25ab84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040249185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.1040249185
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.758564040
Short name T81
Test name
Test status
Simulation time 4769945784 ps
CPU time 11.4 seconds
Started Jun 27 07:06:37 PM PDT 24
Finished Jun 27 07:06:53 PM PDT 24
Peak memory 217076 kb
Host smart-1cdf843d-bbe1-41df-8198-223f08a1ff0f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758564040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.758564040
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.245909604
Short name T458
Test name
Test status
Simulation time 5691339803 ps
CPU time 4.44 seconds
Started Jun 27 07:06:33 PM PDT 24
Finished Jun 27 07:06:40 PM PDT 24
Peak memory 201668 kb
Host smart-844edbc2-ddd1-4d3e-8b44-346a3ff04113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245909604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.245909604
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.616189776
Short name T771
Test name
Test status
Simulation time 81276023411 ps
CPU time 371.93 seconds
Started Jun 27 07:06:36 PM PDT 24
Finished Jun 27 07:12:53 PM PDT 24
Peak memory 202144 kb
Host smart-988bfa79-02c1-4c16-a2d9-208cca2b4688
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616189776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.616189776
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.4156193083
Short name T751
Test name
Test status
Simulation time 138990605867 ps
CPU time 268.59 seconds
Started Jun 27 07:06:38 PM PDT 24
Finished Jun 27 07:11:13 PM PDT 24
Peak memory 210576 kb
Host smart-1467aa35-7eb9-4969-8418-27fa65ef7c3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156193083 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.4156193083
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2203491730
Short name T71
Test name
Test status
Simulation time 526228819 ps
CPU time 1.88 seconds
Started Jun 27 07:06:33 PM PDT 24
Finished Jun 27 07:06:38 PM PDT 24
Peak memory 201580 kb
Host smart-998958a3-08f4-4978-b85b-3ca07c51f609
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203491730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2203491730
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.3946279170
Short name T336
Test name
Test status
Simulation time 163457013958 ps
CPU time 376.15 seconds
Started Jun 27 07:06:42 PM PDT 24
Finished Jun 27 07:13:07 PM PDT 24
Peak memory 201888 kb
Host smart-c8f91948-2f9c-492f-b116-a95f51320fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946279170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3946279170
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.4078273733
Short name T498
Test name
Test status
Simulation time 332090736340 ps
CPU time 182.98 seconds
Started Jun 27 07:06:39 PM PDT 24
Finished Jun 27 07:09:50 PM PDT 24
Peak memory 201820 kb
Host smart-17733b9c-f7af-480e-98fa-c35e4b7b5df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078273733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.4078273733
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2350291258
Short name T113
Test name
Test status
Simulation time 323014372787 ps
CPU time 761.46 seconds
Started Jun 27 07:06:37 PM PDT 24
Finished Jun 27 07:19:24 PM PDT 24
Peak memory 201820 kb
Host smart-e5ac5c9b-6758-4669-8bd1-7261a57c7813
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350291258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.2350291258
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.3152530271
Short name T494
Test name
Test status
Simulation time 165694996998 ps
CPU time 101.92 seconds
Started Jun 27 07:06:43 PM PDT 24
Finished Jun 27 07:08:34 PM PDT 24
Peak memory 201864 kb
Host smart-0af41b0d-466c-4535-921c-a2ac2a3f26f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152530271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.3152530271
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2720309687
Short name T599
Test name
Test status
Simulation time 167562478017 ps
CPU time 106.56 seconds
Started Jun 27 07:06:37 PM PDT 24
Finished Jun 27 07:08:29 PM PDT 24
Peak memory 201868 kb
Host smart-e6e53362-0023-41c8-aaf4-2ca3f495d1a2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720309687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2720309687
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1629985007
Short name T758
Test name
Test status
Simulation time 186481659511 ps
CPU time 426.8 seconds
Started Jun 27 07:06:39 PM PDT 24
Finished Jun 27 07:13:54 PM PDT 24
Peak memory 201904 kb
Host smart-9dc6e478-8924-4026-87bc-a3229d50c0f6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629985007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1629985007
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1708998970
Short name T515
Test name
Test status
Simulation time 597491919916 ps
CPU time 314.89 seconds
Started Jun 27 07:06:39 PM PDT 24
Finished Jun 27 07:12:02 PM PDT 24
Peak memory 201804 kb
Host smart-abf4daf6-3c42-4861-a590-d4248f8492eb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708998970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1708998970
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1203634935
Short name T49
Test name
Test status
Simulation time 113109588793 ps
CPU time 459.1 seconds
Started Jun 27 07:06:39 PM PDT 24
Finished Jun 27 07:14:27 PM PDT 24
Peak memory 202144 kb
Host smart-f24ac3ca-ee4d-4dcc-9452-993202aa3e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203634935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1203634935
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.1398830022
Short name T449
Test name
Test status
Simulation time 40069045412 ps
CPU time 23.53 seconds
Started Jun 27 07:06:37 PM PDT 24
Finished Jun 27 07:07:06 PM PDT 24
Peak memory 201604 kb
Host smart-d33a1e67-257a-4861-90ac-376a15c6acfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398830022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1398830022
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.284475378
Short name T653
Test name
Test status
Simulation time 2850734472 ps
CPU time 3.63 seconds
Started Jun 27 07:06:42 PM PDT 24
Finished Jun 27 07:06:55 PM PDT 24
Peak memory 201688 kb
Host smart-b4536062-afea-4d71-9dc1-b51dcc1c5c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284475378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.284475378
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.1151742518
Short name T519
Test name
Test status
Simulation time 5681966184 ps
CPU time 6.74 seconds
Started Jun 27 07:06:37 PM PDT 24
Finished Jun 27 07:06:50 PM PDT 24
Peak memory 201624 kb
Host smart-fce95ead-2d47-4916-86d1-8ddc16308b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151742518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.1151742518
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.2508972611
Short name T331
Test name
Test status
Simulation time 326808787908 ps
CPU time 657.26 seconds
Started Jun 27 07:06:39 PM PDT 24
Finished Jun 27 07:17:44 PM PDT 24
Peak memory 201880 kb
Host smart-7309dbe5-f0a2-4b3c-9b5c-c96c467906c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508972611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
2508972611
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.239394807
Short name T700
Test name
Test status
Simulation time 208050460268 ps
CPU time 127.53 seconds
Started Jun 27 07:06:40 PM PDT 24
Finished Jun 27 07:08:56 PM PDT 24
Peak memory 210204 kb
Host smart-27767a6e-78fd-4d67-a821-ca74c5efe441
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239394807 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.239394807
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1601968901
Short name T100
Test name
Test status
Simulation time 554268868 ps
CPU time 1.04 seconds
Started Jun 27 07:07:00 PM PDT 24
Finished Jun 27 07:07:04 PM PDT 24
Peak memory 201572 kb
Host smart-cf6490ff-1a42-425a-afb1-7fdfcbc3b84c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601968901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1601968901
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.1985377964
Short name T800
Test name
Test status
Simulation time 443667535974 ps
CPU time 90.81 seconds
Started Jun 27 07:06:57 PM PDT 24
Finished Jun 27 07:08:31 PM PDT 24
Peak memory 201720 kb
Host smart-b8a70d47-3dff-4be5-ab99-1f887693af24
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985377964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.1985377964
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.4051595746
Short name T334
Test name
Test status
Simulation time 505855041744 ps
CPU time 542.51 seconds
Started Jun 27 07:06:56 PM PDT 24
Finished Jun 27 07:16:02 PM PDT 24
Peak memory 201812 kb
Host smart-8e06c54b-7133-46b3-8ce7-3b064169cc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051595746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.4051595746
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3294798085
Short name T779
Test name
Test status
Simulation time 166764670519 ps
CPU time 377.21 seconds
Started Jun 27 07:06:56 PM PDT 24
Finished Jun 27 07:13:17 PM PDT 24
Peak memory 201812 kb
Host smart-19f411aa-6495-44ca-95ff-00b0732a175c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294798085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3294798085
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.926096953
Short name T184
Test name
Test status
Simulation time 493916328680 ps
CPU time 273.98 seconds
Started Jun 27 07:06:59 PM PDT 24
Finished Jun 27 07:11:36 PM PDT 24
Peak memory 201760 kb
Host smart-c34d014c-3cc9-4bf1-811a-09d6cf3e0d1c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=926096953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrup
t_fixed.926096953
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.530949191
Short name T756
Test name
Test status
Simulation time 328766949625 ps
CPU time 384.37 seconds
Started Jun 27 07:06:57 PM PDT 24
Finished Jun 27 07:13:25 PM PDT 24
Peak memory 201720 kb
Host smart-edda7c1e-86f6-4edb-89f5-57cd499b5a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530949191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.530949191
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1445836076
Short name T671
Test name
Test status
Simulation time 493361486397 ps
CPU time 1097.47 seconds
Started Jun 27 07:06:58 PM PDT 24
Finished Jun 27 07:25:19 PM PDT 24
Peak memory 201744 kb
Host smart-61fe5e40-d3db-4a1c-95e5-c03aaa362577
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445836076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1445836076
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.953818826
Short name T604
Test name
Test status
Simulation time 200715551962 ps
CPU time 436.6 seconds
Started Jun 27 07:06:56 PM PDT 24
Finished Jun 27 07:14:16 PM PDT 24
Peak memory 201756 kb
Host smart-45e506df-46a5-4791-b10a-d8a98294ff71
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953818826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.953818826
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.2311865998
Short name T219
Test name
Test status
Simulation time 63717858811 ps
CPU time 345.87 seconds
Started Jun 27 07:06:58 PM PDT 24
Finished Jun 27 07:12:47 PM PDT 24
Peak memory 202160 kb
Host smart-4478a3f5-8ad5-4b1e-865d-625b9a9fbc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311865998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2311865998
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.2936635405
Short name T643
Test name
Test status
Simulation time 26402621731 ps
CPU time 26.57 seconds
Started Jun 27 07:06:59 PM PDT 24
Finished Jun 27 07:07:28 PM PDT 24
Peak memory 201588 kb
Host smart-24edc167-6e7e-4e3d-b39e-3fe1744331cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936635405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.2936635405
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.1554765245
Short name T561
Test name
Test status
Simulation time 3895077032 ps
CPU time 9.24 seconds
Started Jun 27 07:06:59 PM PDT 24
Finished Jun 27 07:07:11 PM PDT 24
Peak memory 201592 kb
Host smart-886017a5-d5e9-45c3-9c39-a2edff62020a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554765245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.1554765245
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.1509499260
Short name T499
Test name
Test status
Simulation time 6021681055 ps
CPU time 2.35 seconds
Started Jun 27 07:06:57 PM PDT 24
Finished Jun 27 07:07:03 PM PDT 24
Peak memory 201680 kb
Host smart-16a73434-3b2c-4cbd-b7b2-639844712bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509499260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.1509499260
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.1397330144
Short name T677
Test name
Test status
Simulation time 45512171452 ps
CPU time 39.71 seconds
Started Jun 27 07:07:00 PM PDT 24
Finished Jun 27 07:07:42 PM PDT 24
Peak memory 201680 kb
Host smart-df658fba-6436-4389-8295-37245ab453c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397330144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.1397330144
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.2877818775
Short name T464
Test name
Test status
Simulation time 465922808 ps
CPU time 1.13 seconds
Started Jun 27 07:07:14 PM PDT 24
Finished Jun 27 07:07:19 PM PDT 24
Peak memory 201636 kb
Host smart-ae19ab75-02a0-42cb-94b4-ad4c44bb51d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877818775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.2877818775
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.1680390092
Short name T285
Test name
Test status
Simulation time 460030232873 ps
CPU time 358.69 seconds
Started Jun 27 07:07:00 PM PDT 24
Finished Jun 27 07:13:01 PM PDT 24
Peak memory 201804 kb
Host smart-d576a1ce-4dea-4203-b9e0-171ab9f4b20d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680390092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.1680390092
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.2926471474
Short name T259
Test name
Test status
Simulation time 167249218014 ps
CPU time 194.29 seconds
Started Jun 27 07:07:03 PM PDT 24
Finished Jun 27 07:10:18 PM PDT 24
Peak memory 201912 kb
Host smart-4f87cfe8-0581-42e3-8711-027404bf93a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926471474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2926471474
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.614844128
Short name T343
Test name
Test status
Simulation time 497178180529 ps
CPU time 1191.63 seconds
Started Jun 27 07:07:00 PM PDT 24
Finished Jun 27 07:26:54 PM PDT 24
Peak memory 201872 kb
Host smart-877ee97e-d033-435e-b464-8677e963410e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614844128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.614844128
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2884724452
Short name T693
Test name
Test status
Simulation time 329369666896 ps
CPU time 752.87 seconds
Started Jun 27 07:07:03 PM PDT 24
Finished Jun 27 07:19:37 PM PDT 24
Peak memory 201844 kb
Host smart-e11a3964-074d-4eff-bbc1-d1d38111b5b9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884724452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2884724452
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.3080662686
Short name T295
Test name
Test status
Simulation time 499568462255 ps
CPU time 542.38 seconds
Started Jun 27 07:07:01 PM PDT 24
Finished Jun 27 07:16:06 PM PDT 24
Peak memory 201892 kb
Host smart-a4ebb90b-ff6f-4dea-b933-48773ffda8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080662686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3080662686
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.1305491111
Short name T202
Test name
Test status
Simulation time 168006084985 ps
CPU time 64.25 seconds
Started Jun 27 07:07:00 PM PDT 24
Finished Jun 27 07:08:07 PM PDT 24
Peak memory 201844 kb
Host smart-023fa570-8546-400c-9718-e6700ae09d4a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305491111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.1305491111
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.150490788
Short name T556
Test name
Test status
Simulation time 37172482428 ps
CPU time 83.78 seconds
Started Jun 27 07:07:15 PM PDT 24
Finished Jun 27 07:08:43 PM PDT 24
Peak memory 201652 kb
Host smart-5464d8c7-91d7-4e54-8d94-7edb9c91101a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150490788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.150490788
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.295194036
Short name T402
Test name
Test status
Simulation time 2768928159 ps
CPU time 3.21 seconds
Started Jun 27 07:07:15 PM PDT 24
Finished Jun 27 07:07:22 PM PDT 24
Peak memory 201648 kb
Host smart-5fbbfe9f-1a02-4fb2-913b-0e117e96ff04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295194036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.295194036
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.4226331540
Short name T537
Test name
Test status
Simulation time 6053324461 ps
CPU time 7.89 seconds
Started Jun 27 07:06:59 PM PDT 24
Finished Jun 27 07:07:10 PM PDT 24
Peak memory 201676 kb
Host smart-85204e4b-69b5-4487-9b66-2a9a5cf85939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226331540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.4226331540
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.859390552
Short name T353
Test name
Test status
Simulation time 504906478983 ps
CPU time 502.26 seconds
Started Jun 27 07:07:15 PM PDT 24
Finished Jun 27 07:15:42 PM PDT 24
Peak memory 201956 kb
Host smart-d1743281-d4a6-4127-83ee-eb932ef4bdc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859390552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.
859390552
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.2533969378
Short name T754
Test name
Test status
Simulation time 389700696 ps
CPU time 1.1 seconds
Started Jun 27 07:07:13 PM PDT 24
Finished Jun 27 07:07:16 PM PDT 24
Peak memory 201632 kb
Host smart-5547d272-347c-4846-9c01-15d6c01b0029
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533969378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2533969378
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.3207187309
Short name T504
Test name
Test status
Simulation time 198493249818 ps
CPU time 436.42 seconds
Started Jun 27 07:07:14 PM PDT 24
Finished Jun 27 07:14:33 PM PDT 24
Peak memory 201884 kb
Host smart-33f7c1d9-d872-4dc1-a8a2-a3a35ce476d3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207187309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.3207187309
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.2672891803
Short name T273
Test name
Test status
Simulation time 364456458769 ps
CPU time 79.27 seconds
Started Jun 27 07:07:15 PM PDT 24
Finished Jun 27 07:08:39 PM PDT 24
Peak memory 201880 kb
Host smart-e2f63147-ac79-4ded-9282-a436437c2aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672891803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.2672891803
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.1233592422
Short name T648
Test name
Test status
Simulation time 162285228279 ps
CPU time 351.84 seconds
Started Jun 27 07:07:13 PM PDT 24
Finished Jun 27 07:13:06 PM PDT 24
Peak memory 201936 kb
Host smart-84f05872-c874-4de4-92b6-4c57e7d8de8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233592422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.1233592422
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1633064011
Short name T710
Test name
Test status
Simulation time 166665542038 ps
CPU time 397.04 seconds
Started Jun 27 07:07:14 PM PDT 24
Finished Jun 27 07:13:55 PM PDT 24
Peak memory 201788 kb
Host smart-028f6098-8871-45ec-8b96-a766fdb5c868
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633064011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1633064011
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.2897241364
Short name T208
Test name
Test status
Simulation time 500407978648 ps
CPU time 302.24 seconds
Started Jun 27 07:07:13 PM PDT 24
Finished Jun 27 07:12:17 PM PDT 24
Peak memory 201940 kb
Host smart-25455779-0376-47d2-9906-c8bf6f1f5f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897241364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2897241364
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1863219045
Short name T623
Test name
Test status
Simulation time 483546065879 ps
CPU time 144.43 seconds
Started Jun 27 07:07:14 PM PDT 24
Finished Jun 27 07:09:42 PM PDT 24
Peak memory 201852 kb
Host smart-ab1a6587-fca2-4e7e-8c4b-790ffaf08970
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863219045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1863219045
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1964748493
Short name T372
Test name
Test status
Simulation time 407348681633 ps
CPU time 508.87 seconds
Started Jun 27 07:07:13 PM PDT 24
Finished Jun 27 07:15:44 PM PDT 24
Peak memory 201860 kb
Host smart-bde2506b-12c8-4c7e-ab1e-47778913b134
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964748493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1964748493
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.3434350728
Short name T471
Test name
Test status
Simulation time 93571590451 ps
CPU time 496.47 seconds
Started Jun 27 07:07:15 PM PDT 24
Finished Jun 27 07:15:35 PM PDT 24
Peak memory 202276 kb
Host smart-a7536aa0-ac7b-4225-820c-3b844d4dba51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434350728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.3434350728
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.1487364183
Short name T427
Test name
Test status
Simulation time 22772656104 ps
CPU time 10.73 seconds
Started Jun 27 07:07:15 PM PDT 24
Finished Jun 27 07:07:29 PM PDT 24
Peak memory 201896 kb
Host smart-8b5b0ecc-cf30-49e7-b6b4-c2f727b31e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487364183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.1487364183
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2407103903
Short name T84
Test name
Test status
Simulation time 3250585826 ps
CPU time 1.43 seconds
Started Jun 27 07:07:14 PM PDT 24
Finished Jun 27 07:07:19 PM PDT 24
Peak memory 201684 kb
Host smart-d0b1c296-eb78-4da7-a5de-caf31326123e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407103903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2407103903
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.1767556430
Short name T389
Test name
Test status
Simulation time 5871727170 ps
CPU time 15.75 seconds
Started Jun 27 07:07:15 PM PDT 24
Finished Jun 27 07:07:35 PM PDT 24
Peak memory 201652 kb
Host smart-52fb06ae-ec16-4bdc-a5d0-04b2f8510742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767556430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1767556430
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.518419506
Short name T39
Test name
Test status
Simulation time 429994110487 ps
CPU time 289.44 seconds
Started Jun 27 07:07:19 PM PDT 24
Finished Jun 27 07:12:11 PM PDT 24
Peak memory 210824 kb
Host smart-4599352a-6dc2-4959-84b2-f1e2a278c9ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518419506 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.518419506
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.215607834
Short name T420
Test name
Test status
Simulation time 353292878 ps
CPU time 1.47 seconds
Started Jun 27 07:07:15 PM PDT 24
Finished Jun 27 07:07:20 PM PDT 24
Peak memory 201612 kb
Host smart-95c331da-85c6-4023-95f5-e7ab98c95ae1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215607834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.215607834
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.4102652904
Short name T327
Test name
Test status
Simulation time 179762225803 ps
CPU time 205.29 seconds
Started Jun 27 07:07:14 PM PDT 24
Finished Jun 27 07:10:43 PM PDT 24
Peak memory 201884 kb
Host smart-baa817f3-2e10-491f-af27-b5c420f2f811
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102652904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.4102652904
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3850625726
Short name T349
Test name
Test status
Simulation time 161748590400 ps
CPU time 186.39 seconds
Started Jun 27 07:07:15 PM PDT 24
Finished Jun 27 07:10:25 PM PDT 24
Peak memory 201872 kb
Host smart-2f8bee8b-e626-4c43-8b97-281ae84f3274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850625726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3850625726
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.3381206493
Short name T619
Test name
Test status
Simulation time 164147184631 ps
CPU time 314.09 seconds
Started Jun 27 07:07:15 PM PDT 24
Finished Jun 27 07:12:33 PM PDT 24
Peak memory 201876 kb
Host smart-f79dc857-2800-4d85-ae21-ed24a2c8461e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381206493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3381206493
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.2671688161
Short name T161
Test name
Test status
Simulation time 160040135193 ps
CPU time 34.25 seconds
Started Jun 27 07:07:17 PM PDT 24
Finished Jun 27 07:07:55 PM PDT 24
Peak memory 201796 kb
Host smart-000bf425-a28a-4f41-8035-5f5e26e9188a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671688161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.2671688161
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3191273772
Short name T212
Test name
Test status
Simulation time 324498061640 ps
CPU time 379.11 seconds
Started Jun 27 07:07:14 PM PDT 24
Finished Jun 27 07:13:36 PM PDT 24
Peak memory 201884 kb
Host smart-7b3d960d-7397-4cb0-9547-a0580fddc22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191273772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3191273772
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3580312539
Short name T725
Test name
Test status
Simulation time 495569301226 ps
CPU time 101.69 seconds
Started Jun 27 07:07:15 PM PDT 24
Finished Jun 27 07:09:01 PM PDT 24
Peak memory 202112 kb
Host smart-ec644941-cc3d-4f3f-80a4-e49114a71692
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580312539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3580312539
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.384776089
Short name T153
Test name
Test status
Simulation time 191742990364 ps
CPU time 409.72 seconds
Started Jun 27 07:07:13 PM PDT 24
Finished Jun 27 07:14:05 PM PDT 24
Peak memory 201884 kb
Host smart-20e3ee24-f658-47ff-be0d-7c9818eaee1c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384776089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_
wakeup.384776089
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.616268451
Short name T721
Test name
Test status
Simulation time 405547344914 ps
CPU time 188 seconds
Started Jun 27 07:07:14 PM PDT 24
Finished Jun 27 07:10:26 PM PDT 24
Peak memory 201892 kb
Host smart-d7552213-f89f-4649-bed8-dbdb5a7f07e4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616268451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
adc_ctrl_filters_wakeup_fixed.616268451
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2054206780
Short name T686
Test name
Test status
Simulation time 95342476281 ps
CPU time 385.23 seconds
Started Jun 27 07:07:17 PM PDT 24
Finished Jun 27 07:13:46 PM PDT 24
Peak memory 202240 kb
Host smart-a7129638-54ed-4b87-b7dc-0c4f9f53e43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054206780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2054206780
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3940816818
Short name T381
Test name
Test status
Simulation time 38124462087 ps
CPU time 23.31 seconds
Started Jun 27 07:07:14 PM PDT 24
Finished Jun 27 07:07:41 PM PDT 24
Peak memory 201620 kb
Host smart-eceb93b9-d171-4054-8c09-6b7bf75cacb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940816818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3940816818
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.1512120961
Short name T624
Test name
Test status
Simulation time 3826729531 ps
CPU time 3.06 seconds
Started Jun 27 07:07:15 PM PDT 24
Finished Jun 27 07:07:22 PM PDT 24
Peak memory 201688 kb
Host smart-2615bfa8-3527-4490-b863-8ae015660f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512120961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.1512120961
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.1269475930
Short name T200
Test name
Test status
Simulation time 5904356911 ps
CPU time 14.09 seconds
Started Jun 27 07:07:16 PM PDT 24
Finished Jun 27 07:07:34 PM PDT 24
Peak memory 201132 kb
Host smart-dd0353a6-945d-498e-a07c-0e421cc45222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269475930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.1269475930
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.2561284912
Short name T164
Test name
Test status
Simulation time 508363397062 ps
CPU time 256.31 seconds
Started Jun 27 07:07:14 PM PDT 24
Finished Jun 27 07:11:33 PM PDT 24
Peak memory 201876 kb
Host smart-f25d7bd7-67d5-4117-bb38-1baebfb72dc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561284912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.2561284912
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.546568984
Short name T16
Test name
Test status
Simulation time 32932734026 ps
CPU time 83.68 seconds
Started Jun 27 07:07:14 PM PDT 24
Finished Jun 27 07:08:42 PM PDT 24
Peak memory 210492 kb
Host smart-f17243fa-7ebb-49f1-8847-dea6fb4b25c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546568984 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.546568984
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.4291238646
Short name T507
Test name
Test status
Simulation time 599521328881 ps
CPU time 466.75 seconds
Started Jun 27 07:07:15 PM PDT 24
Finished Jun 27 07:15:05 PM PDT 24
Peak memory 201924 kb
Host smart-e26ea2f9-f4b3-493a-a076-93482cb6efe9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291238646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.4291238646
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.2948611152
Short name T191
Test name
Test status
Simulation time 543239686022 ps
CPU time 283.84 seconds
Started Jun 27 07:07:15 PM PDT 24
Finished Jun 27 07:12:02 PM PDT 24
Peak memory 201904 kb
Host smart-d9030071-f83f-4a41-bf8d-0fd0accca773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948611152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.2948611152
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.1031858358
Short name T548
Test name
Test status
Simulation time 163807437592 ps
CPU time 379.07 seconds
Started Jun 27 07:07:14 PM PDT 24
Finished Jun 27 07:13:37 PM PDT 24
Peak memory 201816 kb
Host smart-80b4e668-6aae-4050-b62f-e7dfda6e5dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031858358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.1031858358
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2482294275
Short name T488
Test name
Test status
Simulation time 159482476073 ps
CPU time 99.75 seconds
Started Jun 27 07:07:14 PM PDT 24
Finished Jun 27 07:08:58 PM PDT 24
Peak memory 201860 kb
Host smart-faa30ced-0b85-42e5-b4cd-c1ff7b70021d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482294275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2482294275
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1305475267
Short name T232
Test name
Test status
Simulation time 489055197507 ps
CPU time 303.38 seconds
Started Jun 27 07:07:17 PM PDT 24
Finished Jun 27 07:12:24 PM PDT 24
Peak memory 201776 kb
Host smart-71615988-b514-492a-9fb8-b0e90063f4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305475267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1305475267
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.1456878836
Short name T748
Test name
Test status
Simulation time 163819727788 ps
CPU time 100.88 seconds
Started Jun 27 07:07:14 PM PDT 24
Finished Jun 27 07:08:59 PM PDT 24
Peak memory 201828 kb
Host smart-af8e84a0-5e48-4ea3-a4eb-72aac6da6884
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456878836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.1456878836
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1912269068
Short name T425
Test name
Test status
Simulation time 203828130617 ps
CPU time 335.22 seconds
Started Jun 27 07:07:16 PM PDT 24
Finished Jun 27 07:12:55 PM PDT 24
Peak memory 201860 kb
Host smart-2518db79-9344-4e09-a1b2-919c47d94582
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912269068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1912269068
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.925494500
Short name T762
Test name
Test status
Simulation time 100344056785 ps
CPU time 329.43 seconds
Started Jun 27 07:07:18 PM PDT 24
Finished Jun 27 07:12:51 PM PDT 24
Peak memory 202204 kb
Host smart-bda1cdcd-762b-439b-85d6-af888c4e1a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925494500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.925494500
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.1339752484
Short name T793
Test name
Test status
Simulation time 30270906541 ps
CPU time 70.68 seconds
Started Jun 27 07:07:16 PM PDT 24
Finished Jun 27 07:08:30 PM PDT 24
Peak memory 201684 kb
Host smart-1b5e91a9-2baa-41ec-807e-8493bbb30f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339752484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1339752484
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.2434672807
Short name T477
Test name
Test status
Simulation time 5374576325 ps
CPU time 12.46 seconds
Started Jun 27 07:07:16 PM PDT 24
Finished Jun 27 07:07:33 PM PDT 24
Peak memory 201884 kb
Host smart-39715ae2-990c-4889-8f6b-7263f352d8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434672807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2434672807
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.849780061
Short name T745
Test name
Test status
Simulation time 5731095981 ps
CPU time 7.02 seconds
Started Jun 27 07:07:15 PM PDT 24
Finished Jun 27 07:07:26 PM PDT 24
Peak memory 201712 kb
Host smart-b3eca844-0f53-4bc0-bdc5-c34d2cacb960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849780061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.849780061
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.2254585865
Short name T36
Test name
Test status
Simulation time 50228929524 ps
CPU time 10.3 seconds
Started Jun 27 07:07:17 PM PDT 24
Finished Jun 27 07:07:31 PM PDT 24
Peak memory 210468 kb
Host smart-4ba3c259-5d01-455e-b910-9a44f2f2edd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254585865 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.2254585865
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1290831999
Short name T774
Test name
Test status
Simulation time 397392490 ps
CPU time 1.61 seconds
Started Jun 27 07:07:28 PM PDT 24
Finished Jun 27 07:07:32 PM PDT 24
Peak memory 201840 kb
Host smart-55da5d69-72a8-4620-b242-42fc81f77595
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290831999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1290831999
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2057179346
Short name T660
Test name
Test status
Simulation time 165612053047 ps
CPU time 15.28 seconds
Started Jun 27 07:07:26 PM PDT 24
Finished Jun 27 07:07:43 PM PDT 24
Peak memory 201824 kb
Host smart-9effe80f-7247-4402-a60a-e5de6a9aa5c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057179346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2057179346
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.1238995176
Short name T730
Test name
Test status
Simulation time 180278571515 ps
CPU time 43.48 seconds
Started Jun 27 07:07:30 PM PDT 24
Finished Jun 27 07:08:17 PM PDT 24
Peak memory 201900 kb
Host smart-b708f405-2ae5-4a6a-9761-9970607731ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238995176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.1238995176
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.2109047573
Short name T145
Test name
Test status
Simulation time 329922504372 ps
CPU time 722.89 seconds
Started Jun 27 07:07:26 PM PDT 24
Finished Jun 27 07:19:30 PM PDT 24
Peak memory 201896 kb
Host smart-7f8e8812-0a28-4d60-b7ad-db8e785cf327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109047573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.2109047573
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3707530189
Short name T369
Test name
Test status
Simulation time 486401533798 ps
CPU time 1180.75 seconds
Started Jun 27 07:07:26 PM PDT 24
Finished Jun 27 07:27:07 PM PDT 24
Peak memory 201856 kb
Host smart-c3d4ef28-5df5-47bf-9ae4-fea09e610cd3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707530189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.3707530189
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3923935250
Short name T347
Test name
Test status
Simulation time 163420538905 ps
CPU time 174.61 seconds
Started Jun 27 07:07:34 PM PDT 24
Finished Jun 27 07:10:30 PM PDT 24
Peak memory 201888 kb
Host smart-7c6ad1b0-0b2d-44ca-8c39-14a88bd8e442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923935250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3923935250
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.671648283
Short name T723
Test name
Test status
Simulation time 491976040317 ps
CPU time 446.31 seconds
Started Jun 27 07:07:27 PM PDT 24
Finished Jun 27 07:14:56 PM PDT 24
Peak memory 201812 kb
Host smart-f7bedc34-8e47-418d-b35e-3dd3ebb5fc0e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=671648283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixe
d.671648283
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3024871186
Short name T757
Test name
Test status
Simulation time 173191117201 ps
CPU time 371.63 seconds
Started Jun 27 07:07:31 PM PDT 24
Finished Jun 27 07:13:46 PM PDT 24
Peak memory 201716 kb
Host smart-f6c49d91-8ca3-4bf9-beb0-f575bbd288bb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024871186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3024871186
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3764172383
Short name T428
Test name
Test status
Simulation time 623151362559 ps
CPU time 451.38 seconds
Started Jun 27 07:07:29 PM PDT 24
Finished Jun 27 07:15:03 PM PDT 24
Peak memory 201640 kb
Host smart-47953d6e-003f-441c-bce3-bd4fc4639615
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764172383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3764172383
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.756912647
Short name T447
Test name
Test status
Simulation time 109854470016 ps
CPU time 535.28 seconds
Started Jun 27 07:07:28 PM PDT 24
Finished Jun 27 07:16:26 PM PDT 24
Peak memory 202188 kb
Host smart-ae00e8b1-d45a-474b-8178-663c81a3878c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756912647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.756912647
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3094975142
Short name T185
Test name
Test status
Simulation time 33834079371 ps
CPU time 13.84 seconds
Started Jun 27 07:07:35 PM PDT 24
Finished Jun 27 07:07:50 PM PDT 24
Peak memory 201616 kb
Host smart-5c166903-1de9-44e0-82d3-d5108db0739d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094975142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3094975142
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.1573589951
Short name T650
Test name
Test status
Simulation time 3616921372 ps
CPU time 2.79 seconds
Started Jun 27 07:07:28 PM PDT 24
Finished Jun 27 07:07:34 PM PDT 24
Peak memory 201884 kb
Host smart-055803b6-89e7-44b1-8ecd-169571401794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573589951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1573589951
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.4285720888
Short name T207
Test name
Test status
Simulation time 5695909929 ps
CPU time 12.93 seconds
Started Jun 27 07:07:26 PM PDT 24
Finished Jun 27 07:07:40 PM PDT 24
Peak memory 201660 kb
Host smart-603e35c6-a265-4388-9e3b-a78fca803532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285720888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.4285720888
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3576969711
Short name T21
Test name
Test status
Simulation time 145453013341 ps
CPU time 298.81 seconds
Started Jun 27 07:07:30 PM PDT 24
Finished Jun 27 07:12:32 PM PDT 24
Peak memory 211832 kb
Host smart-31f4fc98-5347-434d-af76-40d146f38680
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576969711 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3576969711
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.3960041417
Short name T727
Test name
Test status
Simulation time 325041387 ps
CPU time 0.76 seconds
Started Jun 27 07:08:21 PM PDT 24
Finished Jun 27 07:08:23 PM PDT 24
Peak memory 201472 kb
Host smart-6d48cb8f-d6b4-4249-adca-6e99aa088fdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960041417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3960041417
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.483299294
Short name T244
Test name
Test status
Simulation time 161320922769 ps
CPU time 102.15 seconds
Started Jun 27 07:07:30 PM PDT 24
Finished Jun 27 07:09:15 PM PDT 24
Peak memory 201908 kb
Host smart-5b6b8571-4c0f-46aa-952c-65ded867d00f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483299294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gati
ng.483299294
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3166790960
Short name T348
Test name
Test status
Simulation time 396715463639 ps
CPU time 895.52 seconds
Started Jun 27 07:07:28 PM PDT 24
Finished Jun 27 07:22:26 PM PDT 24
Peak memory 201892 kb
Host smart-216c8d52-4c01-4a96-bf76-ac1fc65277c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166790960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3166790960
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.211294049
Short name T642
Test name
Test status
Simulation time 321287713771 ps
CPU time 179.28 seconds
Started Jun 27 07:07:29 PM PDT 24
Finished Jun 27 07:10:31 PM PDT 24
Peak memory 201808 kb
Host smart-c670f73f-be9d-4def-ae7e-d78318ec9f5e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=211294049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrup
t_fixed.211294049
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.1073197298
Short name T8
Test name
Test status
Simulation time 334769612342 ps
CPU time 709.87 seconds
Started Jun 27 07:07:27 PM PDT 24
Finished Jun 27 07:19:18 PM PDT 24
Peak memory 201888 kb
Host smart-cfde7e4f-4e4f-48fb-b8e5-0496f017e5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073197298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1073197298
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1233925625
Short name T702
Test name
Test status
Simulation time 329983143093 ps
CPU time 368.06 seconds
Started Jun 27 07:07:26 PM PDT 24
Finished Jun 27 07:13:36 PM PDT 24
Peak memory 201876 kb
Host smart-c9ef47f6-3f86-48aa-a869-182ed0758a97
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233925625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1233925625
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.3584698014
Short name T541
Test name
Test status
Simulation time 415158174724 ps
CPU time 240.59 seconds
Started Jun 27 07:07:28 PM PDT 24
Finished Jun 27 07:11:31 PM PDT 24
Peak memory 201904 kb
Host smart-698b4fbf-0c72-4cc2-b271-5e6c6631d5f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584698014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.3584698014
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.982957311
Short name T188
Test name
Test status
Simulation time 214216818537 ps
CPU time 133.7 seconds
Started Jun 27 07:07:30 PM PDT 24
Finished Jun 27 07:09:47 PM PDT 24
Peak memory 201852 kb
Host smart-faad11a6-b843-4e79-81ce-4f88fcf6dc9f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982957311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
adc_ctrl_filters_wakeup_fixed.982957311
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.1046552353
Short name T543
Test name
Test status
Simulation time 98988165244 ps
CPU time 272.97 seconds
Started Jun 27 07:07:28 PM PDT 24
Finished Jun 27 07:12:04 PM PDT 24
Peak memory 202276 kb
Host smart-cdae9e32-d958-41b3-a261-e4565b52d8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046552353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.1046552353
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2445957238
Short name T478
Test name
Test status
Simulation time 40666010617 ps
CPU time 8.11 seconds
Started Jun 27 07:07:30 PM PDT 24
Finished Jun 27 07:07:41 PM PDT 24
Peak memory 201660 kb
Host smart-a795741e-60c1-4b40-a392-d7eddcb381a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445957238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2445957238
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.529048934
Short name T472
Test name
Test status
Simulation time 3709017902 ps
CPU time 9.54 seconds
Started Jun 27 07:07:28 PM PDT 24
Finished Jun 27 07:07:40 PM PDT 24
Peak memory 201676 kb
Host smart-acd5fc44-7535-4cc5-a893-a883eb998f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529048934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.529048934
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.2626863971
Short name T31
Test name
Test status
Simulation time 5916606911 ps
CPU time 5.07 seconds
Started Jun 27 07:07:30 PM PDT 24
Finished Jun 27 07:07:38 PM PDT 24
Peak memory 201656 kb
Host smart-07a6bae9-6769-4190-ad7e-981b1eb13bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626863971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.2626863971
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2193407273
Short name T486
Test name
Test status
Simulation time 532631367 ps
CPU time 0.93 seconds
Started Jun 27 07:07:36 PM PDT 24
Finished Jun 27 07:07:38 PM PDT 24
Peak memory 201628 kb
Host smart-c7305378-47c3-487c-a418-a2b4c26c00b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193407273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2193407273
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.3938485243
Short name T4
Test name
Test status
Simulation time 325943660569 ps
CPU time 180.19 seconds
Started Jun 27 07:07:30 PM PDT 24
Finished Jun 27 07:10:33 PM PDT 24
Peak memory 201864 kb
Host smart-685997ce-9568-4f01-9504-93008356262e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938485243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.3938485243
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1053241946
Short name T546
Test name
Test status
Simulation time 163848118861 ps
CPU time 275.74 seconds
Started Jun 27 07:07:29 PM PDT 24
Finished Jun 27 07:12:07 PM PDT 24
Peak memory 201856 kb
Host smart-fed15545-b1f8-443a-a751-c026db5fc789
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053241946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1053241946
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.3434484483
Short name T88
Test name
Test status
Simulation time 489818579537 ps
CPU time 287.87 seconds
Started Jun 27 07:07:28 PM PDT 24
Finished Jun 27 07:12:18 PM PDT 24
Peak memory 201864 kb
Host smart-f3faa012-ed24-41bd-a79b-ba55c523f180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434484483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.3434484483
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.1409617559
Short name T573
Test name
Test status
Simulation time 163932978192 ps
CPU time 400.36 seconds
Started Jun 27 07:07:36 PM PDT 24
Finished Jun 27 07:14:17 PM PDT 24
Peak memory 201916 kb
Host smart-1123d26e-9e71-4fcd-8bcb-57e05884746e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409617559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.1409617559
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.4103259462
Short name T637
Test name
Test status
Simulation time 203628816169 ps
CPU time 112.76 seconds
Started Jun 27 07:07:28 PM PDT 24
Finished Jun 27 07:09:23 PM PDT 24
Peak memory 201888 kb
Host smart-7815bafb-4aec-4c9d-aa47-287e566b022e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103259462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.4103259462
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.1147283629
Short name T99
Test name
Test status
Simulation time 394550832571 ps
CPU time 900.25 seconds
Started Jun 27 07:07:29 PM PDT 24
Finished Jun 27 07:22:32 PM PDT 24
Peak memory 201868 kb
Host smart-fae7cad2-1147-4dd0-b3c9-13eac3f5e5af
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147283629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.1147283629
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2004344388
Short name T789
Test name
Test status
Simulation time 95526085164 ps
CPU time 508.84 seconds
Started Jun 27 07:07:28 PM PDT 24
Finished Jun 27 07:16:00 PM PDT 24
Peak memory 202216 kb
Host smart-6843bd80-98ed-4508-8e52-4ed03e588b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004344388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2004344388
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.2790574193
Short name T521
Test name
Test status
Simulation time 27252287845 ps
CPU time 8.14 seconds
Started Jun 27 07:07:29 PM PDT 24
Finished Jun 27 07:07:40 PM PDT 24
Peak memory 201500 kb
Host smart-e72ca537-f1e5-4547-a7c6-318ee9b4c162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790574193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.2790574193
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1278550514
Short name T792
Test name
Test status
Simulation time 3591337619 ps
CPU time 2.74 seconds
Started Jun 27 07:07:30 PM PDT 24
Finished Jun 27 07:07:36 PM PDT 24
Peak memory 201684 kb
Host smart-ecf1e0f1-03a1-4344-81e2-87c56bfb1bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278550514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1278550514
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3906173799
Short name T705
Test name
Test status
Simulation time 6159934819 ps
CPU time 3.87 seconds
Started Jun 27 07:07:29 PM PDT 24
Finished Jun 27 07:07:36 PM PDT 24
Peak memory 201680 kb
Host smart-9c69b0d4-94a1-4fc7-af69-8abf763d5892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906173799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3906173799
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.1721659386
Short name T324
Test name
Test status
Simulation time 506318092134 ps
CPU time 264.57 seconds
Started Jun 27 07:07:30 PM PDT 24
Finished Jun 27 07:11:58 PM PDT 24
Peak memory 201872 kb
Host smart-e2289853-16b6-4e2d-9c4a-c2e15795aee2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721659386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.1721659386
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2610012553
Short name T89
Test name
Test status
Simulation time 98824613049 ps
CPU time 61.78 seconds
Started Jun 27 07:07:28 PM PDT 24
Finished Jun 27 07:08:33 PM PDT 24
Peak memory 210200 kb
Host smart-2419d18e-bd03-4a9b-94eb-475fc30b50b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610012553 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.2610012553
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.4080991103
Short name T646
Test name
Test status
Simulation time 353669354 ps
CPU time 0.84 seconds
Started Jun 27 07:07:29 PM PDT 24
Finished Jun 27 07:07:33 PM PDT 24
Peak memory 201596 kb
Host smart-89e97696-82fe-44c5-802d-8057c0ed403a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080991103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.4080991103
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.1545550493
Short name T97
Test name
Test status
Simulation time 348999175305 ps
CPU time 394.83 seconds
Started Jun 27 07:07:31 PM PDT 24
Finished Jun 27 07:14:09 PM PDT 24
Peak memory 201832 kb
Host smart-35c10f21-c47a-4c22-8651-ac8c83e83ba6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545550493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.1545550493
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2792780041
Short name T780
Test name
Test status
Simulation time 325537198516 ps
CPU time 700.29 seconds
Started Jun 27 07:07:32 PM PDT 24
Finished Jun 27 07:19:15 PM PDT 24
Peak memory 201852 kb
Host smart-87eb813a-108e-4bc6-a294-eeecbd855331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792780041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2792780041
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.4275278076
Short name T178
Test name
Test status
Simulation time 162526559402 ps
CPU time 372.55 seconds
Started Jun 27 07:07:35 PM PDT 24
Finished Jun 27 07:13:49 PM PDT 24
Peak memory 201880 kb
Host smart-dafe9527-cdcc-4a41-abad-4f0817af0604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275278076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.4275278076
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.3818729742
Short name T596
Test name
Test status
Simulation time 162689251726 ps
CPU time 383.44 seconds
Started Jun 27 07:07:35 PM PDT 24
Finished Jun 27 07:14:00 PM PDT 24
Peak memory 201752 kb
Host smart-eff4078a-f547-4591-bc68-929268bfe99a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818729742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.3818729742
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.866058996
Short name T741
Test name
Test status
Simulation time 161486759255 ps
CPU time 102.83 seconds
Started Jun 27 07:07:31 PM PDT 24
Finished Jun 27 07:09:17 PM PDT 24
Peak memory 201940 kb
Host smart-35ab593f-6d97-4fb7-8e30-3b1351ef7149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866058996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.866058996
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.1503267932
Short name T502
Test name
Test status
Simulation time 161461920173 ps
CPU time 133.87 seconds
Started Jun 27 07:07:31 PM PDT 24
Finished Jun 27 07:09:48 PM PDT 24
Peak memory 201704 kb
Host smart-2823fd60-eebb-4394-a666-b72ba380504c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503267932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.1503267932
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.2272600790
Short name T94
Test name
Test status
Simulation time 585117798858 ps
CPU time 1156.47 seconds
Started Jun 27 07:07:32 PM PDT 24
Finished Jun 27 07:26:51 PM PDT 24
Peak memory 201840 kb
Host smart-5da9f77a-05c9-489a-8b20-8314b675d3a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272600790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.2272600790
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.4248285626
Short name T591
Test name
Test status
Simulation time 399322756571 ps
CPU time 301.14 seconds
Started Jun 27 07:07:33 PM PDT 24
Finished Jun 27 07:12:36 PM PDT 24
Peak memory 201812 kb
Host smart-677a50ab-0e06-49b7-be8c-8cc87148e1a8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248285626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.4248285626
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3948646082
Short name T505
Test name
Test status
Simulation time 44198362128 ps
CPU time 26.07 seconds
Started Jun 27 07:07:30 PM PDT 24
Finished Jun 27 07:07:59 PM PDT 24
Peak memory 201688 kb
Host smart-a88db472-0c97-4753-b753-07a87d2a1858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948646082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3948646082
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.3288562727
Short name T704
Test name
Test status
Simulation time 3069638236 ps
CPU time 7.12 seconds
Started Jun 27 07:07:32 PM PDT 24
Finished Jun 27 07:07:41 PM PDT 24
Peak memory 201644 kb
Host smart-60fec9f5-ff73-4e60-a498-e92bb718c2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288562727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3288562727
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.1853371669
Short name T532
Test name
Test status
Simulation time 5539615526 ps
CPU time 4.24 seconds
Started Jun 27 07:07:27 PM PDT 24
Finished Jun 27 07:07:33 PM PDT 24
Peak memory 201676 kb
Host smart-06258c63-8104-4b88-b305-643bc05e5b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853371669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.1853371669
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.1800120010
Short name T589
Test name
Test status
Simulation time 322725499 ps
CPU time 0.94 seconds
Started Jun 27 07:07:44 PM PDT 24
Finished Jun 27 07:07:47 PM PDT 24
Peak memory 201656 kb
Host smart-adc18524-e860-43da-ac55-f6f3c01bb38d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800120010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1800120010
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.387769004
Short name T313
Test name
Test status
Simulation time 359595081343 ps
CPU time 217.68 seconds
Started Jun 27 07:07:41 PM PDT 24
Finished Jun 27 07:11:20 PM PDT 24
Peak memory 201884 kb
Host smart-e63c13cf-fda7-4153-bd98-453a14dea8a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387769004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gati
ng.387769004
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.446351401
Short name T271
Test name
Test status
Simulation time 409029475230 ps
CPU time 1004.2 seconds
Started Jun 27 07:07:42 PM PDT 24
Finished Jun 27 07:24:28 PM PDT 24
Peak memory 201824 kb
Host smart-a79ec55c-70b0-4d28-b0f4-cf5b84e5ae45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446351401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.446351401
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3383439891
Short name T644
Test name
Test status
Simulation time 332489953532 ps
CPU time 141.1 seconds
Started Jun 27 07:07:42 PM PDT 24
Finished Jun 27 07:10:05 PM PDT 24
Peak memory 201824 kb
Host smart-966c7c9f-2ead-4d98-a41c-407a1a57bcc1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383439891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.3383439891
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1741055387
Short name T443
Test name
Test status
Simulation time 169998175188 ps
CPU time 397.96 seconds
Started Jun 27 07:07:42 PM PDT 24
Finished Jun 27 07:14:22 PM PDT 24
Peak memory 201876 kb
Host smart-b4cdfb91-1b96-4e57-b8ad-7c94c97c8e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741055387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1741055387
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1965443060
Short name T559
Test name
Test status
Simulation time 322032005623 ps
CPU time 745.33 seconds
Started Jun 27 07:07:41 PM PDT 24
Finished Jun 27 07:20:07 PM PDT 24
Peak memory 201860 kb
Host smart-76489fc5-0e0b-4d81-925c-c0e47895e4a1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965443060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1965443060
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.4287478933
Short name T635
Test name
Test status
Simulation time 408205464196 ps
CPU time 697.43 seconds
Started Jun 27 07:07:42 PM PDT 24
Finished Jun 27 07:19:22 PM PDT 24
Peak memory 201836 kb
Host smart-106da346-5d63-449b-989a-f15a46d909e4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287478933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.4287478933
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.1592540036
Short name T755
Test name
Test status
Simulation time 84618677050 ps
CPU time 431.1 seconds
Started Jun 27 07:07:43 PM PDT 24
Finished Jun 27 07:14:56 PM PDT 24
Peak memory 202284 kb
Host smart-a91c4e1b-fb3d-4fe1-ab95-b8ccce18aa39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592540036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1592540036
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2731700952
Short name T742
Test name
Test status
Simulation time 27828137410 ps
CPU time 4.34 seconds
Started Jun 27 07:07:45 PM PDT 24
Finished Jun 27 07:07:51 PM PDT 24
Peak memory 201688 kb
Host smart-9fb3928b-763a-4b73-a66c-eaeafd953f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731700952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2731700952
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.2035841876
Short name T378
Test name
Test status
Simulation time 4751320937 ps
CPU time 11.69 seconds
Started Jun 27 07:07:42 PM PDT 24
Finished Jun 27 07:07:56 PM PDT 24
Peak memory 201684 kb
Host smart-93e36c00-a3fa-49ff-b644-3bdb6eb71153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035841876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2035841876
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1185793500
Short name T459
Test name
Test status
Simulation time 5971304857 ps
CPU time 14.37 seconds
Started Jun 27 07:07:30 PM PDT 24
Finished Jun 27 07:07:48 PM PDT 24
Peak memory 201624 kb
Host smart-4164a8b8-f570-4090-b901-b38843c7a5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185793500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1185793500
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.1748978089
Short name T527
Test name
Test status
Simulation time 166681609496 ps
CPU time 187.67 seconds
Started Jun 27 07:07:41 PM PDT 24
Finished Jun 27 07:10:50 PM PDT 24
Peak memory 201932 kb
Host smart-d8c2b22c-0611-440a-a28f-05e502664127
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748978089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.1748978089
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.3033709699
Short name T588
Test name
Test status
Simulation time 450752461 ps
CPU time 0.84 seconds
Started Jun 27 07:06:41 PM PDT 24
Finished Jun 27 07:06:51 PM PDT 24
Peak memory 201600 kb
Host smart-a67fb25f-a1a8-42b3-8ed7-3eab9428bee6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033709699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3033709699
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.4108012245
Short name T570
Test name
Test status
Simulation time 329896932587 ps
CPU time 337.34 seconds
Started Jun 27 07:06:39 PM PDT 24
Finished Jun 27 07:12:24 PM PDT 24
Peak memory 201840 kb
Host smart-980518fc-f46a-4fe3-839b-b893b244366b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108012245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.4108012245
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2109711643
Short name T467
Test name
Test status
Simulation time 327490314299 ps
CPU time 262.28 seconds
Started Jun 27 07:06:40 PM PDT 24
Finished Jun 27 07:11:11 PM PDT 24
Peak memory 201852 kb
Host smart-903adef0-8999-4326-8fee-4ef628742698
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109711643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.2109711643
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.2906604038
Short name T297
Test name
Test status
Simulation time 493592451090 ps
CPU time 223.64 seconds
Started Jun 27 07:06:40 PM PDT 24
Finished Jun 27 07:10:32 PM PDT 24
Peak memory 201896 kb
Host smart-8d75f6b1-8acc-46d1-8a8a-7351d299adff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906604038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.2906604038
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1201608971
Short name T199
Test name
Test status
Simulation time 320974578159 ps
CPU time 735.52 seconds
Started Jun 27 07:06:39 PM PDT 24
Finished Jun 27 07:19:02 PM PDT 24
Peak memory 201908 kb
Host smart-a74d0faf-01d4-4435-8cfb-9ce58b5b0497
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201608971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.1201608971
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.3541354530
Short name T333
Test name
Test status
Simulation time 173974292076 ps
CPU time 149.67 seconds
Started Jun 27 07:06:40 PM PDT 24
Finished Jun 27 07:09:19 PM PDT 24
Peak memory 201884 kb
Host smart-edd34213-64ef-4850-9e7e-fa0f1ba07829
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541354530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.3541354530
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2704306809
Short name T587
Test name
Test status
Simulation time 589274338990 ps
CPU time 685.48 seconds
Started Jun 27 07:06:40 PM PDT 24
Finished Jun 27 07:18:15 PM PDT 24
Peak memory 201804 kb
Host smart-d62649c0-e785-4b95-b31e-16ffa20b6422
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704306809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2704306809
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.2137013138
Short name T616
Test name
Test status
Simulation time 133735003121 ps
CPU time 532.32 seconds
Started Jun 27 07:06:41 PM PDT 24
Finished Jun 27 07:15:43 PM PDT 24
Peak memory 202188 kb
Host smart-b51e28f6-c48e-4f3a-83a2-737cd66532bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137013138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.2137013138
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2954235503
Short name T778
Test name
Test status
Simulation time 41892847117 ps
CPU time 12.52 seconds
Started Jun 27 07:06:41 PM PDT 24
Finished Jun 27 07:07:03 PM PDT 24
Peak memory 201696 kb
Host smart-dd82f3b4-b40b-4561-82fc-03145f803e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954235503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2954235503
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.904074452
Short name T629
Test name
Test status
Simulation time 2893691738 ps
CPU time 2.23 seconds
Started Jun 27 07:06:41 PM PDT 24
Finished Jun 27 07:06:53 PM PDT 24
Peak memory 201688 kb
Host smart-43879f0b-ad6a-4de3-8ff0-2d76b2645fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904074452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.904074452
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3704243210
Short name T80
Test name
Test status
Simulation time 8768679082 ps
CPU time 2.03 seconds
Started Jun 27 07:06:43 PM PDT 24
Finished Jun 27 07:06:54 PM PDT 24
Peak memory 218236 kb
Host smart-004bf1f6-6b0a-449f-a190-a774501fc25e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704243210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3704243210
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.1256047427
Short name T173
Test name
Test status
Simulation time 5826607130 ps
CPU time 15.47 seconds
Started Jun 27 07:06:37 PM PDT 24
Finished Jun 27 07:06:59 PM PDT 24
Peak memory 201616 kb
Host smart-03a62326-f506-4e9c-8713-b3d1793cbaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256047427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.1256047427
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.2919836988
Short name T307
Test name
Test status
Simulation time 176517223836 ps
CPU time 149.94 seconds
Started Jun 27 07:06:41 PM PDT 24
Finished Jun 27 07:09:20 PM PDT 24
Peak memory 210764 kb
Host smart-cc883a07-556b-4d99-84ac-4eb3a29330bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919836988 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.2919836988
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.2347662915
Short name T799
Test name
Test status
Simulation time 499789802 ps
CPU time 1.23 seconds
Started Jun 27 07:07:45 PM PDT 24
Finished Jun 27 07:07:48 PM PDT 24
Peak memory 201572 kb
Host smart-00001e03-694f-4aec-9d86-95c8d8e6a9a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347662915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2347662915
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3296163050
Short name T215
Test name
Test status
Simulation time 344975192263 ps
CPU time 160.04 seconds
Started Jun 27 07:07:42 PM PDT 24
Finished Jun 27 07:10:23 PM PDT 24
Peak memory 201724 kb
Host smart-45903f42-a884-4eee-8406-fb7f5be921ca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296163050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3296163050
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.255731810
Short name T610
Test name
Test status
Simulation time 491425182477 ps
CPU time 278.06 seconds
Started Jun 27 07:07:42 PM PDT 24
Finished Jun 27 07:12:22 PM PDT 24
Peak memory 201856 kb
Host smart-681d0d4a-7528-4d75-aacc-0c9a8a01dda8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=255731810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrup
t_fixed.255731810
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3410510575
Short name T311
Test name
Test status
Simulation time 498190305706 ps
CPU time 558.34 seconds
Started Jun 27 07:07:42 PM PDT 24
Finished Jun 27 07:17:03 PM PDT 24
Peak memory 201876 kb
Host smart-c1540d3e-ca38-44ba-b6e9-04474116e52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410510575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3410510575
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.3345991761
Short name T417
Test name
Test status
Simulation time 321603646126 ps
CPU time 226.42 seconds
Started Jun 27 07:07:43 PM PDT 24
Finished Jun 27 07:11:31 PM PDT 24
Peak memory 201816 kb
Host smart-77c9889a-22a0-4bf6-a74b-3da01244f5e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345991761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.3345991761
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.997014070
Short name T394
Test name
Test status
Simulation time 579026777427 ps
CPU time 1176.6 seconds
Started Jun 27 07:07:45 PM PDT 24
Finished Jun 27 07:27:23 PM PDT 24
Peak memory 201688 kb
Host smart-16ac21bf-cb53-4be4-9df3-d0da124e4b8c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997014070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
adc_ctrl_filters_wakeup_fixed.997014070
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2919747066
Short name T545
Test name
Test status
Simulation time 78916739955 ps
CPU time 437.15 seconds
Started Jun 27 07:07:44 PM PDT 24
Finished Jun 27 07:15:03 PM PDT 24
Peak memory 202168 kb
Host smart-f33ffe8b-aa42-430e-b36d-0f7d91b6e183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919747066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2919747066
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1879558165
Short name T701
Test name
Test status
Simulation time 25575606323 ps
CPU time 29.92 seconds
Started Jun 27 07:07:43 PM PDT 24
Finished Jun 27 07:08:15 PM PDT 24
Peak memory 201664 kb
Host smart-0bf30a3d-3bcc-4581-80f4-7625c2e9c0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879558165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1879558165
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.3123521757
Short name T797
Test name
Test status
Simulation time 3432831912 ps
CPU time 2.68 seconds
Started Jun 27 07:07:45 PM PDT 24
Finished Jun 27 07:07:49 PM PDT 24
Peak memory 201628 kb
Host smart-67360e23-8327-42c2-bb05-069e5ea65b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123521757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.3123521757
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3971780077
Short name T603
Test name
Test status
Simulation time 5810347749 ps
CPU time 14.78 seconds
Started Jun 27 07:07:40 PM PDT 24
Finished Jun 27 07:07:56 PM PDT 24
Peak memory 201668 kb
Host smart-26ecd26a-e74e-434e-a367-c7f61824dd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971780077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3971780077
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.1038685898
Short name T761
Test name
Test status
Simulation time 435706865869 ps
CPU time 1246.25 seconds
Started Jun 27 07:07:44 PM PDT 24
Finished Jun 27 07:28:33 PM PDT 24
Peak memory 210408 kb
Host smart-2a56ed0d-ff11-41a6-a6c4-3f5de5bafb71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038685898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.1038685898
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.457002443
Short name T17
Test name
Test status
Simulation time 65693472750 ps
CPU time 89.68 seconds
Started Jun 27 07:07:40 PM PDT 24
Finished Jun 27 07:09:11 PM PDT 24
Peak memory 210496 kb
Host smart-a027221d-8f8b-44ed-8493-e582da752021
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457002443 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.457002443
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.2546570359
Short name T489
Test name
Test status
Simulation time 334222659 ps
CPU time 0.75 seconds
Started Jun 27 07:07:57 PM PDT 24
Finished Jun 27 07:07:59 PM PDT 24
Peak memory 201600 kb
Host smart-8bf9cd01-397c-44d8-80e5-824f4893c120
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546570359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.2546570359
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1521509922
Short name T426
Test name
Test status
Simulation time 372430356537 ps
CPU time 14.27 seconds
Started Jun 27 07:07:45 PM PDT 24
Finished Jun 27 07:08:01 PM PDT 24
Peak memory 201652 kb
Host smart-8c5721a2-21ba-4796-91ac-c5f98b8cb7a2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521509922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1521509922
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.3980239172
Short name T728
Test name
Test status
Simulation time 358205672598 ps
CPU time 415.43 seconds
Started Jun 27 07:07:40 PM PDT 24
Finished Jun 27 07:14:37 PM PDT 24
Peak memory 201884 kb
Host smart-7c2158dc-a34f-4e90-a11b-6cdbec90ff83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980239172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.3980239172
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.2081989799
Short name T608
Test name
Test status
Simulation time 492492910586 ps
CPU time 242.53 seconds
Started Jun 27 07:07:41 PM PDT 24
Finished Jun 27 07:11:45 PM PDT 24
Peak memory 202088 kb
Host smart-57713854-fc56-4d3d-b46f-6b4b3282ba1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081989799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2081989799
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3837747606
Short name T483
Test name
Test status
Simulation time 327663126686 ps
CPU time 189.78 seconds
Started Jun 27 07:07:44 PM PDT 24
Finished Jun 27 07:10:56 PM PDT 24
Peak memory 201864 kb
Host smart-d8ed2d98-1ab0-4c11-9369-c6a9d0452860
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837747606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.3837747606
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.895897633
Short name T276
Test name
Test status
Simulation time 157685476885 ps
CPU time 168.59 seconds
Started Jun 27 07:07:43 PM PDT 24
Finished Jun 27 07:10:33 PM PDT 24
Peak memory 201972 kb
Host smart-2c6dd789-301b-4c5a-be9f-92c265e04f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895897633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.895897633
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1369857304
Short name T203
Test name
Test status
Simulation time 320496266025 ps
CPU time 151.74 seconds
Started Jun 27 07:07:43 PM PDT 24
Finished Jun 27 07:10:17 PM PDT 24
Peak memory 201968 kb
Host smart-b7bac9f3-46d4-437b-931c-04cf7cfd57bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369857304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.1369857304
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.1292245466
Short name T162
Test name
Test status
Simulation time 366221499591 ps
CPU time 843.35 seconds
Started Jun 27 07:07:42 PM PDT 24
Finished Jun 27 07:21:47 PM PDT 24
Peak memory 201952 kb
Host smart-c5352fb2-ab12-4462-a08d-fe5076b111f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292245466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.1292245466
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.718614476
Short name T201
Test name
Test status
Simulation time 593381415549 ps
CPU time 687.62 seconds
Started Jun 27 07:07:43 PM PDT 24
Finished Jun 27 07:19:13 PM PDT 24
Peak memory 201864 kb
Host smart-e8dbcf0a-bc58-4009-8bc6-b67f7db04b6d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718614476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.718614476
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.1967615869
Short name T356
Test name
Test status
Simulation time 114583998158 ps
CPU time 425.23 seconds
Started Jun 27 07:07:43 PM PDT 24
Finished Jun 27 07:14:51 PM PDT 24
Peak memory 202180 kb
Host smart-7aa2d233-0689-4bc4-84a1-f5a2e5c262a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967615869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1967615869
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.3486091375
Short name T647
Test name
Test status
Simulation time 30795446822 ps
CPU time 70.2 seconds
Started Jun 27 07:07:45 PM PDT 24
Finished Jun 27 07:08:57 PM PDT 24
Peak memory 201696 kb
Host smart-f125117d-d9bb-44b5-bbb6-e9257a2caa9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486091375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.3486091375
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2902391380
Short name T687
Test name
Test status
Simulation time 4253148535 ps
CPU time 4.97 seconds
Started Jun 27 07:07:43 PM PDT 24
Finished Jun 27 07:07:50 PM PDT 24
Peak memory 201680 kb
Host smart-5c1167ec-9fd6-4cec-80cc-03e72f3fdcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902391380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2902391380
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2717160510
Short name T535
Test name
Test status
Simulation time 5957044348 ps
CPU time 4.12 seconds
Started Jun 27 07:07:44 PM PDT 24
Finished Jun 27 07:07:50 PM PDT 24
Peak memory 201680 kb
Host smart-9e1704d9-bcf6-4fe3-898e-6147bcf50086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717160510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2717160510
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.2472752822
Short name T260
Test name
Test status
Simulation time 170544300204 ps
CPU time 197.24 seconds
Started Jun 27 07:08:32 PM PDT 24
Finished Jun 27 07:11:50 PM PDT 24
Peak memory 201828 kb
Host smart-e8cae26d-b8ca-4bf9-b976-6250ee3efb3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472752822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.2472752822
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.2386882025
Short name T422
Test name
Test status
Simulation time 287991241 ps
CPU time 0.84 seconds
Started Jun 27 07:08:02 PM PDT 24
Finished Jun 27 07:08:04 PM PDT 24
Peak memory 201628 kb
Host smart-71166730-52e0-4350-90cc-7a431f83b7ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386882025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.2386882025
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.181424376
Short name T195
Test name
Test status
Simulation time 494144019408 ps
CPU time 71.16 seconds
Started Jun 27 07:07:57 PM PDT 24
Finished Jun 27 07:09:10 PM PDT 24
Peak memory 201880 kb
Host smart-dd1012a2-b801-4963-8e69-b7fc5eeae542
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181424376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gati
ng.181424376
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.1451037781
Short name T275
Test name
Test status
Simulation time 481235209496 ps
CPU time 186.45 seconds
Started Jun 27 07:07:57 PM PDT 24
Finished Jun 27 07:11:05 PM PDT 24
Peak memory 201884 kb
Host smart-578bc850-5828-48f6-b65d-3679f0874b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451037781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.1451037781
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2024534496
Short name T528
Test name
Test status
Simulation time 333580027379 ps
CPU time 319 seconds
Started Jun 27 07:07:59 PM PDT 24
Finished Jun 27 07:13:19 PM PDT 24
Peak memory 201784 kb
Host smart-3a936ce0-b4c6-4934-a205-5fb6d85be900
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024534496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2024534496
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.955315459
Short name T661
Test name
Test status
Simulation time 498251263353 ps
CPU time 1082.98 seconds
Started Jun 27 07:07:59 PM PDT 24
Finished Jun 27 07:26:03 PM PDT 24
Peak memory 201924 kb
Host smart-88894a06-9419-4734-971d-d9b9ec569c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955315459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.955315459
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2732871748
Short name T526
Test name
Test status
Simulation time 324832397695 ps
CPU time 743.6 seconds
Started Jun 27 07:07:58 PM PDT 24
Finished Jun 27 07:20:23 PM PDT 24
Peak memory 201888 kb
Host smart-ac155f0d-18d6-4d74-8663-355e1937506f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732871748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2732871748
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2423932556
Short name T165
Test name
Test status
Simulation time 369514079530 ps
CPU time 402.6 seconds
Started Jun 27 07:07:58 PM PDT 24
Finished Jun 27 07:14:42 PM PDT 24
Peak memory 201856 kb
Host smart-d37cbe48-3159-4c26-a378-5bfc52edeae7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423932556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2423932556
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2507837244
Short name T663
Test name
Test status
Simulation time 592636778519 ps
CPU time 1284.04 seconds
Started Jun 27 07:07:57 PM PDT 24
Finished Jun 27 07:29:22 PM PDT 24
Peak memory 201824 kb
Host smart-2a48b09c-b716-492d-8873-f80856ad6c01
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507837244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.2507837244
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2432071239
Short name T673
Test name
Test status
Simulation time 102046780820 ps
CPU time 371.09 seconds
Started Jun 27 07:08:02 PM PDT 24
Finished Jun 27 07:14:14 PM PDT 24
Peak memory 202196 kb
Host smart-0a3cb3b2-4693-4acb-a452-7739e8666343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432071239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2432071239
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.548999062
Short name T649
Test name
Test status
Simulation time 34309084473 ps
CPU time 70.63 seconds
Started Jun 27 07:08:01 PM PDT 24
Finished Jun 27 07:09:13 PM PDT 24
Peak memory 201680 kb
Host smart-142014e9-cd81-43be-b83f-50e5da805a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548999062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.548999062
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.3921798466
Short name T724
Test name
Test status
Simulation time 3728290422 ps
CPU time 2.06 seconds
Started Jun 27 07:07:56 PM PDT 24
Finished Jun 27 07:07:59 PM PDT 24
Peak memory 201592 kb
Host smart-3ec51d43-b0cf-43b4-ab2c-4343ea6b8c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921798466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.3921798466
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.4186876481
Short name T582
Test name
Test status
Simulation time 5789822948 ps
CPU time 3.77 seconds
Started Jun 27 07:07:57 PM PDT 24
Finished Jun 27 07:08:02 PM PDT 24
Peak memory 201672 kb
Host smart-56b116d7-ed21-43e2-a184-7ae71644684c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186876481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.4186876481
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.3748554284
Short name T358
Test name
Test status
Simulation time 344986302838 ps
CPU time 533.66 seconds
Started Jun 27 07:07:55 PM PDT 24
Finished Jun 27 07:16:49 PM PDT 24
Peak memory 202112 kb
Host smart-f2551e55-8315-4128-9ace-66a203ef430d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748554284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.3748554284
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.4004438826
Short name T572
Test name
Test status
Simulation time 77735968282 ps
CPU time 46.25 seconds
Started Jun 27 07:08:00 PM PDT 24
Finished Jun 27 07:08:47 PM PDT 24
Peak memory 210264 kb
Host smart-3caffe08-90d9-418c-bbee-77134f9fcbd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004438826 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.4004438826
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.839820745
Short name T72
Test name
Test status
Simulation time 450621924 ps
CPU time 0.72 seconds
Started Jun 27 07:08:14 PM PDT 24
Finished Jun 27 07:08:16 PM PDT 24
Peak memory 201632 kb
Host smart-ec948c9e-d9dc-4c49-a074-af4820cc3946
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839820745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.839820745
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3523488645
Short name T283
Test name
Test status
Simulation time 495275818810 ps
CPU time 88.58 seconds
Started Jun 27 07:07:57 PM PDT 24
Finished Jun 27 07:09:26 PM PDT 24
Peak memory 201928 kb
Host smart-f90eac67-be1a-4c67-84bd-acfe9b461022
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523488645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3523488645
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.3793631451
Short name T246
Test name
Test status
Simulation time 356948385158 ps
CPU time 422.06 seconds
Started Jun 27 07:07:58 PM PDT 24
Finished Jun 27 07:15:01 PM PDT 24
Peak memory 201936 kb
Host smart-6ec6b386-f3c5-4406-9e02-813c864fe969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793631451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.3793631451
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3347031878
Short name T607
Test name
Test status
Simulation time 330600121074 ps
CPU time 698.85 seconds
Started Jun 27 07:07:57 PM PDT 24
Finished Jun 27 07:19:36 PM PDT 24
Peak memory 201848 kb
Host smart-c2f4ffb7-c8a4-4598-a2ec-597bb55fd237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347031878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3347031878
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.3743097354
Short name T783
Test name
Test status
Simulation time 497029598580 ps
CPU time 577.72 seconds
Started Jun 27 07:08:01 PM PDT 24
Finished Jun 27 07:17:40 PM PDT 24
Peak memory 201852 kb
Host smart-b507fcd1-4621-4165-9ee8-f476717ff692
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743097354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.3743097354
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.1786663431
Short name T172
Test name
Test status
Simulation time 487656602925 ps
CPU time 1072.85 seconds
Started Jun 27 07:08:00 PM PDT 24
Finished Jun 27 07:25:53 PM PDT 24
Peak memory 201892 kb
Host smart-020701e0-b144-4110-be8b-7231fa9d089f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786663431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.1786663431
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1010420754
Short name T744
Test name
Test status
Simulation time 318696750515 ps
CPU time 704.92 seconds
Started Jun 27 07:07:57 PM PDT 24
Finished Jun 27 07:19:44 PM PDT 24
Peak memory 201848 kb
Host smart-1e4671e0-e0cd-4767-ae24-19251fd3c209
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010420754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1010420754
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1230511518
Short name T96
Test name
Test status
Simulation time 293438969108 ps
CPU time 306.25 seconds
Started Jun 27 07:07:56 PM PDT 24
Finished Jun 27 07:13:03 PM PDT 24
Peak memory 201884 kb
Host smart-dd5a0262-b8bb-4054-8cb2-71c9779c8119
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230511518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1230511518
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3128464585
Short name T765
Test name
Test status
Simulation time 208729501724 ps
CPU time 337.11 seconds
Started Jun 27 07:07:57 PM PDT 24
Finished Jun 27 07:13:35 PM PDT 24
Peak memory 201860 kb
Host smart-2e797c78-4630-40b4-a14d-a3fd92d4bb8e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128464585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3128464585
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.3125496870
Short name T47
Test name
Test status
Simulation time 122504374830 ps
CPU time 592.63 seconds
Started Jun 27 07:08:00 PM PDT 24
Finished Jun 27 07:17:53 PM PDT 24
Peak memory 202204 kb
Host smart-2fcc41f8-0417-4ce1-8342-703ac402fe2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125496870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.3125496870
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2379335078
Short name T98
Test name
Test status
Simulation time 39933041106 ps
CPU time 26.33 seconds
Started Jun 27 07:08:00 PM PDT 24
Finished Jun 27 07:08:27 PM PDT 24
Peak memory 201680 kb
Host smart-fccbe34f-fb84-4956-b4ba-43aa0d18046e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379335078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2379335078
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.4094190865
Short name T455
Test name
Test status
Simulation time 2951786431 ps
CPU time 2.61 seconds
Started Jun 27 07:08:03 PM PDT 24
Finished Jun 27 07:08:06 PM PDT 24
Peak memory 201684 kb
Host smart-30e8120f-93c1-442a-8662-45a5911a4451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094190865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.4094190865
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.1474069161
Short name T583
Test name
Test status
Simulation time 5983121667 ps
CPU time 8 seconds
Started Jun 27 07:07:57 PM PDT 24
Finished Jun 27 07:08:05 PM PDT 24
Peak memory 201660 kb
Host smart-0c14db8a-3181-41d8-899d-84c9977310ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474069161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1474069161
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.1592365459
Short name T433
Test name
Test status
Simulation time 314872792 ps
CPU time 1.32 seconds
Started Jun 27 07:08:14 PM PDT 24
Finished Jun 27 07:08:17 PM PDT 24
Peak memory 201556 kb
Host smart-1e530539-59b8-43ef-b04e-50e7f47141a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592365459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1592365459
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3103006421
Short name T257
Test name
Test status
Simulation time 346143633161 ps
CPU time 723.48 seconds
Started Jun 27 07:08:13 PM PDT 24
Finished Jun 27 07:20:18 PM PDT 24
Peak memory 201868 kb
Host smart-2dbd832a-7449-4303-8ddf-5f59dcf171a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103006421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3103006421
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.890697409
Short name T93
Test name
Test status
Simulation time 386851272468 ps
CPU time 851.97 seconds
Started Jun 27 07:08:12 PM PDT 24
Finished Jun 27 07:22:26 PM PDT 24
Peak memory 201892 kb
Host smart-462b61ee-d5ec-46fb-b582-22d09a1ee360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890697409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.890697409
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2865646421
Short name T479
Test name
Test status
Simulation time 329128838069 ps
CPU time 686.77 seconds
Started Jun 27 07:08:13 PM PDT 24
Finished Jun 27 07:19:42 PM PDT 24
Peak memory 201760 kb
Host smart-5f8484dc-ec3f-4796-9b53-29c778883428
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865646421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.2865646421
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2044326893
Short name T154
Test name
Test status
Simulation time 326310053696 ps
CPU time 140.92 seconds
Started Jun 27 07:08:15 PM PDT 24
Finished Jun 27 07:10:37 PM PDT 24
Peak memory 201928 kb
Host smart-2bff884e-12ac-40cd-b8cc-ab289a87f9a0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044326893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2044326893
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.2453360113
Short name T176
Test name
Test status
Simulation time 352697179883 ps
CPU time 718.28 seconds
Started Jun 27 07:08:14 PM PDT 24
Finished Jun 27 07:20:14 PM PDT 24
Peak memory 201864 kb
Host smart-364ccc54-c5d4-456a-8c0e-23ff62a003ac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453360113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.2453360113
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.3224756090
Short name T578
Test name
Test status
Simulation time 587188172432 ps
CPU time 1437.29 seconds
Started Jun 27 07:08:16 PM PDT 24
Finished Jun 27 07:32:15 PM PDT 24
Peak memory 201900 kb
Host smart-03656ad0-ae95-4bc3-b6ce-fa24604ede90
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224756090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.3224756090
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.2777084299
Short name T594
Test name
Test status
Simulation time 104605960990 ps
CPU time 577.59 seconds
Started Jun 27 07:08:17 PM PDT 24
Finished Jun 27 07:17:55 PM PDT 24
Peak memory 202444 kb
Host smart-271819f7-7157-4044-8c7c-8142dde4f0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777084299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.2777084299
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.111516549
Short name T376
Test name
Test status
Simulation time 37277244247 ps
CPU time 12.79 seconds
Started Jun 27 07:08:15 PM PDT 24
Finished Jun 27 07:08:29 PM PDT 24
Peak memory 201620 kb
Host smart-2a4690c1-8b8d-44ef-8eb2-67c419535d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111516549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.111516549
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.2026728343
Short name T639
Test name
Test status
Simulation time 2968817143 ps
CPU time 7.29 seconds
Started Jun 27 07:08:15 PM PDT 24
Finished Jun 27 07:08:24 PM PDT 24
Peak memory 201900 kb
Host smart-6635d295-2606-4b68-80cc-ac08a03eda38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026728343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2026728343
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.1889086720
Short name T695
Test name
Test status
Simulation time 5972233086 ps
CPU time 4.17 seconds
Started Jun 27 07:08:13 PM PDT 24
Finished Jun 27 07:08:18 PM PDT 24
Peak memory 201712 kb
Host smart-e9dcdbcc-1645-4968-a71b-2af764c95314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889086720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.1889086720
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.3459962775
Short name T638
Test name
Test status
Simulation time 424866159755 ps
CPU time 801.36 seconds
Started Jun 27 07:08:13 PM PDT 24
Finished Jun 27 07:21:36 PM PDT 24
Peak memory 210344 kb
Host smart-8eaf5ef9-915a-44d7-9277-1c6569f2c873
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459962775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.3459962775
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.4158214640
Short name T469
Test name
Test status
Simulation time 362243607184 ps
CPU time 210.1 seconds
Started Jun 27 07:08:15 PM PDT 24
Finished Jun 27 07:11:46 PM PDT 24
Peak memory 210472 kb
Host smart-9675fb0a-8462-4895-9a0b-093c6eeda668
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158214640 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.4158214640
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1037725711
Short name T636
Test name
Test status
Simulation time 337117460 ps
CPU time 1.02 seconds
Started Jun 27 07:08:33 PM PDT 24
Finished Jun 27 07:08:35 PM PDT 24
Peak memory 201592 kb
Host smart-9f4da462-7576-4857-ac4d-e01dc0f44cad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037725711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1037725711
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3262345241
Short name T692
Test name
Test status
Simulation time 524045198596 ps
CPU time 1167.16 seconds
Started Jun 27 07:08:37 PM PDT 24
Finished Jun 27 07:28:06 PM PDT 24
Peak memory 202132 kb
Host smart-18b22c84-66d2-43c5-8e51-dfa6abb7dedf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262345241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3262345241
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.1087983830
Short name T314
Test name
Test status
Simulation time 158288794910 ps
CPU time 102.29 seconds
Started Jun 27 07:08:35 PM PDT 24
Finished Jun 27 07:10:18 PM PDT 24
Peak memory 201920 kb
Host smart-7d0fc095-4313-4210-998a-a84ac69ae1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087983830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.1087983830
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.18433786
Short name T159
Test name
Test status
Simulation time 162670275946 ps
CPU time 379.68 seconds
Started Jun 27 07:08:13 PM PDT 24
Finished Jun 27 07:14:34 PM PDT 24
Peak memory 201904 kb
Host smart-cdaf1120-9cff-45e4-8548-1b5f729c6c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18433786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.18433786
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3205785117
Short name T529
Test name
Test status
Simulation time 162923956590 ps
CPU time 97.22 seconds
Started Jun 27 07:08:37 PM PDT 24
Finished Jun 27 07:10:15 PM PDT 24
Peak memory 202060 kb
Host smart-c7d37785-a816-4603-a851-a3b98b5be4dd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205785117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3205785117
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.4135461151
Short name T802
Test name
Test status
Simulation time 339639137752 ps
CPU time 729.6 seconds
Started Jun 27 07:08:18 PM PDT 24
Finished Jun 27 07:20:29 PM PDT 24
Peak memory 202128 kb
Host smart-cafb2e52-4bb1-4516-8063-7ff770e83d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135461151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.4135461151
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3643432265
Short name T669
Test name
Test status
Simulation time 324433785666 ps
CPU time 206.46 seconds
Started Jun 27 07:08:14 PM PDT 24
Finished Jun 27 07:11:42 PM PDT 24
Peak memory 201856 kb
Host smart-2ac346bc-faaf-44a9-a3b2-73f3855e8692
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643432265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3643432265
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.717240713
Short name T618
Test name
Test status
Simulation time 209167974048 ps
CPU time 240.91 seconds
Started Jun 27 07:08:36 PM PDT 24
Finished Jun 27 07:12:38 PM PDT 24
Peak memory 201832 kb
Host smart-1038d5cb-ad0a-42f0-95f3-882d32fb0d38
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717240713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.717240713
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.4023189195
Short name T664
Test name
Test status
Simulation time 34046639195 ps
CPU time 81.95 seconds
Started Jun 27 07:08:40 PM PDT 24
Finished Jun 27 07:10:03 PM PDT 24
Peak memory 201616 kb
Host smart-fde58efb-54c7-454e-94bb-9ef0e94dff63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023189195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.4023189195
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.264612549
Short name T585
Test name
Test status
Simulation time 5172127728 ps
CPU time 3.46 seconds
Started Jun 27 07:08:34 PM PDT 24
Finished Jun 27 07:08:39 PM PDT 24
Peak memory 201696 kb
Host smart-472af4f5-98eb-47a2-a106-10d2a409067e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264612549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.264612549
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.2265661866
Short name T665
Test name
Test status
Simulation time 5711769341 ps
CPU time 2.28 seconds
Started Jun 27 07:08:16 PM PDT 24
Finished Jun 27 07:08:19 PM PDT 24
Peak memory 201652 kb
Host smart-13a77cbd-d64f-4c7a-be99-5d8b58f63a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265661866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2265661866
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3124153837
Short name T247
Test name
Test status
Simulation time 408165434039 ps
CPU time 196.87 seconds
Started Jun 27 07:08:35 PM PDT 24
Finished Jun 27 07:11:54 PM PDT 24
Peak memory 201812 kb
Host smart-723c19fb-6dab-4334-8c0e-1cdb563183a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124153837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3124153837
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.727816128
Short name T621
Test name
Test status
Simulation time 521580138 ps
CPU time 0.97 seconds
Started Jun 27 07:08:34 PM PDT 24
Finished Jun 27 07:08:36 PM PDT 24
Peak memory 201624 kb
Host smart-9c54064a-9bae-44f0-b80b-c566f6cc0888
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727816128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.727816128
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.4294331935
Short name T763
Test name
Test status
Simulation time 206488351691 ps
CPU time 79.92 seconds
Started Jun 27 07:08:35 PM PDT 24
Finished Jun 27 07:09:56 PM PDT 24
Peak memory 201812 kb
Host smart-aa6decc9-791f-460b-8fb9-e1bac39745ba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294331935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.4294331935
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.1330401310
Short name T551
Test name
Test status
Simulation time 335143288838 ps
CPU time 475.35 seconds
Started Jun 27 07:08:33 PM PDT 24
Finished Jun 27 07:16:30 PM PDT 24
Peak memory 201876 kb
Host smart-3da7d61b-feb3-42ea-a55c-6ca0f874732c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330401310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.1330401310
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2124849645
Short name T242
Test name
Test status
Simulation time 165136516174 ps
CPU time 184.25 seconds
Started Jun 27 07:08:33 PM PDT 24
Finished Jun 27 07:11:38 PM PDT 24
Peak memory 201932 kb
Host smart-f0fdd92a-f657-404e-a21d-0612875d3d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124849645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2124849645
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3713561063
Short name T436
Test name
Test status
Simulation time 496135754983 ps
CPU time 181.6 seconds
Started Jun 27 07:08:35 PM PDT 24
Finished Jun 27 07:11:38 PM PDT 24
Peak memory 201864 kb
Host smart-58a5184b-9c6b-468b-9b63-ba6395e50207
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713561063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.3713561063
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.1054294672
Short name T234
Test name
Test status
Simulation time 484775870138 ps
CPU time 1016.19 seconds
Started Jun 27 07:08:40 PM PDT 24
Finished Jun 27 07:25:37 PM PDT 24
Peak memory 201812 kb
Host smart-c4ae8990-1200-49c9-840f-c131081515da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054294672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1054294672
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3938037305
Short name T538
Test name
Test status
Simulation time 492407642651 ps
CPU time 1096.22 seconds
Started Jun 27 07:08:37 PM PDT 24
Finished Jun 27 07:26:54 PM PDT 24
Peak memory 201828 kb
Host smart-dc84390a-a254-47e0-82a2-11ba7e09f25a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938037305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3938037305
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2835626765
Short name T108
Test name
Test status
Simulation time 351003701512 ps
CPU time 826.43 seconds
Started Jun 27 07:08:34 PM PDT 24
Finished Jun 27 07:22:21 PM PDT 24
Peak memory 201828 kb
Host smart-e0141685-d91b-42ad-93b9-5771ff9e221a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835626765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2835626765
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2733755089
Short name T441
Test name
Test status
Simulation time 207898858520 ps
CPU time 472.21 seconds
Started Jun 27 07:08:35 PM PDT 24
Finished Jun 27 07:16:29 PM PDT 24
Peak memory 201872 kb
Host smart-ae26e082-0005-4e3f-9dae-9daa88f3c186
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733755089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.2733755089
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.721862662
Short name T226
Test name
Test status
Simulation time 124552439594 ps
CPU time 510.94 seconds
Started Jun 27 07:08:40 PM PDT 24
Finished Jun 27 07:17:12 PM PDT 24
Peak memory 202140 kb
Host smart-7b8991b1-d0a5-4815-9c86-266bcb40dd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721862662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.721862662
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2044227443
Short name T615
Test name
Test status
Simulation time 22279393158 ps
CPU time 24.21 seconds
Started Jun 27 07:08:33 PM PDT 24
Finished Jun 27 07:08:58 PM PDT 24
Peak memory 201684 kb
Host smart-66635dc1-8295-4a1b-94a7-1efb4cd641bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044227443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2044227443
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.4293121425
Short name T580
Test name
Test status
Simulation time 4980983737 ps
CPU time 12.67 seconds
Started Jun 27 07:08:35 PM PDT 24
Finished Jun 27 07:08:49 PM PDT 24
Peak memory 201636 kb
Host smart-586ff9d3-ea3d-404d-ac46-03cc7f4fbb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293121425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.4293121425
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.3779846038
Short name T368
Test name
Test status
Simulation time 5846406840 ps
CPU time 13.72 seconds
Started Jun 27 07:08:41 PM PDT 24
Finished Jun 27 07:08:57 PM PDT 24
Peak memory 201612 kb
Host smart-a5a70ee5-32a5-4dc8-a3b7-dc3b215e7e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779846038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3779846038
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.1450395389
Short name T310
Test name
Test status
Simulation time 358931643225 ps
CPU time 795.12 seconds
Started Jun 27 07:08:35 PM PDT 24
Finished Jun 27 07:21:51 PM PDT 24
Peak memory 201904 kb
Host smart-dc851b20-5626-463d-950e-75db049ede06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450395389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.1450395389
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.834309188
Short name T680
Test name
Test status
Simulation time 27234058368 ps
CPU time 28.96 seconds
Started Jun 27 07:08:37 PM PDT 24
Finished Jun 27 07:09:07 PM PDT 24
Peak memory 202028 kb
Host smart-02a9ce36-1ac1-4383-8747-6ed387209bd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834309188 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.834309188
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1728177348
Short name T614
Test name
Test status
Simulation time 449578234 ps
CPU time 0.9 seconds
Started Jun 27 07:08:49 PM PDT 24
Finished Jun 27 07:08:53 PM PDT 24
Peak memory 201628 kb
Host smart-7ea18d16-69a7-45df-bff5-c31b7c763545
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728177348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1728177348
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.750657187
Short name T279
Test name
Test status
Simulation time 216144389723 ps
CPU time 514.22 seconds
Started Jun 27 07:08:49 PM PDT 24
Finished Jun 27 07:17:26 PM PDT 24
Peak memory 201932 kb
Host smart-317038bd-6f08-41f2-81f1-aeb114587de1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750657187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gati
ng.750657187
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.2018251034
Short name T337
Test name
Test status
Simulation time 494386455117 ps
CPU time 1053.26 seconds
Started Jun 27 07:08:50 PM PDT 24
Finished Jun 27 07:26:26 PM PDT 24
Peak memory 201868 kb
Host smart-f03d44cc-f45b-4f8b-b13d-0b7e8db8986b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018251034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.2018251034
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1780882718
Short name T86
Test name
Test status
Simulation time 160492028116 ps
CPU time 201.92 seconds
Started Jun 27 07:08:51 PM PDT 24
Finished Jun 27 07:12:15 PM PDT 24
Peak memory 202096 kb
Host smart-54457a39-a648-4db4-9db1-dafc49f6b675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780882718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1780882718
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.789188512
Short name T713
Test name
Test status
Simulation time 491467811460 ps
CPU time 274.21 seconds
Started Jun 27 07:08:48 PM PDT 24
Finished Jun 27 07:13:25 PM PDT 24
Peak memory 201888 kb
Host smart-b0bba826-1229-4f90-9d5e-077fe4b20166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789188512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.789188512
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.320118394
Short name T26
Test name
Test status
Simulation time 324855873761 ps
CPU time 193.35 seconds
Started Jun 27 07:08:49 PM PDT 24
Finished Jun 27 07:12:05 PM PDT 24
Peak memory 201848 kb
Host smart-7bf9f735-4cb0-4bf1-8a52-f0de12437b60
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=320118394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixe
d.320118394
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.2400659488
Short name T148
Test name
Test status
Simulation time 200863301919 ps
CPU time 111.85 seconds
Started Jun 27 07:08:51 PM PDT 24
Finished Jun 27 07:10:45 PM PDT 24
Peak memory 202084 kb
Host smart-b3479019-5b24-4b5d-8f05-7a29483add18
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400659488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.2400659488
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.3602575896
Short name T606
Test name
Test status
Simulation time 630886152382 ps
CPU time 1427.06 seconds
Started Jun 27 07:08:53 PM PDT 24
Finished Jun 27 07:32:42 PM PDT 24
Peak memory 201880 kb
Host smart-b9937144-56f3-4765-9944-75d7e4ed6560
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602575896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.3602575896
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2905762142
Short name T715
Test name
Test status
Simulation time 75154453865 ps
CPU time 301.83 seconds
Started Jun 27 07:08:53 PM PDT 24
Finished Jun 27 07:13:57 PM PDT 24
Peak memory 202216 kb
Host smart-4231e9cf-6170-4424-ab09-325aa1fb7659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905762142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2905762142
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2822552506
Short name T382
Test name
Test status
Simulation time 37935508196 ps
CPU time 89.19 seconds
Started Jun 27 07:08:53 PM PDT 24
Finished Jun 27 07:10:24 PM PDT 24
Peak memory 201692 kb
Host smart-f233eb95-7627-47c1-b269-ac7bfe4abf44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822552506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2822552506
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.355554328
Short name T401
Test name
Test status
Simulation time 4597799103 ps
CPU time 3.29 seconds
Started Jun 27 07:08:49 PM PDT 24
Finished Jun 27 07:08:55 PM PDT 24
Peak memory 201684 kb
Host smart-c946a413-d80e-4444-803c-efb160d14997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355554328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.355554328
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.3001041591
Short name T487
Test name
Test status
Simulation time 5942856415 ps
CPU time 7.69 seconds
Started Jun 27 07:08:34 PM PDT 24
Finished Jun 27 07:08:43 PM PDT 24
Peak memory 201668 kb
Host smart-a9047bdd-2d4d-4029-a775-69b15dec6446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001041591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3001041591
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.4246335229
Short name T444
Test name
Test status
Simulation time 26606234084 ps
CPU time 31.68 seconds
Started Jun 27 07:08:53 PM PDT 24
Finished Jun 27 07:09:26 PM PDT 24
Peak memory 201688 kb
Host smart-3df12138-2b81-42ac-a6c1-a6604dd4c1e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246335229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.4246335229
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2465523668
Short name T19
Test name
Test status
Simulation time 154565991694 ps
CPU time 190.67 seconds
Started Jun 27 07:08:48 PM PDT 24
Finished Jun 27 07:12:02 PM PDT 24
Peak memory 210596 kb
Host smart-415fff57-7c20-4f40-a338-fbaec5685b90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465523668 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.2465523668
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.1410732421
Short name T451
Test name
Test status
Simulation time 529984753 ps
CPU time 1.88 seconds
Started Jun 27 07:09:05 PM PDT 24
Finished Jun 27 07:09:08 PM PDT 24
Peak memory 201840 kb
Host smart-810ae86f-a407-4ca0-abdc-f6d87f650e8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410732421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1410732421
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1876153818
Short name T293
Test name
Test status
Simulation time 407109865980 ps
CPU time 882.83 seconds
Started Jun 27 07:08:49 PM PDT 24
Finished Jun 27 07:23:35 PM PDT 24
Peak memory 201868 kb
Host smart-61f46944-06f4-4ec4-afa5-bb72aed09a73
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876153818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1876153818
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.243476530
Short name T167
Test name
Test status
Simulation time 341144385007 ps
CPU time 201.42 seconds
Started Jun 27 07:08:50 PM PDT 24
Finished Jun 27 07:12:14 PM PDT 24
Peak memory 201964 kb
Host smart-76ab799d-321b-4c19-bc23-6032159abf71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243476530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.243476530
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.813641569
Short name T794
Test name
Test status
Simulation time 330551093933 ps
CPU time 362.82 seconds
Started Jun 27 07:08:48 PM PDT 24
Finished Jun 27 07:14:54 PM PDT 24
Peak memory 201872 kb
Host smart-3ea6adf8-e808-42d9-b4cc-0f9e70382aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813641569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.813641569
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2526475259
Short name T514
Test name
Test status
Simulation time 490937551136 ps
CPU time 279.35 seconds
Started Jun 27 07:08:50 PM PDT 24
Finished Jun 27 07:13:32 PM PDT 24
Peak memory 201860 kb
Host smart-fe1c0216-8fa6-4a3f-b526-8775e86e6894
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526475259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2526475259
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1632632344
Short name T612
Test name
Test status
Simulation time 163968336445 ps
CPU time 254.83 seconds
Started Jun 27 07:08:50 PM PDT 24
Finished Jun 27 07:13:07 PM PDT 24
Peak memory 201960 kb
Host smart-620eb226-3a98-4235-b14b-f37b632fd54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632632344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1632632344
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3567747655
Short name T424
Test name
Test status
Simulation time 484902627009 ps
CPU time 1048.21 seconds
Started Jun 27 07:08:47 PM PDT 24
Finished Jun 27 07:26:17 PM PDT 24
Peak memory 201856 kb
Host smart-bbe677c0-041a-49bf-827c-3c6befa9cee4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567747655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3567747655
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1592679106
Short name T91
Test name
Test status
Simulation time 590397099462 ps
CPU time 656.13 seconds
Started Jun 27 07:08:47 PM PDT 24
Finished Jun 27 07:19:47 PM PDT 24
Peak memory 201784 kb
Host smart-1da2a686-5814-405c-8942-11d023aea829
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592679106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1592679106
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3395864208
Short name T435
Test name
Test status
Simulation time 71759787910 ps
CPU time 248.04 seconds
Started Jun 27 07:09:04 PM PDT 24
Finished Jun 27 07:13:13 PM PDT 24
Peak memory 202196 kb
Host smart-cebb68ce-a566-4b47-b34a-74dd08d662b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395864208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3395864208
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3613217797
Short name T158
Test name
Test status
Simulation time 38313094611 ps
CPU time 21.06 seconds
Started Jun 27 07:09:04 PM PDT 24
Finished Jun 27 07:09:27 PM PDT 24
Peak memory 201684 kb
Host smart-daad593d-37f8-4250-a860-0a3f70d7577d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613217797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3613217797
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.2890614062
Short name T15
Test name
Test status
Simulation time 2975002976 ps
CPU time 2.37 seconds
Started Jun 27 07:09:04 PM PDT 24
Finished Jun 27 07:09:08 PM PDT 24
Peak memory 201684 kb
Host smart-7d5a2c00-b8f5-4ddb-8e4d-e8999875509a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890614062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.2890614062
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1688024677
Short name T563
Test name
Test status
Simulation time 6039295984 ps
CPU time 13.81 seconds
Started Jun 27 07:08:48 PM PDT 24
Finished Jun 27 07:09:05 PM PDT 24
Peak memory 201648 kb
Host smart-ddcf1ad6-14b9-4c01-829f-c2bb0d66128a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688024677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1688024677
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.2116280667
Short name T627
Test name
Test status
Simulation time 9999560283 ps
CPU time 6.92 seconds
Started Jun 27 07:09:04 PM PDT 24
Finished Jun 27 07:09:12 PM PDT 24
Peak memory 201684 kb
Host smart-c71ec5da-ca96-4157-962a-3789ab859ad5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116280667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.2116280667
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.4100421783
Short name T315
Test name
Test status
Simulation time 138568652410 ps
CPU time 53.27 seconds
Started Jun 27 07:09:04 PM PDT 24
Finished Jun 27 07:09:59 PM PDT 24
Peak memory 210204 kb
Host smart-7c87244d-037d-4df9-8aba-60e0003a8429
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100421783 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.4100421783
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1505355128
Short name T388
Test name
Test status
Simulation time 414905370 ps
CPU time 1.47 seconds
Started Jun 27 07:09:14 PM PDT 24
Finished Jun 27 07:09:16 PM PDT 24
Peak memory 201632 kb
Host smart-4de6b083-e5c1-43ad-bc1c-012e8820c22a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505355128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1505355128
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3515247973
Short name T590
Test name
Test status
Simulation time 358652233509 ps
CPU time 733.22 seconds
Started Jun 27 07:09:05 PM PDT 24
Finished Jun 27 07:21:20 PM PDT 24
Peak memory 202156 kb
Host smart-9a9702c4-f2a5-49ce-ab21-38d1ec87c736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515247973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3515247973
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.3265013091
Short name T335
Test name
Test status
Simulation time 495395499377 ps
CPU time 565.23 seconds
Started Jun 27 07:09:02 PM PDT 24
Finished Jun 27 07:18:28 PM PDT 24
Peak memory 201852 kb
Host smart-d25081f4-99a8-41b3-9583-dcc2271da2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265013091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3265013091
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2187715284
Short name T2
Test name
Test status
Simulation time 498446256143 ps
CPU time 1081.73 seconds
Started Jun 27 07:09:03 PM PDT 24
Finished Jun 27 07:27:06 PM PDT 24
Peak memory 201868 kb
Host smart-749a8f50-14c0-4f8d-a4d6-7f33af496dcf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187715284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2187715284
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.112015533
Short name T194
Test name
Test status
Simulation time 490898920034 ps
CPU time 81.52 seconds
Started Jun 27 07:09:04 PM PDT 24
Finished Jun 27 07:10:27 PM PDT 24
Peak memory 201972 kb
Host smart-e2b2024d-33f7-47d4-91bf-aab83185c3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112015533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.112015533
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.1556546201
Short name T439
Test name
Test status
Simulation time 329031235353 ps
CPU time 775.81 seconds
Started Jun 27 07:09:01 PM PDT 24
Finished Jun 27 07:21:58 PM PDT 24
Peak memory 201900 kb
Host smart-6c801ce0-c011-46e3-9eec-c2de4fbea0f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556546201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.1556546201
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.2852261307
Short name T262
Test name
Test status
Simulation time 351159721060 ps
CPU time 501.74 seconds
Started Jun 27 07:09:04 PM PDT 24
Finished Jun 27 07:17:27 PM PDT 24
Peak memory 201852 kb
Host smart-230dec9b-b1a6-4871-bc07-f50823a8a6fa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852261307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.2852261307
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.4287248599
Short name T525
Test name
Test status
Simulation time 215692098804 ps
CPU time 134.95 seconds
Started Jun 27 07:09:04 PM PDT 24
Finished Jun 27 07:11:20 PM PDT 24
Peak memory 201856 kb
Host smart-89090985-ebb5-4940-8e5a-26d7605efc42
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287248599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.4287248599
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3243553930
Short name T221
Test name
Test status
Simulation time 101017525831 ps
CPU time 363.24 seconds
Started Jun 27 07:09:15 PM PDT 24
Finished Jun 27 07:15:19 PM PDT 24
Peak memory 202188 kb
Host smart-e799c9ec-be3e-4e38-9a8d-5b064148c5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243553930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3243553930
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.3427752614
Short name T109
Test name
Test status
Simulation time 40310466130 ps
CPU time 87.34 seconds
Started Jun 27 07:09:04 PM PDT 24
Finished Jun 27 07:10:33 PM PDT 24
Peak memory 201684 kb
Host smart-07980623-edbf-4e73-b44b-bff8e07382cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427752614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.3427752614
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.4094634217
Short name T736
Test name
Test status
Simulation time 5274812037 ps
CPU time 3.93 seconds
Started Jun 27 07:09:01 PM PDT 24
Finished Jun 27 07:09:06 PM PDT 24
Peak memory 201688 kb
Host smart-7595261f-98cb-49c0-9268-cb807c0e99de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094634217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.4094634217
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.2667496911
Short name T28
Test name
Test status
Simulation time 5663352978 ps
CPU time 2.06 seconds
Started Jun 27 07:09:03 PM PDT 24
Finished Jun 27 07:09:06 PM PDT 24
Peak memory 201652 kb
Host smart-6f3a382e-ec37-4412-9b5e-02e43fea7c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667496911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.2667496911
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.1197219589
Short name T634
Test name
Test status
Simulation time 333074871841 ps
CPU time 159.36 seconds
Started Jun 27 07:09:14 PM PDT 24
Finished Jun 27 07:11:54 PM PDT 24
Peak memory 201872 kb
Host smart-0d6fc92c-9a59-48ed-8e0f-e06d09a78b55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197219589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.1197219589
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.4059899022
Short name T22
Test name
Test status
Simulation time 43802181641 ps
CPU time 91.42 seconds
Started Jun 27 07:09:17 PM PDT 24
Finished Jun 27 07:10:50 PM PDT 24
Peak memory 210260 kb
Host smart-6cd14db2-d59c-4e15-84cf-2d7f585bf68d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059899022 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.4059899022
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.464263150
Short name T497
Test name
Test status
Simulation time 405855598 ps
CPU time 1.57 seconds
Started Jun 27 07:06:39 PM PDT 24
Finished Jun 27 07:06:48 PM PDT 24
Peak memory 201652 kb
Host smart-85238c38-3cdf-4e79-aba3-c25d3503afb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464263150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.464263150
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.3424935291
Short name T706
Test name
Test status
Simulation time 167180679607 ps
CPU time 275.11 seconds
Started Jun 27 07:06:39 PM PDT 24
Finished Jun 27 07:11:23 PM PDT 24
Peak memory 201936 kb
Host smart-d8cd2c24-8ddc-4112-becc-9d74eec4cbe7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424935291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.3424935291
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.1674881189
Short name T328
Test name
Test status
Simulation time 212530734352 ps
CPU time 104.36 seconds
Started Jun 27 07:06:43 PM PDT 24
Finished Jun 27 07:08:37 PM PDT 24
Peak memory 201804 kb
Host smart-c86c03cd-8f37-44cf-b100-4805591a1fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674881189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.1674881189
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.644072230
Short name T179
Test name
Test status
Simulation time 500169620883 ps
CPU time 338.75 seconds
Started Jun 27 07:06:43 PM PDT 24
Finished Jun 27 07:12:31 PM PDT 24
Peak memory 201768 kb
Host smart-21174562-83f2-483a-ac08-33e8f727d866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644072230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.644072230
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.691827350
Short name T536
Test name
Test status
Simulation time 489539605210 ps
CPU time 1102.62 seconds
Started Jun 27 07:06:43 PM PDT 24
Finished Jun 27 07:25:15 PM PDT 24
Peak memory 201840 kb
Host smart-dcbaf51d-f930-4a91-aaa9-b31953d9618a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=691827350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.691827350
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.3789140159
Short name T539
Test name
Test status
Simulation time 162570806697 ps
CPU time 195.19 seconds
Started Jun 27 07:06:42 PM PDT 24
Finished Jun 27 07:10:06 PM PDT 24
Peak memory 201892 kb
Host smart-13fc5a4d-b75f-4b55-bc70-f4d7c2861f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789140159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3789140159
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1464953540
Short name T777
Test name
Test status
Simulation time 325543446039 ps
CPU time 206.63 seconds
Started Jun 27 07:06:43 PM PDT 24
Finished Jun 27 07:10:19 PM PDT 24
Peak memory 201912 kb
Host smart-9504bb1f-0e9d-411c-8156-89dc74bef805
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464953540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1464953540
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.863699746
Short name T103
Test name
Test status
Simulation time 615944564441 ps
CPU time 111.84 seconds
Started Jun 27 07:06:39 PM PDT 24
Finished Jun 27 07:08:39 PM PDT 24
Peak memory 201880 kb
Host smart-58bd976c-f923-4b3b-9b4c-6aaaddb861cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863699746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_w
akeup.863699746
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1413164519
Short name T747
Test name
Test status
Simulation time 610186198965 ps
CPU time 359.52 seconds
Started Jun 27 07:06:41 PM PDT 24
Finished Jun 27 07:12:50 PM PDT 24
Peak memory 201884 kb
Host smart-804723cd-bd14-4101-920e-359c751e53f5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413164519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1413164519
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1343686771
Short name T470
Test name
Test status
Simulation time 89437256679 ps
CPU time 340.49 seconds
Started Jun 27 07:06:43 PM PDT 24
Finished Jun 27 07:12:33 PM PDT 24
Peak memory 202172 kb
Host smart-aae999dc-2574-4819-88cc-a4327356598e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343686771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1343686771
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3627614424
Short name T3
Test name
Test status
Simulation time 36294066526 ps
CPU time 20.14 seconds
Started Jun 27 07:06:41 PM PDT 24
Finished Jun 27 07:07:11 PM PDT 24
Peak memory 201668 kb
Host smart-d92b7805-5ffe-4c6c-b9b7-f39f7b971b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627614424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3627614424
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.880409939
Short name T530
Test name
Test status
Simulation time 4674487795 ps
CPU time 11.87 seconds
Started Jun 27 07:06:39 PM PDT 24
Finished Jun 27 07:06:59 PM PDT 24
Peak memory 201692 kb
Host smart-2da901ae-d5c6-41f1-8ea4-5e64bb4092ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880409939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.880409939
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3811108635
Short name T65
Test name
Test status
Simulation time 4549402975 ps
CPU time 1.68 seconds
Started Jun 27 07:06:44 PM PDT 24
Finished Jun 27 07:06:54 PM PDT 24
Peak memory 217012 kb
Host smart-88190ccf-33fc-438e-aa56-814f0cebbae5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811108635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3811108635
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1008029541
Short name T509
Test name
Test status
Simulation time 5847366518 ps
CPU time 14.34 seconds
Started Jun 27 07:06:41 PM PDT 24
Finished Jun 27 07:07:05 PM PDT 24
Peak memory 201676 kb
Host smart-84dd41df-b947-44fe-9b45-849e25de2806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008029541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1008029541
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.1968948737
Short name T85
Test name
Test status
Simulation time 38977908596 ps
CPU time 80.35 seconds
Started Jun 27 07:06:38 PM PDT 24
Finished Jun 27 07:08:05 PM PDT 24
Peak memory 201708 kb
Host smart-deea6718-486d-48ad-9009-43efdbaa2bc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968948737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
1968948737
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2157042348
Short name T20
Test name
Test status
Simulation time 44911295628 ps
CPU time 26.61 seconds
Started Jun 27 07:06:43 PM PDT 24
Finished Jun 27 07:07:19 PM PDT 24
Peak memory 211532 kb
Host smart-75889072-e2d4-45d3-b310-0f2b9d4925bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157042348 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.2157042348
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2315216530
Short name T397
Test name
Test status
Simulation time 286125528 ps
CPU time 1.29 seconds
Started Jun 27 07:09:34 PM PDT 24
Finished Jun 27 07:09:37 PM PDT 24
Peak memory 201640 kb
Host smart-f61b3da1-6e4d-4808-b749-05d9d233b4f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315216530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2315216530
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.2139316032
Short name T776
Test name
Test status
Simulation time 204882474842 ps
CPU time 239.24 seconds
Started Jun 27 07:09:16 PM PDT 24
Finished Jun 27 07:13:17 PM PDT 24
Peak memory 201816 kb
Host smart-c476574c-a0db-46fb-a810-89788bceea52
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139316032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.2139316032
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3503921540
Short name T675
Test name
Test status
Simulation time 328747359362 ps
CPU time 194.39 seconds
Started Jun 27 07:09:16 PM PDT 24
Finished Jun 27 07:12:32 PM PDT 24
Peak memory 201876 kb
Host smart-7066d6ef-4122-4764-993d-8d676595b90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503921540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3503921540
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2207425425
Short name T412
Test name
Test status
Simulation time 162057405678 ps
CPU time 335.22 seconds
Started Jun 27 07:09:16 PM PDT 24
Finished Jun 27 07:14:53 PM PDT 24
Peak memory 201844 kb
Host smart-f82e79c8-8e6d-4659-9914-10421e253bf2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207425425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2207425425
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.1340793212
Short name T183
Test name
Test status
Simulation time 492784726851 ps
CPU time 297.5 seconds
Started Jun 27 07:09:14 PM PDT 24
Finished Jun 27 07:14:13 PM PDT 24
Peak memory 201924 kb
Host smart-b507fea6-cba9-4d78-b5a6-183e7b9f2e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340793212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.1340793212
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.3125386418
Short name T383
Test name
Test status
Simulation time 333807242035 ps
CPU time 361.39 seconds
Started Jun 27 07:09:15 PM PDT 24
Finished Jun 27 07:15:18 PM PDT 24
Peak memory 201756 kb
Host smart-a5efbc0e-5d1f-400c-92f3-17b16aa5f0d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125386418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.3125386418
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2992137492
Short name T214
Test name
Test status
Simulation time 384989627233 ps
CPU time 932.19 seconds
Started Jun 27 07:09:15 PM PDT 24
Finished Jun 27 07:24:48 PM PDT 24
Peak memory 201784 kb
Host smart-7590af95-eb7b-4a24-a241-ed81638b307c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992137492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2992137492
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3347513964
Short name T670
Test name
Test status
Simulation time 198459369929 ps
CPU time 479.68 seconds
Started Jun 27 07:09:14 PM PDT 24
Finished Jun 27 07:17:15 PM PDT 24
Peak memory 201852 kb
Host smart-d3b3a4d2-a4ef-48b9-a7a4-d8182f674fd6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347513964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3347513964
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2797226022
Short name T362
Test name
Test status
Simulation time 89843032717 ps
CPU time 293.92 seconds
Started Jun 27 07:09:18 PM PDT 24
Finished Jun 27 07:14:13 PM PDT 24
Peak memory 202196 kb
Host smart-8ada1b21-2b89-402a-9f7e-6b1136ab9bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797226022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2797226022
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.31291339
Short name T373
Test name
Test status
Simulation time 30577312999 ps
CPU time 68.56 seconds
Started Jun 27 07:09:16 PM PDT 24
Finished Jun 27 07:10:26 PM PDT 24
Peak memory 201676 kb
Host smart-6b50c41e-1322-4e98-bdf5-18aa754cf59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31291339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.31291339
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.2958809435
Short name T374
Test name
Test status
Simulation time 3505784166 ps
CPU time 8.92 seconds
Started Jun 27 07:09:16 PM PDT 24
Finished Jun 27 07:09:26 PM PDT 24
Peak memory 201632 kb
Host smart-4b078dda-2eb3-4fa5-999f-71955374ca72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958809435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.2958809435
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.3429841416
Short name T392
Test name
Test status
Simulation time 5740976458 ps
CPU time 2.01 seconds
Started Jun 27 07:09:17 PM PDT 24
Finished Jun 27 07:09:20 PM PDT 24
Peak memory 201604 kb
Host smart-58f7e0bf-8f5d-4b10-9351-5e5d2add6286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429841416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3429841416
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3467531186
Short name T768
Test name
Test status
Simulation time 174712764509 ps
CPU time 103.4 seconds
Started Jun 27 07:09:15 PM PDT 24
Finished Jun 27 07:10:59 PM PDT 24
Peak memory 201920 kb
Host smart-e1113ad7-cc2d-45d2-aa81-3161e6436869
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467531186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3467531186
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.1870295418
Short name T437
Test name
Test status
Simulation time 285084287 ps
CPU time 1.3 seconds
Started Jun 27 07:09:30 PM PDT 24
Finished Jun 27 07:09:32 PM PDT 24
Peak memory 201620 kb
Host smart-c8ba63e5-504b-4edf-8b3c-e6cfdadb8b2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870295418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.1870295418
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.205264166
Short name T233
Test name
Test status
Simulation time 171480970289 ps
CPU time 172.39 seconds
Started Jun 27 07:09:30 PM PDT 24
Finished Jun 27 07:12:24 PM PDT 24
Peak memory 201724 kb
Host smart-f7338842-c7a8-4062-8587-97b0931f0388
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205264166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gati
ng.205264166
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.991526012
Short name T298
Test name
Test status
Simulation time 166939805645 ps
CPU time 108.6 seconds
Started Jun 27 07:09:29 PM PDT 24
Finished Jun 27 07:11:19 PM PDT 24
Peak memory 201848 kb
Host smart-196de67b-6bbb-4147-b1a0-0b893e111fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991526012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.991526012
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.3734528603
Short name T659
Test name
Test status
Simulation time 326720073278 ps
CPU time 273.44 seconds
Started Jun 27 07:09:29 PM PDT 24
Finished Jun 27 07:14:03 PM PDT 24
Peak memory 201852 kb
Host smart-45f41d66-d0b1-4473-8f69-6a31edc7db82
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734528603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.3734528603
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2717660547
Short name T5
Test name
Test status
Simulation time 319031567337 ps
CPU time 350.69 seconds
Started Jun 27 07:09:30 PM PDT 24
Finished Jun 27 07:15:22 PM PDT 24
Peak memory 201936 kb
Host smart-a11e2343-cad1-49b6-8fd5-2f2af1f84aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717660547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2717660547
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3612321477
Short name T440
Test name
Test status
Simulation time 481178832371 ps
CPU time 1034.53 seconds
Started Jun 27 07:09:30 PM PDT 24
Finished Jun 27 07:26:46 PM PDT 24
Peak memory 201708 kb
Host smart-4a1de8e6-b22e-4973-93a9-7d22fc28055f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612321477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3612321477
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.822464960
Short name T205
Test name
Test status
Simulation time 367908897867 ps
CPU time 759.51 seconds
Started Jun 27 07:09:29 PM PDT 24
Finished Jun 27 07:22:11 PM PDT 24
Peak memory 201900 kb
Host smart-a42d89cb-87c4-44d9-837b-e16bc01e250a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822464960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_
wakeup.822464960
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1603429496
Short name T41
Test name
Test status
Simulation time 201662740825 ps
CPU time 241.56 seconds
Started Jun 27 07:09:30 PM PDT 24
Finished Jun 27 07:13:33 PM PDT 24
Peak memory 201880 kb
Host smart-981cfccc-920b-4e34-873e-56c672d338ca
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603429496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1603429496
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2830691433
Short name T740
Test name
Test status
Simulation time 82413530326 ps
CPU time 425.36 seconds
Started Jun 27 07:09:31 PM PDT 24
Finished Jun 27 07:16:37 PM PDT 24
Peak memory 202140 kb
Host smart-5aa75430-8dbc-4e93-93a8-7d7331d3ac1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830691433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2830691433
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3389267829
Short name T801
Test name
Test status
Simulation time 28379173261 ps
CPU time 61.25 seconds
Started Jun 27 07:09:28 PM PDT 24
Finished Jun 27 07:10:30 PM PDT 24
Peak memory 201656 kb
Host smart-129ced36-73ba-4479-a514-7b343ffb1f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389267829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3389267829
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.775908267
Short name T688
Test name
Test status
Simulation time 4224447474 ps
CPU time 5.74 seconds
Started Jun 27 07:09:28 PM PDT 24
Finished Jun 27 07:09:35 PM PDT 24
Peak memory 201584 kb
Host smart-ed092650-2179-403d-90a9-d05514f64dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775908267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.775908267
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2212282694
Short name T379
Test name
Test status
Simulation time 5778707051 ps
CPU time 4.22 seconds
Started Jun 27 07:09:30 PM PDT 24
Finished Jun 27 07:09:36 PM PDT 24
Peak memory 201612 kb
Host smart-4d1de0c0-ba54-47b5-961c-cb2ce49f0d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212282694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2212282694
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.3403269934
Short name T166
Test name
Test status
Simulation time 402343808414 ps
CPU time 227.18 seconds
Started Jun 27 07:09:30 PM PDT 24
Finished Jun 27 07:13:19 PM PDT 24
Peak memory 201932 kb
Host smart-1a91ee71-261b-45dd-9125-40862caf1f14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403269934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.3403269934
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.110624970
Short name T431
Test name
Test status
Simulation time 492152183 ps
CPU time 1.22 seconds
Started Jun 27 07:09:44 PM PDT 24
Finished Jun 27 07:09:47 PM PDT 24
Peak memory 201612 kb
Host smart-82bfff57-44c0-426f-8b15-cd7640c5aa00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110624970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.110624970
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.274083113
Short name T782
Test name
Test status
Simulation time 524362296884 ps
CPU time 438.86 seconds
Started Jun 27 07:09:43 PM PDT 24
Finished Jun 27 07:17:03 PM PDT 24
Peak memory 201872 kb
Host smart-6ec862a2-7d3b-43ed-995b-f34dd4fc900b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274083113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.274083113
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2539546445
Short name T329
Test name
Test status
Simulation time 156962896393 ps
CPU time 373.85 seconds
Started Jun 27 07:09:43 PM PDT 24
Finished Jun 27 07:15:57 PM PDT 24
Peak memory 201824 kb
Host smart-eb7de324-bd49-4a80-b11c-1a7372943f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539546445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2539546445
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.3445195701
Short name T321
Test name
Test status
Simulation time 331690654737 ps
CPU time 688.84 seconds
Started Jun 27 07:09:29 PM PDT 24
Finished Jun 27 07:21:00 PM PDT 24
Peak memory 201896 kb
Host smart-5ea2a7c0-99bf-4ee2-a2f0-98c9e0d6de50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445195701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.3445195701
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2486924352
Short name T155
Test name
Test status
Simulation time 326456495501 ps
CPU time 768.52 seconds
Started Jun 27 07:09:43 PM PDT 24
Finished Jun 27 07:22:33 PM PDT 24
Peak memory 201864 kb
Host smart-769eda78-038f-4dc8-8742-2fbde98ab7d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486924352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.2486924352
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.3245078962
Short name T490
Test name
Test status
Simulation time 158125588535 ps
CPU time 104.9 seconds
Started Jun 27 07:09:34 PM PDT 24
Finished Jun 27 07:11:21 PM PDT 24
Peak memory 201900 kb
Host smart-f9bd643a-26d2-4b07-b0f4-de472476e2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245078962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3245078962
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.2887621644
Short name T597
Test name
Test status
Simulation time 494235841028 ps
CPU time 290.15 seconds
Started Jun 27 07:09:29 PM PDT 24
Finished Jun 27 07:14:21 PM PDT 24
Peak memory 201760 kb
Host smart-1b71babf-1058-44b5-94bf-54615d9224ec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887621644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.2887621644
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.4158435619
Short name T323
Test name
Test status
Simulation time 521703403865 ps
CPU time 630.19 seconds
Started Jun 27 07:09:45 PM PDT 24
Finished Jun 27 07:20:17 PM PDT 24
Peak memory 201884 kb
Host smart-23267707-44ff-4c6a-b5ff-b91bd5b1d413
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158435619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.4158435619
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.1637040033
Short name T569
Test name
Test status
Simulation time 201427262681 ps
CPU time 426.21 seconds
Started Jun 27 07:09:44 PM PDT 24
Finished Jun 27 07:16:52 PM PDT 24
Peak memory 201868 kb
Host smart-7ed5e9ef-5dc7-424a-8f5a-d552f7a5dc64
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637040033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.1637040033
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.570460470
Short name T516
Test name
Test status
Simulation time 123234291567 ps
CPU time 622.34 seconds
Started Jun 27 07:09:43 PM PDT 24
Finished Jun 27 07:20:06 PM PDT 24
Peak memory 202200 kb
Host smart-23f85c46-3060-4024-83a1-bc7c82c5bd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570460470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.570460470
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.1364211367
Short name T45
Test name
Test status
Simulation time 34331551418 ps
CPU time 19.26 seconds
Started Jun 27 07:09:42 PM PDT 24
Finished Jun 27 07:10:02 PM PDT 24
Peak memory 201664 kb
Host smart-8eea65d4-0a5f-464d-8c2b-e436f321e427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364211367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.1364211367
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.2761439258
Short name T592
Test name
Test status
Simulation time 3550336071 ps
CPU time 2.45 seconds
Started Jun 27 07:09:44 PM PDT 24
Finished Jun 27 07:09:48 PM PDT 24
Peak memory 201676 kb
Host smart-278901d1-f553-41ba-81d6-f012141dbe84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761439258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.2761439258
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.327221212
Short name T434
Test name
Test status
Simulation time 5626177084 ps
CPU time 4.28 seconds
Started Jun 27 07:09:30 PM PDT 24
Finished Jun 27 07:09:35 PM PDT 24
Peak memory 201632 kb
Host smart-95b18ef9-7221-4a36-9af4-3358949aadb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327221212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.327221212
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1368383952
Short name T503
Test name
Test status
Simulation time 70690437685 ps
CPU time 34.45 seconds
Started Jun 27 07:09:44 PM PDT 24
Finished Jun 27 07:10:20 PM PDT 24
Peak memory 210176 kb
Host smart-ff292676-bdde-4f9e-9669-d7fe02cc2710
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368383952 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1368383952
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2385305181
Short name T196
Test name
Test status
Simulation time 469649737 ps
CPU time 1.61 seconds
Started Jun 27 07:10:00 PM PDT 24
Finished Jun 27 07:10:19 PM PDT 24
Peak memory 201600 kb
Host smart-5dfcf688-412c-480f-944f-685a6801a80a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385305181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2385305181
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3919319950
Short name T255
Test name
Test status
Simulation time 329180642744 ps
CPU time 676.34 seconds
Started Jun 27 07:10:00 PM PDT 24
Finished Jun 27 07:21:34 PM PDT 24
Peak memory 201876 kb
Host smart-832e4bc1-5287-4928-9a5c-82b46288436e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919319950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3919319950
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.3887158073
Short name T662
Test name
Test status
Simulation time 165056078972 ps
CPU time 97.69 seconds
Started Jun 27 07:09:59 PM PDT 24
Finished Jun 27 07:11:54 PM PDT 24
Peak memory 201896 kb
Host smart-be7c76ae-dbca-4813-8f29-76bc1e183656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887158073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.3887158073
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.305090652
Short name T452
Test name
Test status
Simulation time 159966379783 ps
CPU time 363.76 seconds
Started Jun 27 07:10:00 PM PDT 24
Finished Jun 27 07:16:22 PM PDT 24
Peak memory 201856 kb
Host smart-681dd0e3-4bd4-4ca7-b7d1-f8000603d562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305090652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.305090652
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.464987609
Short name T206
Test name
Test status
Simulation time 170831262202 ps
CPU time 189.23 seconds
Started Jun 27 07:09:58 PM PDT 24
Finished Jun 27 07:13:24 PM PDT 24
Peak memory 201840 kb
Host smart-999601be-e283-475c-a1c3-90c9e38556b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=464987609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrup
t_fixed.464987609
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.3427154164
Short name T87
Test name
Test status
Simulation time 167269591427 ps
CPU time 400.58 seconds
Started Jun 27 07:09:44 PM PDT 24
Finished Jun 27 07:16:26 PM PDT 24
Peak memory 201864 kb
Host smart-70e6be45-c6fd-4dd9-810d-9e74c3be1c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427154164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3427154164
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2200715881
Short name T480
Test name
Test status
Simulation time 326614177504 ps
CPU time 284.29 seconds
Started Jun 27 07:09:44 PM PDT 24
Finished Jun 27 07:14:30 PM PDT 24
Peak memory 202064 kb
Host smart-c90991db-3627-46d7-a533-cf1fbc07f039
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200715881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2200715881
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.2331926915
Short name T403
Test name
Test status
Simulation time 399825385724 ps
CPU time 853.12 seconds
Started Jun 27 07:10:00 PM PDT 24
Finished Jun 27 07:24:31 PM PDT 24
Peak memory 201896 kb
Host smart-60e6a45c-1e8f-4d31-b5d7-53411baa9e72
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331926915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.2331926915
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.1187898038
Short name T216
Test name
Test status
Simulation time 126806089680 ps
CPU time 650.3 seconds
Started Jun 27 07:10:00 PM PDT 24
Finished Jun 27 07:21:08 PM PDT 24
Peak memory 202208 kb
Host smart-edc04ec8-10f2-4224-8e64-e59cba1e781f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187898038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1187898038
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3219316833
Short name T737
Test name
Test status
Simulation time 42277280207 ps
CPU time 46.93 seconds
Started Jun 27 07:10:00 PM PDT 24
Finished Jun 27 07:11:05 PM PDT 24
Peak memory 201664 kb
Host smart-7b2bf3b0-990e-4f0d-b2b3-76729b6750b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219316833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3219316833
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1636499726
Short name T620
Test name
Test status
Simulation time 3295088016 ps
CPU time 8.23 seconds
Started Jun 27 07:10:02 PM PDT 24
Finished Jun 27 07:10:28 PM PDT 24
Peak memory 201608 kb
Host smart-553a43c6-a072-42e8-a874-1ed59826dfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636499726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1636499726
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3723643366
Short name T564
Test name
Test status
Simulation time 5718030072 ps
CPU time 2.42 seconds
Started Jun 27 07:09:44 PM PDT 24
Finished Jun 27 07:09:48 PM PDT 24
Peak memory 201680 kb
Host smart-8c370393-b002-48b9-9720-9ae6fd4c6c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723643366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3723643366
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.3023351681
Short name T684
Test name
Test status
Simulation time 3947690090442 ps
CPU time 2115.77 seconds
Started Jun 27 07:09:59 PM PDT 24
Finished Jun 27 07:45:32 PM PDT 24
Peak memory 210428 kb
Host smart-1d00c430-7b09-4f51-a79d-d2530e0ede51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023351681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.3023351681
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.2331572537
Short name T236
Test name
Test status
Simulation time 134148209597 ps
CPU time 148.68 seconds
Started Jun 27 07:09:58 PM PDT 24
Finished Jun 27 07:12:43 PM PDT 24
Peak memory 210572 kb
Host smart-917ff45d-8c9f-4edd-9b20-f0808cb9af5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331572537 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.2331572537
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1502218054
Short name T791
Test name
Test status
Simulation time 425410765 ps
CPU time 0.91 seconds
Started Jun 27 07:10:13 PM PDT 24
Finished Jun 27 07:10:29 PM PDT 24
Peak memory 201584 kb
Host smart-e2e572ae-1f8a-4f66-89ca-30bd3600bc91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502218054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1502218054
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.2867997670
Short name T531
Test name
Test status
Simulation time 198242929418 ps
CPU time 73.39 seconds
Started Jun 27 07:10:13 PM PDT 24
Finished Jun 27 07:11:41 PM PDT 24
Peak memory 201848 kb
Host smart-2bbd032d-2209-4580-a472-29bc32688871
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867997670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.2867997670
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1744827124
Short name T759
Test name
Test status
Simulation time 167003827799 ps
CPU time 79.42 seconds
Started Jun 27 07:10:14 PM PDT 24
Finished Jun 27 07:11:47 PM PDT 24
Peak memory 201892 kb
Host smart-3da1915b-4354-40b3-8063-c14f30eea361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744827124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1744827124
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1411308845
Short name T287
Test name
Test status
Simulation time 164627712205 ps
CPU time 111.27 seconds
Started Jun 27 07:10:01 PM PDT 24
Finished Jun 27 07:12:09 PM PDT 24
Peak memory 201792 kb
Host smart-4e6cff42-b34a-4af5-9d7e-0fef8f8e9c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411308845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.1411308845
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3482506660
Short name T786
Test name
Test status
Simulation time 487888340334 ps
CPU time 280.1 seconds
Started Jun 27 07:10:02 PM PDT 24
Finished Jun 27 07:14:59 PM PDT 24
Peak memory 201840 kb
Host smart-8679befa-7a1c-4aa3-9493-2c9cdacd65e5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482506660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.3482506660
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.2796873324
Short name T571
Test name
Test status
Simulation time 490529609449 ps
CPU time 573.11 seconds
Started Jun 27 07:10:01 PM PDT 24
Finished Jun 27 07:19:51 PM PDT 24
Peak memory 201808 kb
Host smart-1bcc7ee1-e9ec-4d74-b0ca-65354a81a7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796873324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.2796873324
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.3845983250
Short name T393
Test name
Test status
Simulation time 484284438375 ps
CPU time 530.06 seconds
Started Jun 27 07:10:00 PM PDT 24
Finished Jun 27 07:19:08 PM PDT 24
Peak memory 201852 kb
Host smart-7a9a3f9c-4871-4cdb-9726-a1c09e4d5e3e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845983250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.3845983250
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.1532176762
Short name T90
Test name
Test status
Simulation time 166348452592 ps
CPU time 195.01 seconds
Started Jun 27 07:10:14 PM PDT 24
Finished Jun 27 07:13:44 PM PDT 24
Peak memory 201876 kb
Host smart-b61dd7c7-ef77-4d41-bda9-447bd7fa8c64
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532176762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.1532176762
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.2929563349
Short name T517
Test name
Test status
Simulation time 404617082767 ps
CPU time 922.81 seconds
Started Jun 27 07:10:12 PM PDT 24
Finished Jun 27 07:25:50 PM PDT 24
Peak memory 201792 kb
Host smart-a6e39aff-5e3f-47cb-a6b2-cd09a6d5fb9d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929563349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.2929563349
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.3643803597
Short name T359
Test name
Test status
Simulation time 109257651357 ps
CPU time 406.73 seconds
Started Jun 27 07:10:13 PM PDT 24
Finished Jun 27 07:17:15 PM PDT 24
Peak memory 202216 kb
Host smart-12861682-b98d-43f0-abd9-67a04bdf71ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643803597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3643803597
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.827958473
Short name T370
Test name
Test status
Simulation time 36166383488 ps
CPU time 82.06 seconds
Started Jun 27 07:10:14 PM PDT 24
Finished Jun 27 07:11:51 PM PDT 24
Peak memory 201680 kb
Host smart-c12ee562-e57a-47a9-a0be-8fc1cb30c706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827958473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.827958473
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.1545882401
Short name T197
Test name
Test status
Simulation time 3845634600 ps
CPU time 5.32 seconds
Started Jun 27 07:10:12 PM PDT 24
Finished Jun 27 07:10:33 PM PDT 24
Peak memory 201684 kb
Host smart-7036dd55-f58c-4ea1-8f9d-837536972c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545882401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1545882401
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.684175597
Short name T438
Test name
Test status
Simulation time 6209353512 ps
CPU time 4.04 seconds
Started Jun 27 07:10:00 PM PDT 24
Finished Jun 27 07:10:21 PM PDT 24
Peak memory 201688 kb
Host smart-eecd9290-7c65-4701-a944-ed5c3ad19d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684175597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.684175597
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.1636591110
Short name T157
Test name
Test status
Simulation time 240296002006 ps
CPU time 253.24 seconds
Started Jun 27 07:10:12 PM PDT 24
Finished Jun 27 07:14:41 PM PDT 24
Peak memory 201844 kb
Host smart-306cde49-3cc6-4b8e-9cf3-fa94fa6053e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636591110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.1636591110
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.2351071177
Short name T106
Test name
Test status
Simulation time 49800452549 ps
CPU time 110.34 seconds
Started Jun 27 07:10:12 PM PDT 24
Finished Jun 27 07:12:17 PM PDT 24
Peak memory 210576 kb
Host smart-ec3283a9-f02c-48b7-9759-536b1021977d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351071177 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.2351071177
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1293160255
Short name T409
Test name
Test status
Simulation time 479295799 ps
CPU time 0.87 seconds
Started Jun 27 07:10:31 PM PDT 24
Finished Jun 27 07:10:37 PM PDT 24
Peak memory 201612 kb
Host smart-ccf786ce-e2e2-4b8f-9777-66b6bb1e5375
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293160255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1293160255
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2236802708
Short name T272
Test name
Test status
Simulation time 353430909775 ps
CPU time 266.49 seconds
Started Jun 27 07:10:33 PM PDT 24
Finished Jun 27 07:15:03 PM PDT 24
Peak memory 201932 kb
Host smart-ff21a4ba-3ab3-470c-8d25-698b2c8e0684
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236802708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2236802708
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.1684598581
Short name T734
Test name
Test status
Simulation time 340927261612 ps
CPU time 221.41 seconds
Started Jun 27 07:10:14 PM PDT 24
Finished Jun 27 07:14:10 PM PDT 24
Peak memory 201940 kb
Host smart-fac8d432-47a7-4c9c-adf6-a86c003702a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684598581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.1684598581
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.4013341653
Short name T558
Test name
Test status
Simulation time 327549434977 ps
CPU time 373.24 seconds
Started Jun 27 07:10:16 PM PDT 24
Finished Jun 27 07:16:42 PM PDT 24
Peak memory 201864 kb
Host smart-975dae1e-e5b9-4c2f-9404-bf94343a8bb3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013341653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.4013341653
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.2551184835
Short name T291
Test name
Test status
Simulation time 482857370623 ps
CPU time 307.04 seconds
Started Jun 27 07:10:14 PM PDT 24
Finished Jun 27 07:15:36 PM PDT 24
Peak memory 201864 kb
Host smart-55bd6dc0-57d6-4b4f-a50e-b7e92964ca33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551184835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2551184835
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.2735957216
Short name T476
Test name
Test status
Simulation time 167695106076 ps
CPU time 208.87 seconds
Started Jun 27 07:10:15 PM PDT 24
Finished Jun 27 07:13:58 PM PDT 24
Peak memory 201860 kb
Host smart-bfcd9ab4-748e-46ce-b631-3d57e0584ec5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735957216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.2735957216
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3895786153
Short name T707
Test name
Test status
Simulation time 356575889720 ps
CPU time 739.29 seconds
Started Jun 27 07:10:13 PM PDT 24
Finished Jun 27 07:22:47 PM PDT 24
Peak memory 201932 kb
Host smart-1a103eeb-a6ec-49fc-8151-c32622484eb7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895786153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3895786153
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1475172874
Short name T12
Test name
Test status
Simulation time 392024670213 ps
CPU time 93.59 seconds
Started Jun 27 07:10:35 PM PDT 24
Finished Jun 27 07:12:11 PM PDT 24
Peak memory 201860 kb
Host smart-9479875d-6d32-4f63-94da-106a6478c6be
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475172874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.1475172874
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1310333406
Short name T699
Test name
Test status
Simulation time 90008140758 ps
CPU time 489.65 seconds
Started Jun 27 07:10:33 PM PDT 24
Finished Jun 27 07:18:46 PM PDT 24
Peak memory 202188 kb
Host smart-900b313f-7838-4cc2-bf34-59c7cdd55ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310333406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1310333406
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.3374354828
Short name T717
Test name
Test status
Simulation time 37811634891 ps
CPU time 89.2 seconds
Started Jun 27 07:10:34 PM PDT 24
Finished Jun 27 07:12:06 PM PDT 24
Peak memory 201680 kb
Host smart-467883b9-1359-4253-8fb8-71c27cda1e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374354828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.3374354828
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.1133640808
Short name T544
Test name
Test status
Simulation time 3936440688 ps
CPU time 10.01 seconds
Started Jun 27 07:10:32 PM PDT 24
Finished Jun 27 07:10:47 PM PDT 24
Peak memory 201668 kb
Host smart-d5259896-347f-4e6e-9d61-3fbd253a22a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133640808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.1133640808
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.3507976816
Short name T25
Test name
Test status
Simulation time 5670546482 ps
CPU time 3.86 seconds
Started Jun 27 07:10:14 PM PDT 24
Finished Jun 27 07:10:32 PM PDT 24
Peak memory 201612 kb
Host smart-0f3a62a9-dfd8-4451-8175-3b17a13ee575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507976816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3507976816
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3618769950
Short name T676
Test name
Test status
Simulation time 298905470484 ps
CPU time 916.03 seconds
Started Jun 27 07:10:33 PM PDT 24
Finished Jun 27 07:25:53 PM PDT 24
Peak memory 202156 kb
Host smart-1c90a416-05b3-4182-bf84-08bdc448e652
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618769950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3618769950
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3945209483
Short name T267
Test name
Test status
Simulation time 247913590742 ps
CPU time 206.43 seconds
Started Jun 27 07:10:33 PM PDT 24
Finished Jun 27 07:14:03 PM PDT 24
Peak memory 210500 kb
Host smart-36106b1e-abe5-42c1-b86a-d32139a22142
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945209483 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.3945209483
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.709215827
Short name T396
Test name
Test status
Simulation time 370124837 ps
CPU time 0.87 seconds
Started Jun 27 07:10:46 PM PDT 24
Finished Jun 27 07:10:50 PM PDT 24
Peak memory 201576 kb
Host smart-613a2f93-9bfa-431b-bef3-0dc41335d5f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709215827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.709215827
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.3726425095
Short name T320
Test name
Test status
Simulation time 518175830666 ps
CPU time 1166.62 seconds
Started Jun 27 07:10:47 PM PDT 24
Finished Jun 27 07:30:17 PM PDT 24
Peak memory 201860 kb
Host smart-26f68fcb-4247-425c-ba59-8c1bda65ae65
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726425095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.3726425095
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.682479825
Short name T340
Test name
Test status
Simulation time 382115778430 ps
CPU time 221.25 seconds
Started Jun 27 07:10:47 PM PDT 24
Finished Jun 27 07:14:31 PM PDT 24
Peak memory 201888 kb
Host smart-788472dc-1e99-4efa-a9c2-92e86c08fe97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682479825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.682479825
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2980309780
Short name T485
Test name
Test status
Simulation time 164335104181 ps
CPU time 105.6 seconds
Started Jun 27 07:10:34 PM PDT 24
Finished Jun 27 07:12:23 PM PDT 24
Peak memory 201876 kb
Host smart-c8f7d783-6f1a-4ba1-b415-b48eaf0f8778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980309780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2980309780
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2197793443
Short name T602
Test name
Test status
Simulation time 329102255819 ps
CPU time 799.36 seconds
Started Jun 27 07:10:47 PM PDT 24
Finished Jun 27 07:24:10 PM PDT 24
Peak memory 201764 kb
Host smart-2c543089-fcf4-46a0-a5c1-d8d67a38344f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197793443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2197793443
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.4162363512
Short name T175
Test name
Test status
Simulation time 330331982556 ps
CPU time 179.19 seconds
Started Jun 27 07:10:32 PM PDT 24
Finished Jun 27 07:13:36 PM PDT 24
Peak memory 201960 kb
Host smart-14a2814b-11d9-4ffa-b447-f29bcc9235ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162363512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.4162363512
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2889708293
Short name T524
Test name
Test status
Simulation time 161633017744 ps
CPU time 363.98 seconds
Started Jun 27 07:10:32 PM PDT 24
Finished Jun 27 07:16:40 PM PDT 24
Peak memory 201828 kb
Host smart-04b6da3a-00b1-45d6-b819-fa951d6a7c1e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889708293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.2889708293
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.2535426488
Short name T174
Test name
Test status
Simulation time 383763768169 ps
CPU time 801.93 seconds
Started Jun 27 07:10:47 PM PDT 24
Finished Jun 27 07:24:11 PM PDT 24
Peak memory 201968 kb
Host smart-6b87b1eb-76a1-488c-ba88-3370aa20763b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535426488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.2535426488
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.146146448
Short name T423
Test name
Test status
Simulation time 594946880492 ps
CPU time 110.88 seconds
Started Jun 27 07:10:46 PM PDT 24
Finished Jun 27 07:12:40 PM PDT 24
Peak memory 201860 kb
Host smart-8b3d62d8-9591-49ac-adf8-10bcdbf1efd7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146146448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
adc_ctrl_filters_wakeup_fixed.146146448
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.2959885419
Short name T796
Test name
Test status
Simulation time 75776598694 ps
CPU time 273.13 seconds
Started Jun 27 07:10:46 PM PDT 24
Finished Jun 27 07:15:22 PM PDT 24
Peak memory 202144 kb
Host smart-450e5854-5fd3-4763-8344-54559217ee02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959885419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.2959885419
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.1743753247
Short name T674
Test name
Test status
Simulation time 24269246590 ps
CPU time 27.2 seconds
Started Jun 27 07:10:47 PM PDT 24
Finished Jun 27 07:11:18 PM PDT 24
Peak memory 201632 kb
Host smart-93527a45-0383-4b70-8269-90dc63a67eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743753247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.1743753247
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.1513035754
Short name T510
Test name
Test status
Simulation time 5239024998 ps
CPU time 6.57 seconds
Started Jun 27 07:10:48 PM PDT 24
Finished Jun 27 07:10:57 PM PDT 24
Peak memory 201672 kb
Host smart-e76742d4-e438-4f09-b7dc-9d74b5ccd9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513035754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.1513035754
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.2648656717
Short name T513
Test name
Test status
Simulation time 6004794684 ps
CPU time 7.65 seconds
Started Jun 27 07:10:31 PM PDT 24
Finished Jun 27 07:10:44 PM PDT 24
Peak memory 201672 kb
Host smart-7c033ee0-8160-4d82-9d44-da90b30b0286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648656717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2648656717
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3606757577
Short name T326
Test name
Test status
Simulation time 346566666819 ps
CPU time 763.24 seconds
Started Jun 27 07:10:47 PM PDT 24
Finished Jun 27 07:23:34 PM PDT 24
Peak memory 201804 kb
Host smart-a18ce27c-561e-4471-9871-722d368fc4e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606757577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3606757577
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.3643621860
Short name T34
Test name
Test status
Simulation time 88889174667 ps
CPU time 40.58 seconds
Started Jun 27 07:10:47 PM PDT 24
Finished Jun 27 07:11:30 PM PDT 24
Peak memory 210572 kb
Host smart-0fdd93e9-5a46-4ba4-bbe2-b57c6af981f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643621860 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.3643621860
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.70052836
Short name T70
Test name
Test status
Simulation time 475345615 ps
CPU time 1.55 seconds
Started Jun 27 07:11:03 PM PDT 24
Finished Jun 27 07:11:07 PM PDT 24
Peak memory 201632 kb
Host smart-a23c7238-557b-49a8-82ab-9812bc5539cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70052836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.70052836
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3358851389
Short name T192
Test name
Test status
Simulation time 394312419812 ps
CPU time 106.69 seconds
Started Jun 27 07:11:03 PM PDT 24
Finished Jun 27 07:12:51 PM PDT 24
Peak memory 201888 kb
Host smart-b1c09430-6562-4751-ab14-3917ee0f4cce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358851389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3358851389
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.1423583833
Short name T645
Test name
Test status
Simulation time 170409984440 ps
CPU time 82.32 seconds
Started Jun 27 07:11:03 PM PDT 24
Finished Jun 27 07:12:27 PM PDT 24
Peak memory 201884 kb
Host smart-2d871790-9b4a-4f51-8d19-004ac9ac4a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423583833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1423583833
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1245062879
Short name T555
Test name
Test status
Simulation time 166009782839 ps
CPU time 211.32 seconds
Started Jun 27 07:11:03 PM PDT 24
Finished Jun 27 07:14:36 PM PDT 24
Peak memory 201936 kb
Host smart-4ffb1440-1c7b-4245-8205-a7f45be71d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245062879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1245062879
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.261491724
Short name T576
Test name
Test status
Simulation time 169762960740 ps
CPU time 61.65 seconds
Started Jun 27 07:11:03 PM PDT 24
Finished Jun 27 07:12:07 PM PDT 24
Peak memory 201828 kb
Host smart-1e02eca2-b87b-4636-a762-21e500db9510
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=261491724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrup
t_fixed.261491724
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.3206917892
Short name T473
Test name
Test status
Simulation time 485000396511 ps
CPU time 1048.78 seconds
Started Jun 27 07:11:03 PM PDT 24
Finished Jun 27 07:28:34 PM PDT 24
Peak memory 201900 kb
Host smart-a09b5ee3-a436-47a1-bdf5-1cc35ffb8426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206917892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.3206917892
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.107400664
Short name T419
Test name
Test status
Simulation time 169700306774 ps
CPU time 38.39 seconds
Started Jun 27 07:11:03 PM PDT 24
Finished Jun 27 07:11:43 PM PDT 24
Peak memory 201848 kb
Host smart-2203a7eb-490e-4095-b9a5-d100e033ea0f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=107400664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixe
d.107400664
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2143468631
Short name T171
Test name
Test status
Simulation time 173042265034 ps
CPU time 383.33 seconds
Started Jun 27 07:11:02 PM PDT 24
Finished Jun 27 07:17:28 PM PDT 24
Peak memory 201864 kb
Host smart-2d598af9-6bca-412c-b991-c8fd2a9a8fb5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143468631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2143468631
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2541272304
Short name T739
Test name
Test status
Simulation time 197092889093 ps
CPU time 454.02 seconds
Started Jun 27 07:11:03 PM PDT 24
Finished Jun 27 07:18:40 PM PDT 24
Peak memory 201844 kb
Host smart-bbc69f9f-ea90-484e-918b-73f10205c127
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541272304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2541272304
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.754463601
Short name T46
Test name
Test status
Simulation time 121684596748 ps
CPU time 391.24 seconds
Started Jun 27 07:11:03 PM PDT 24
Finished Jun 27 07:17:36 PM PDT 24
Peak memory 202264 kb
Host smart-c34c1e19-cd3a-49f7-8d88-50925f6ba304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754463601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.754463601
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2041559267
Short name T718
Test name
Test status
Simulation time 45285105226 ps
CPU time 108.92 seconds
Started Jun 27 07:11:03 PM PDT 24
Finished Jun 27 07:12:54 PM PDT 24
Peak memory 201656 kb
Host smart-096edaa3-9221-450f-8618-a06b67854b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041559267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2041559267
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3223062491
Short name T111
Test name
Test status
Simulation time 4658908526 ps
CPU time 2.4 seconds
Started Jun 27 07:11:03 PM PDT 24
Finished Jun 27 07:11:08 PM PDT 24
Peak memory 201656 kb
Host smart-ecae638c-744e-49ca-9654-af38ceabf4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223062491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3223062491
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.1177303890
Short name T500
Test name
Test status
Simulation time 6061702058 ps
CPU time 7.6 seconds
Started Jun 27 07:10:47 PM PDT 24
Finished Jun 27 07:10:57 PM PDT 24
Peak memory 201676 kb
Host smart-ac409673-c739-46f0-849d-571d2ce605a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177303890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1177303890
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.712252554
Short name T345
Test name
Test status
Simulation time 321231119489 ps
CPU time 697.93 seconds
Started Jun 27 07:11:01 PM PDT 24
Finished Jun 27 07:22:40 PM PDT 24
Peak memory 201936 kb
Host smart-ab06588c-4fb5-4894-a613-a2fb45138ff3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712252554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
712252554
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.3088672419
Short name T224
Test name
Test status
Simulation time 145472211438 ps
CPU time 161.39 seconds
Started Jun 27 07:11:04 PM PDT 24
Finished Jun 27 07:13:47 PM PDT 24
Peak memory 210732 kb
Host smart-c32dc531-479d-448d-9061-319a87b21b03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088672419 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.3088672419
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.4147878046
Short name T468
Test name
Test status
Simulation time 337934310 ps
CPU time 1.36 seconds
Started Jun 27 07:11:14 PM PDT 24
Finished Jun 27 07:11:18 PM PDT 24
Peak memory 201604 kb
Host smart-27908916-60dc-43dd-a4f9-eafb2838b0c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147878046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.4147878046
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.3974184099
Short name T346
Test name
Test status
Simulation time 173511282501 ps
CPU time 45.64 seconds
Started Jun 27 07:11:15 PM PDT 24
Finished Jun 27 07:12:04 PM PDT 24
Peak memory 201920 kb
Host smart-3db99efd-c8df-48f9-8357-c7e4221bdc65
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974184099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.3974184099
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.3244254557
Short name T351
Test name
Test status
Simulation time 163807289891 ps
CPU time 99.73 seconds
Started Jun 27 07:11:16 PM PDT 24
Finished Jun 27 07:12:59 PM PDT 24
Peak memory 201868 kb
Host smart-11b2a26a-1b8a-4cc8-9377-dc008f652409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244254557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3244254557
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.800357778
Short name T491
Test name
Test status
Simulation time 490827001691 ps
CPU time 302.72 seconds
Started Jun 27 07:11:03 PM PDT 24
Finished Jun 27 07:16:08 PM PDT 24
Peak memory 201888 kb
Host smart-51543629-e04c-45df-820a-e419d1fb9972
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=800357778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrup
t_fixed.800357778
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.1278446689
Short name T622
Test name
Test status
Simulation time 322798964776 ps
CPU time 402.55 seconds
Started Jun 27 07:11:02 PM PDT 24
Finished Jun 27 07:17:46 PM PDT 24
Peak memory 201872 kb
Host smart-20dcad2e-d9c6-4aca-818f-0b9b45249d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278446689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1278446689
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3724562345
Short name T445
Test name
Test status
Simulation time 492813857175 ps
CPU time 606.45 seconds
Started Jun 27 07:11:02 PM PDT 24
Finished Jun 27 07:21:09 PM PDT 24
Peak memory 201864 kb
Host smart-f055c681-3649-438a-ad9e-d372ca0c6acf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724562345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3724562345
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3816157753
Short name T407
Test name
Test status
Simulation time 199557127500 ps
CPU time 431.99 seconds
Started Jun 27 07:11:15 PM PDT 24
Finished Jun 27 07:18:30 PM PDT 24
Peak memory 201924 kb
Host smart-88dca237-701f-4142-834e-736cc5bc0bff
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816157753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3816157753
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.53444449
Short name T549
Test name
Test status
Simulation time 26997519213 ps
CPU time 64.59 seconds
Started Jun 27 07:11:16 PM PDT 24
Finished Jun 27 07:12:24 PM PDT 24
Peak memory 201704 kb
Host smart-69ce031f-40b0-454b-8df4-0f97e510b42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53444449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.53444449
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3120300500
Short name T410
Test name
Test status
Simulation time 4590066931 ps
CPU time 7.88 seconds
Started Jun 27 07:11:15 PM PDT 24
Finished Jun 27 07:11:25 PM PDT 24
Peak memory 201688 kb
Host smart-97d524dd-801f-4a6f-ad19-43651d417f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120300500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3120300500
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1038957851
Short name T540
Test name
Test status
Simulation time 6152779099 ps
CPU time 16.47 seconds
Started Jun 27 07:11:02 PM PDT 24
Finished Jun 27 07:11:20 PM PDT 24
Peak memory 201668 kb
Host smart-eb0cdcce-be44-49ff-ac0d-bf6db5e3e353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038957851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1038957851
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1524270621
Short name T416
Test name
Test status
Simulation time 329633096103 ps
CPU time 100.35 seconds
Started Jun 27 07:11:17 PM PDT 24
Finished Jun 27 07:13:00 PM PDT 24
Peak memory 201880 kb
Host smart-4084519e-26af-425e-b91b-c88426ea7b38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524270621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1524270621
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1232211207
Short name T658
Test name
Test status
Simulation time 97158521742 ps
CPU time 150.34 seconds
Started Jun 27 07:11:16 PM PDT 24
Finished Jun 27 07:13:49 PM PDT 24
Peak memory 202612 kb
Host smart-5e8678fe-9d84-4fd7-8949-a3e5cc92a8eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232211207 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.1232211207
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.1369255569
Short name T667
Test name
Test status
Simulation time 327524654 ps
CPU time 1.37 seconds
Started Jun 27 07:11:16 PM PDT 24
Finished Jun 27 07:11:20 PM PDT 24
Peak memory 201640 kb
Host smart-e2eb3703-09e4-41ac-9f6f-4964f18a002f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369255569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.1369255569
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3296222102
Short name T289
Test name
Test status
Simulation time 202434953011 ps
CPU time 490.2 seconds
Started Jun 27 07:11:15 PM PDT 24
Finished Jun 27 07:19:27 PM PDT 24
Peak memory 201820 kb
Host smart-e70f87f5-2150-4fa2-a171-64c1cc26c7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296222102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3296222102
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.47262489
Short name T101
Test name
Test status
Simulation time 330385255732 ps
CPU time 814.69 seconds
Started Jun 27 07:11:17 PM PDT 24
Finished Jun 27 07:24:55 PM PDT 24
Peak memory 201888 kb
Host smart-706185bb-f9ff-47a3-a639-01efe87e6a34
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=47262489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt
_fixed.47262489
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.218373787
Short name T625
Test name
Test status
Simulation time 166052131797 ps
CPU time 364.57 seconds
Started Jun 27 07:11:13 PM PDT 24
Finished Jun 27 07:17:19 PM PDT 24
Peak memory 201888 kb
Host smart-6c449fa3-5f57-47a9-b625-9b27f7a56657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218373787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.218373787
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.700709244
Short name T767
Test name
Test status
Simulation time 492677652751 ps
CPU time 1134.01 seconds
Started Jun 27 07:11:16 PM PDT 24
Finished Jun 27 07:30:13 PM PDT 24
Peak memory 201800 kb
Host smart-9e2e3399-a7dd-4aaf-ae3b-11732154cdeb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=700709244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixe
d.700709244
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.4177245427
Short name T249
Test name
Test status
Simulation time 563181490771 ps
CPU time 1357.79 seconds
Started Jun 27 07:11:16 PM PDT 24
Finished Jun 27 07:33:57 PM PDT 24
Peak memory 201944 kb
Host smart-356cc422-bc58-40e8-86dd-a554ac73f74c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177245427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.4177245427
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2607040911
Short name T719
Test name
Test status
Simulation time 595867093585 ps
CPU time 633.89 seconds
Started Jun 27 07:11:14 PM PDT 24
Finished Jun 27 07:21:51 PM PDT 24
Peak memory 201860 kb
Host smart-602b82b5-8dfe-491b-82a7-3a7be5644a0d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607040911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2607040911
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2753161532
Short name T222
Test name
Test status
Simulation time 122430374227 ps
CPU time 508.39 seconds
Started Jun 27 07:11:17 PM PDT 24
Finished Jun 27 07:19:48 PM PDT 24
Peak memory 202204 kb
Host smart-cff282e1-fd53-4b62-b781-83ed1d38e6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753161532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2753161532
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.434347127
Short name T738
Test name
Test status
Simulation time 38488446993 ps
CPU time 8.87 seconds
Started Jun 27 07:11:15 PM PDT 24
Finished Jun 27 07:11:26 PM PDT 24
Peak memory 201668 kb
Host smart-d4f67eba-6f7c-4d8c-8f50-b0626f338ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434347127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.434347127
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.3475654783
Short name T466
Test name
Test status
Simulation time 4778495320 ps
CPU time 3.54 seconds
Started Jun 27 07:11:18 PM PDT 24
Finished Jun 27 07:11:24 PM PDT 24
Peak memory 201528 kb
Host smart-6ac554af-beea-416c-96bc-3848011a3002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475654783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.3475654783
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2351292215
Short name T363
Test name
Test status
Simulation time 5794769533 ps
CPU time 15.43 seconds
Started Jun 27 07:11:17 PM PDT 24
Finished Jun 27 07:11:35 PM PDT 24
Peak memory 201632 kb
Host smart-86ddc44b-dd74-4b4a-b913-dac0134dcff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351292215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2351292215
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1305710376
Short name T766
Test name
Test status
Simulation time 339737575243 ps
CPU time 800.14 seconds
Started Jun 27 07:11:17 PM PDT 24
Finished Jun 27 07:24:40 PM PDT 24
Peak memory 201776 kb
Host smart-2521e126-9677-4381-a573-d23407c8e83d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305710376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1305710376
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3458619717
Short name T709
Test name
Test status
Simulation time 70698108897 ps
CPU time 165.39 seconds
Started Jun 27 07:11:16 PM PDT 24
Finished Jun 27 07:14:04 PM PDT 24
Peak memory 210484 kb
Host smart-f13ba918-d7f8-4588-9b20-2401dde2c7d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458619717 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3458619717
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.131683270
Short name T79
Test name
Test status
Simulation time 483471618 ps
CPU time 1.16 seconds
Started Jun 27 07:06:39 PM PDT 24
Finished Jun 27 07:06:49 PM PDT 24
Peak memory 201640 kb
Host smart-c2938757-74ac-420f-9932-83b3eae2f45e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131683270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.131683270
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3100255511
Short name T760
Test name
Test status
Simulation time 159363670304 ps
CPU time 91.46 seconds
Started Jun 27 07:06:41 PM PDT 24
Finished Jun 27 07:08:22 PM PDT 24
Peak memory 201932 kb
Host smart-88ca0da1-31fa-4262-a3f8-7d28e5bc5dde
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100255511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3100255511
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.2336565103
Short name T319
Test name
Test status
Simulation time 333041887423 ps
CPU time 205.4 seconds
Started Jun 27 07:06:37 PM PDT 24
Finished Jun 27 07:10:09 PM PDT 24
Peak memory 201940 kb
Host smart-ee294af6-edd4-4a9e-a727-8378b6226af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336565103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.2336565103
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.3464413040
Short name T371
Test name
Test status
Simulation time 167861346857 ps
CPU time 397.7 seconds
Started Jun 27 07:06:40 PM PDT 24
Finished Jun 27 07:13:27 PM PDT 24
Peak memory 201796 kb
Host smart-691e19ad-244b-4a5e-829e-bc3392b2a323
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464413040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.3464413040
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.1257325398
Short name T506
Test name
Test status
Simulation time 164020852373 ps
CPU time 98.82 seconds
Started Jun 27 07:06:39 PM PDT 24
Finished Jun 27 07:08:25 PM PDT 24
Peak memory 201948 kb
Host smart-8791f3e4-47c3-470f-b4b3-f88b912255b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257325398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1257325398
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.696862787
Short name T651
Test name
Test status
Simulation time 170487254110 ps
CPU time 358.42 seconds
Started Jun 27 07:06:40 PM PDT 24
Finished Jun 27 07:12:48 PM PDT 24
Peak memory 201868 kb
Host smart-58c9b1f1-ee5a-4e25-95b9-032b260ab0e6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=696862787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed
.696862787
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1430250208
Short name T764
Test name
Test status
Simulation time 184494937358 ps
CPU time 423.82 seconds
Started Jun 27 07:06:42 PM PDT 24
Finished Jun 27 07:13:55 PM PDT 24
Peak memory 201944 kb
Host smart-5ca07f66-4ee2-44f2-8db6-7c2dc54da99e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430250208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1430250208
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.818806270
Short name T520
Test name
Test status
Simulation time 600726409496 ps
CPU time 349.4 seconds
Started Jun 27 07:06:40 PM PDT 24
Finished Jun 27 07:12:39 PM PDT 24
Peak memory 201884 kb
Host smart-ca228cae-d4f2-4e5e-9746-957e7b6dcbac
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818806270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.a
dc_ctrl_filters_wakeup_fixed.818806270
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3406963349
Short name T453
Test name
Test status
Simulation time 83649969839 ps
CPU time 320.89 seconds
Started Jun 27 07:06:37 PM PDT 24
Finished Jun 27 07:12:05 PM PDT 24
Peak memory 202192 kb
Host smart-76f43bf0-0169-4244-9adf-11718b84153f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406963349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3406963349
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1243657176
Short name T600
Test name
Test status
Simulation time 43659908240 ps
CPU time 23.48 seconds
Started Jun 27 07:06:39 PM PDT 24
Finished Jun 27 07:07:11 PM PDT 24
Peak memory 201656 kb
Host smart-4cc438fa-48cf-42c4-98b7-770e68c1a792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243657176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1243657176
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.869791376
Short name T595
Test name
Test status
Simulation time 4568620731 ps
CPU time 6.01 seconds
Started Jun 27 07:06:39 PM PDT 24
Finished Jun 27 07:06:52 PM PDT 24
Peak memory 201672 kb
Host smart-3fb0dbe2-9036-478c-9ed3-2f9b6fe13da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869791376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.869791376
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2411207890
Short name T64
Test name
Test status
Simulation time 8532163131 ps
CPU time 19.86 seconds
Started Jun 27 07:06:41 PM PDT 24
Finished Jun 27 07:07:10 PM PDT 24
Peak memory 218192 kb
Host smart-92972285-0686-4dd0-89f0-6ca66519b02a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411207890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2411207890
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2755698984
Short name T450
Test name
Test status
Simulation time 5826597210 ps
CPU time 6.69 seconds
Started Jun 27 07:06:40 PM PDT 24
Finished Jun 27 07:06:55 PM PDT 24
Peak memory 201680 kb
Host smart-42493ddb-f066-4f59-904d-118831c0e02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755698984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2755698984
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.1330161031
Short name T668
Test name
Test status
Simulation time 201264375133 ps
CPU time 123.22 seconds
Started Jun 27 07:06:43 PM PDT 24
Finished Jun 27 07:08:56 PM PDT 24
Peak memory 201860 kb
Host smart-d50a68ad-5d50-43e5-bb1d-ea1f243ab7ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330161031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
1330161031
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2350165571
Short name T565
Test name
Test status
Simulation time 37745023246 ps
CPU time 46.39 seconds
Started Jun 27 07:06:37 PM PDT 24
Finished Jun 27 07:07:28 PM PDT 24
Peak memory 211016 kb
Host smart-7bf6f5fa-57e7-42e0-accf-95c97c16c300
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350165571 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.2350165571
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2971500396
Short name T404
Test name
Test status
Simulation time 474116468 ps
CPU time 1.18 seconds
Started Jun 27 07:11:30 PM PDT 24
Finished Jun 27 07:11:52 PM PDT 24
Peak memory 201604 kb
Host smart-cd50b159-5d6a-4cf7-8e2c-d63acc22cc7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971500396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2971500396
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.3165274524
Short name T712
Test name
Test status
Simulation time 485041378709 ps
CPU time 296.81 seconds
Started Jun 27 07:11:32 PM PDT 24
Finished Jun 27 07:16:57 PM PDT 24
Peak memory 201860 kb
Host smart-d8360d7e-c664-44fe-8477-6c4cd529f604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165274524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3165274524
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.337193728
Short name T7
Test name
Test status
Simulation time 338381692343 ps
CPU time 519.71 seconds
Started Jun 27 07:11:31 PM PDT 24
Finished Jun 27 07:20:37 PM PDT 24
Peak memory 201808 kb
Host smart-2b18449d-791b-444e-8a3e-ad6f69022771
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=337193728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrup
t_fixed.337193728
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.1575894882
Short name T522
Test name
Test status
Simulation time 492276908379 ps
CPU time 1166.28 seconds
Started Jun 27 07:11:17 PM PDT 24
Finished Jun 27 07:30:46 PM PDT 24
Peak memory 201812 kb
Host smart-2389c49d-33f0-40d5-928a-1085f864827c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575894882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1575894882
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.632914678
Short name T448
Test name
Test status
Simulation time 168188902080 ps
CPU time 93.3 seconds
Started Jun 27 07:11:15 PM PDT 24
Finished Jun 27 07:12:51 PM PDT 24
Peak memory 201876 kb
Host smart-c2c97bce-4c31-4a4d-a552-35d53c81118b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=632914678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixe
d.632914678
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2511442725
Short name T512
Test name
Test status
Simulation time 392940501277 ps
CPU time 220.48 seconds
Started Jun 27 07:11:31 PM PDT 24
Finished Jun 27 07:15:38 PM PDT 24
Peak memory 202088 kb
Host smart-fde52ad3-7bb3-4cea-9ab5-a2ac357aece9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511442725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2511442725
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2588064703
Short name T408
Test name
Test status
Simulation time 86224375639 ps
CPU time 315.52 seconds
Started Jun 27 07:11:29 PM PDT 24
Finished Jun 27 07:17:07 PM PDT 24
Peak memory 202148 kb
Host smart-8f10860f-5824-4f45-b345-e9b789622e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588064703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2588064703
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.1097527495
Short name T769
Test name
Test status
Simulation time 34462407401 ps
CPU time 81.7 seconds
Started Jun 27 07:11:30 PM PDT 24
Finished Jun 27 07:13:16 PM PDT 24
Peak memory 201672 kb
Host smart-85e353c4-3102-4f76-af0a-f30858eca01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097527495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1097527495
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.229447036
Short name T732
Test name
Test status
Simulation time 3868904710 ps
CPU time 2.69 seconds
Started Jun 27 07:11:32 PM PDT 24
Finished Jun 27 07:12:04 PM PDT 24
Peak memory 201696 kb
Host smart-6d449f49-2f4d-4d1c-a4e4-cb1f2b3e89d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229447036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.229447036
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.2522059261
Short name T733
Test name
Test status
Simulation time 6031959152 ps
CPU time 15.26 seconds
Started Jun 27 07:11:14 PM PDT 24
Finished Jun 27 07:11:32 PM PDT 24
Peak memory 201680 kb
Host smart-57a088b5-f17b-460f-8967-a5d4ff910c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522059261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2522059261
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.197179217
Short name T354
Test name
Test status
Simulation time 339741775900 ps
CPU time 438.19 seconds
Started Jun 27 07:11:31 PM PDT 24
Finished Jun 27 07:19:15 PM PDT 24
Peak memory 201864 kb
Host smart-fc542d08-472d-4a0d-8de0-dccb9ba9016c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197179217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.
197179217
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.1295021205
Short name T33
Test name
Test status
Simulation time 34467399400 ps
CPU time 21.71 seconds
Started Jun 27 07:11:31 PM PDT 24
Finished Jun 27 07:12:18 PM PDT 24
Peak memory 210264 kb
Host smart-52f869bc-f0a6-4e3d-b453-32ee6025b3f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295021205 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.1295021205
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.2055290812
Short name T697
Test name
Test status
Simulation time 412983513 ps
CPU time 0.85 seconds
Started Jun 27 07:11:44 PM PDT 24
Finished Jun 27 07:12:24 PM PDT 24
Peak memory 201612 kb
Host smart-385a7770-eaf3-4f2d-9eb3-e5f0f59aeceb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055290812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2055290812
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1026735633
Short name T462
Test name
Test status
Simulation time 180735036697 ps
CPU time 99.91 seconds
Started Jun 27 07:11:45 PM PDT 24
Finished Jun 27 07:14:06 PM PDT 24
Peak memory 201872 kb
Host smart-1572c926-e731-4585-91e9-d82e07a0b991
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026735633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1026735633
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.603753199
Short name T795
Test name
Test status
Simulation time 167480168465 ps
CPU time 334.24 seconds
Started Jun 27 07:11:31 PM PDT 24
Finished Jun 27 07:17:32 PM PDT 24
Peak memory 201884 kb
Host smart-a69f55d3-f575-41ec-9841-1835a8298c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603753199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.603753199
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3728789042
Short name T726
Test name
Test status
Simulation time 329150361986 ps
CPU time 211.3 seconds
Started Jun 27 07:11:46 PM PDT 24
Finished Jun 27 07:15:58 PM PDT 24
Peak memory 201852 kb
Host smart-1ec10df2-d3b5-46ed-bf3c-bc3b177f384a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728789042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3728789042
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.3003695357
Short name T611
Test name
Test status
Simulation time 158135539225 ps
CPU time 364.24 seconds
Started Jun 27 07:11:33 PM PDT 24
Finished Jun 27 07:18:05 PM PDT 24
Peak memory 201868 kb
Host smart-6baa8f2d-e6d3-434b-9753-1539aff6c4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003695357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3003695357
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2824708858
Short name T421
Test name
Test status
Simulation time 325914650659 ps
CPU time 740.86 seconds
Started Jun 27 07:11:30 PM PDT 24
Finished Jun 27 07:24:12 PM PDT 24
Peak memory 201844 kb
Host smart-dfaa4261-549e-4fd9-8c0e-aa4b61b52e32
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824708858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2824708858
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2734454395
Short name T168
Test name
Test status
Simulation time 565846213755 ps
CPU time 109.66 seconds
Started Jun 27 07:11:44 PM PDT 24
Finished Jun 27 07:14:13 PM PDT 24
Peak memory 201868 kb
Host smart-cc7d7b45-9748-4a52-9cad-49364a03e178
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734454395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2734454395
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2282540174
Short name T495
Test name
Test status
Simulation time 402808520745 ps
CPU time 864.74 seconds
Started Jun 27 07:11:45 PM PDT 24
Finished Jun 27 07:26:51 PM PDT 24
Peak memory 201852 kb
Host smart-88d5a5d7-6767-4c02-ba1c-225962005f6f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282540174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.2282540174
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.1693201145
Short name T225
Test name
Test status
Simulation time 130555136712 ps
CPU time 512.23 seconds
Started Jun 27 07:11:45 PM PDT 24
Finished Jun 27 07:20:58 PM PDT 24
Peak memory 202196 kb
Host smart-2eddfecf-9f2d-4bcf-a3f5-aaa3b19f1432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693201145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1693201145
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.3489090040
Short name T575
Test name
Test status
Simulation time 21930740387 ps
CPU time 25.24 seconds
Started Jun 27 07:11:45 PM PDT 24
Finished Jun 27 07:12:51 PM PDT 24
Peak memory 201700 kb
Host smart-0b8ef522-134e-4ca1-bbe9-e8d34fbee3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489090040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3489090040
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.174430118
Short name T654
Test name
Test status
Simulation time 3452935074 ps
CPU time 8.47 seconds
Started Jun 27 07:11:45 PM PDT 24
Finished Jun 27 07:12:34 PM PDT 24
Peak memory 201652 kb
Host smart-3483d461-4d53-4783-b7fa-074a01fde423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174430118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.174430118
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.2135875974
Short name T415
Test name
Test status
Simulation time 5811266262 ps
CPU time 3.97 seconds
Started Jun 27 07:11:31 PM PDT 24
Finished Jun 27 07:12:01 PM PDT 24
Peak memory 201648 kb
Host smart-cabe6ae0-9e3c-4df2-99a2-7edd714fbefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135875974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.2135875974
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.3601626452
Short name T248
Test name
Test status
Simulation time 358565271307 ps
CPU time 815.08 seconds
Started Jun 27 07:11:47 PM PDT 24
Finished Jun 27 07:26:05 PM PDT 24
Peak memory 201936 kb
Host smart-b72d618d-e9df-49b4-82ed-c26f9748b15c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601626452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.3601626452
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3583040612
Short name T318
Test name
Test status
Simulation time 355495615717 ps
CPU time 488.09 seconds
Started Jun 27 07:11:47 PM PDT 24
Finished Jun 27 07:20:38 PM PDT 24
Peak memory 210528 kb
Host smart-a42d3242-39fa-4c6c-8999-b1b23e69dabf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583040612 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3583040612
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.959082701
Short name T641
Test name
Test status
Simulation time 313283683 ps
CPU time 1.28 seconds
Started Jun 27 07:12:01 PM PDT 24
Finished Jun 27 07:13:09 PM PDT 24
Peak memory 201612 kb
Host smart-0239c03e-8f37-4a60-a8fd-78603c7654bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959082701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.959082701
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.574380234
Short name T690
Test name
Test status
Simulation time 166252668729 ps
CPU time 302.22 seconds
Started Jun 27 07:12:02 PM PDT 24
Finished Jun 27 07:18:10 PM PDT 24
Peak memory 201828 kb
Host smart-32e79725-d609-4f41-a525-5779e64b8196
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574380234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gati
ng.574380234
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.151706968
Short name T749
Test name
Test status
Simulation time 326640792000 ps
CPU time 132.37 seconds
Started Jun 27 07:12:00 PM PDT 24
Finished Jun 27 07:15:09 PM PDT 24
Peak memory 201904 kb
Host smart-7adfcd55-202f-4ed0-9030-1f2d74746eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151706968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.151706968
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.1743043514
Short name T281
Test name
Test status
Simulation time 497212294524 ps
CPU time 306.91 seconds
Started Jun 27 07:11:45 PM PDT 24
Finished Jun 27 07:17:33 PM PDT 24
Peak memory 201880 kb
Host smart-96943b33-00b8-4d22-8085-8982d556b0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743043514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.1743043514
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.4279771492
Short name T579
Test name
Test status
Simulation time 162754677348 ps
CPU time 189.4 seconds
Started Jun 27 07:11:45 PM PDT 24
Finished Jun 27 07:15:36 PM PDT 24
Peak memory 201776 kb
Host smart-86f15e87-dbec-4dfe-802d-8a55df70a4ce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279771492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.4279771492
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.333344050
Short name T652
Test name
Test status
Simulation time 326050282325 ps
CPU time 703.6 seconds
Started Jun 27 07:11:46 PM PDT 24
Finished Jun 27 07:24:10 PM PDT 24
Peak memory 201888 kb
Host smart-59a55702-3b9e-4c0c-b487-ca12ec2acddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333344050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.333344050
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3293219935
Short name T390
Test name
Test status
Simulation time 325774141772 ps
CPU time 182.87 seconds
Started Jun 27 07:11:45 PM PDT 24
Finished Jun 27 07:15:28 PM PDT 24
Peak memory 201852 kb
Host smart-0e999aa0-1698-47d0-80a8-5c0a4464b066
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293219935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.3293219935
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.180646517
Short name T104
Test name
Test status
Simulation time 175117698863 ps
CPU time 98.79 seconds
Started Jun 27 07:11:45 PM PDT 24
Finished Jun 27 07:14:05 PM PDT 24
Peak memory 201864 kb
Host smart-f6482187-d72f-4475-9b83-6a5a5b39d111
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180646517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.180646517
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.832219247
Short name T598
Test name
Test status
Simulation time 631081210672 ps
CPU time 1419.82 seconds
Started Jun 27 07:12:01 PM PDT 24
Finished Jun 27 07:36:48 PM PDT 24
Peak memory 201860 kb
Host smart-57a7f356-b46f-4755-b0b3-e2d26442f07a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832219247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
adc_ctrl_filters_wakeup_fixed.832219247
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.3545778906
Short name T361
Test name
Test status
Simulation time 105633067136 ps
CPU time 363.78 seconds
Started Jun 27 07:12:00 PM PDT 24
Finished Jun 27 07:19:00 PM PDT 24
Peak memory 202204 kb
Host smart-e04cdc2a-12cb-42b5-a139-c59dff129565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545778906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3545778906
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2182698847
Short name T581
Test name
Test status
Simulation time 43677848416 ps
CPU time 26.48 seconds
Started Jun 27 07:12:02 PM PDT 24
Finished Jun 27 07:13:34 PM PDT 24
Peak memory 201688 kb
Host smart-5b28f44b-cde5-4740-a21e-554c3f6bb3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182698847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2182698847
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3272132802
Short name T365
Test name
Test status
Simulation time 5362007015 ps
CPU time 6.73 seconds
Started Jun 27 07:12:00 PM PDT 24
Finished Jun 27 07:13:03 PM PDT 24
Peak memory 201692 kb
Host smart-9bb2aaf6-dbbd-4a0c-b36a-247deb135aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272132802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3272132802
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.1405364750
Short name T1
Test name
Test status
Simulation time 5722511856 ps
CPU time 13.58 seconds
Started Jun 27 07:11:48 PM PDT 24
Finished Jun 27 07:12:43 PM PDT 24
Peak memory 201680 kb
Host smart-cf00f767-cd21-457e-a3ef-62014097db08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405364750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.1405364750
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.1363488130
Short name T239
Test name
Test status
Simulation time 353751472136 ps
CPU time 251.21 seconds
Started Jun 27 07:12:00 PM PDT 24
Finished Jun 27 07:17:18 PM PDT 24
Peak memory 201924 kb
Host smart-414925e0-0d70-48a5-92c6-11d363ee6cc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363488130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.1363488130
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.4242007519
Short name T493
Test name
Test status
Simulation time 125715719548 ps
CPU time 193.95 seconds
Started Jun 27 07:12:00 PM PDT 24
Finished Jun 27 07:16:10 PM PDT 24
Peak memory 210404 kb
Host smart-645dd522-f0dd-432e-86bb-3a3dae324dbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242007519 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.4242007519
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.302305765
Short name T414
Test name
Test status
Simulation time 495230578 ps
CPU time 0.89 seconds
Started Jun 27 07:12:15 PM PDT 24
Finished Jun 27 07:13:36 PM PDT 24
Peak memory 201632 kb
Host smart-5b1e6f05-7684-41ef-bdee-8fbef4c70bb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302305765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.302305765
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.2233722752
Short name T254
Test name
Test status
Simulation time 543241781923 ps
CPU time 485.45 seconds
Started Jun 27 07:12:16 PM PDT 24
Finished Jun 27 07:21:41 PM PDT 24
Peak memory 201844 kb
Host smart-86c8bef0-f291-4088-9037-26bdcb635342
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233722752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.2233722752
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.3949597123
Short name T143
Test name
Test status
Simulation time 352232380212 ps
CPU time 206.88 seconds
Started Jun 27 07:12:15 PM PDT 24
Finished Jun 27 07:17:02 PM PDT 24
Peak memory 201956 kb
Host smart-020708ae-14be-4cab-9ef1-e689b376f265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949597123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3949597123
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1485749818
Short name T557
Test name
Test status
Simulation time 163413100035 ps
CPU time 30.04 seconds
Started Jun 27 07:12:15 PM PDT 24
Finished Jun 27 07:14:05 PM PDT 24
Peak memory 201836 kb
Host smart-7f910c34-767f-4f00-8ded-f20533e3b841
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485749818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1485749818
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3715241175
Short name T352
Test name
Test status
Simulation time 166925753600 ps
CPU time 257.4 seconds
Started Jun 27 07:12:01 PM PDT 24
Finished Jun 27 07:17:26 PM PDT 24
Peak memory 201884 kb
Host smart-4dc35124-b560-4397-aa6b-b7608f95ce31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715241175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3715241175
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.3128524980
Short name T640
Test name
Test status
Simulation time 495892743460 ps
CPU time 1151.11 seconds
Started Jun 27 07:12:01 PM PDT 24
Finished Jun 27 07:32:19 PM PDT 24
Peak memory 201872 kb
Host smart-17669311-d697-461e-9b9f-7c8d4d2a2ece
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128524980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.3128524980
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.2852391519
Short name T302
Test name
Test status
Simulation time 609224327480 ps
CPU time 1239.08 seconds
Started Jun 27 07:12:18 PM PDT 24
Finished Jun 27 07:34:17 PM PDT 24
Peak memory 201716 kb
Host smart-317d9e65-04e6-460e-a946-48380351a178
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852391519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.2852391519
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.2656601769
Short name T714
Test name
Test status
Simulation time 193324592566 ps
CPU time 180.3 seconds
Started Jun 27 07:12:17 PM PDT 24
Finished Jun 27 07:16:37 PM PDT 24
Peak memory 201768 kb
Host smart-dd3ede31-11ed-4a8d-9f53-c70672d68d87
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656601769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.2656601769
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.3351460399
Short name T657
Test name
Test status
Simulation time 116199642894 ps
CPU time 397.69 seconds
Started Jun 27 07:12:16 PM PDT 24
Finished Jun 27 07:20:13 PM PDT 24
Peak memory 202224 kb
Host smart-0f9bceab-a44c-465f-a1bf-6b0089ea3825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351460399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.3351460399
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.3453849849
Short name T568
Test name
Test status
Simulation time 26250591956 ps
CPU time 57.63 seconds
Started Jun 27 07:12:16 PM PDT 24
Finished Jun 27 07:14:33 PM PDT 24
Peak memory 201624 kb
Host smart-a37922e3-aba1-4693-b406-1ecdfa066ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453849849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3453849849
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.665364209
Short name T460
Test name
Test status
Simulation time 4752047977 ps
CPU time 3.39 seconds
Started Jun 27 07:12:16 PM PDT 24
Finished Jun 27 07:13:39 PM PDT 24
Peak memory 201652 kb
Host smart-f07c4db2-85f6-4775-9b25-c799d81b3dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665364209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.665364209
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.3058493233
Short name T95
Test name
Test status
Simulation time 6026940613 ps
CPU time 15.23 seconds
Started Jun 27 07:12:00 PM PDT 24
Finished Jun 27 07:13:22 PM PDT 24
Peak memory 201624 kb
Host smart-4864c4fc-e98e-488f-a605-26eb2d02fc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058493233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3058493233
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1415622428
Short name T322
Test name
Test status
Simulation time 283580340716 ps
CPU time 169.86 seconds
Started Jun 27 07:12:16 PM PDT 24
Finished Jun 27 07:16:25 PM PDT 24
Peak memory 218628 kb
Host smart-ebc49d54-12ad-408a-8ec8-b4c2bb4980d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415622428 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1415622428
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.2988235619
Short name T691
Test name
Test status
Simulation time 385558362 ps
CPU time 1.37 seconds
Started Jun 27 07:12:31 PM PDT 24
Finished Jun 27 07:14:13 PM PDT 24
Peak memory 201572 kb
Host smart-392a7675-2317-4ea9-8dd3-6096e2291cd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988235619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.2988235619
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.3980438038
Short name T775
Test name
Test status
Simulation time 361374549566 ps
CPU time 176.5 seconds
Started Jun 27 07:12:18 PM PDT 24
Finished Jun 27 07:16:39 PM PDT 24
Peak memory 201812 kb
Host smart-f1c1f81b-c47e-4a13-a251-6a1d687a94a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980438038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.3980438038
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.214009186
Short name T553
Test name
Test status
Simulation time 492964393785 ps
CPU time 1041.55 seconds
Started Jun 27 07:12:18 PM PDT 24
Finished Jun 27 07:30:58 PM PDT 24
Peak memory 201872 kb
Host smart-8ada8261-afd3-48b3-a074-bb97b3b27d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214009186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.214009186
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3982247363
Short name T632
Test name
Test status
Simulation time 336013007057 ps
CPU time 703.33 seconds
Started Jun 27 07:12:18 PM PDT 24
Finished Jun 27 07:25:26 PM PDT 24
Peak memory 201788 kb
Host smart-d8f557a1-4dee-4889-a78a-840b9a2cfff6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982247363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.3982247363
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.3766646583
Short name T83
Test name
Test status
Simulation time 168444261766 ps
CPU time 102.2 seconds
Started Jun 27 07:12:15 PM PDT 24
Finished Jun 27 07:15:17 PM PDT 24
Peak memory 201884 kb
Host smart-74a4d72d-ea5c-45b3-9356-9a7477b00d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766646583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.3766646583
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.1770483864
Short name T456
Test name
Test status
Simulation time 488619858820 ps
CPU time 1102.76 seconds
Started Jun 27 07:12:16 PM PDT 24
Finished Jun 27 07:31:58 PM PDT 24
Peak memory 201828 kb
Host smart-41d23b81-72c9-42d7-8432-8f72c5135874
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770483864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.1770483864
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2251034654
Short name T350
Test name
Test status
Simulation time 172760748999 ps
CPU time 412.17 seconds
Started Jun 27 07:12:17 PM PDT 24
Finished Jun 27 07:20:29 PM PDT 24
Peak memory 201840 kb
Host smart-f9056c54-aa09-491b-97a1-00231279e8e2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251034654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2251034654
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3093626058
Short name T735
Test name
Test status
Simulation time 611432401006 ps
CPU time 599.34 seconds
Started Jun 27 07:12:18 PM PDT 24
Finished Jun 27 07:23:42 PM PDT 24
Peak memory 201840 kb
Host smart-c1c95597-1a58-4778-8391-411e4506b326
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093626058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3093626058
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.2059847612
Short name T678
Test name
Test status
Simulation time 107352748522 ps
CPU time 381.55 seconds
Started Jun 27 07:12:30 PM PDT 24
Finished Jun 27 07:20:30 PM PDT 24
Peak memory 202244 kb
Host smart-37dae258-b986-4b82-b990-4bbb2a7e0e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059847612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2059847612
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.2884373723
Short name T716
Test name
Test status
Simulation time 29548850570 ps
CPU time 17.31 seconds
Started Jun 27 07:12:15 PM PDT 24
Finished Jun 27 07:13:52 PM PDT 24
Peak memory 201680 kb
Host smart-60ac3d9f-67b7-4e50-826f-209a8ecc314c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884373723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.2884373723
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2088291058
Short name T399
Test name
Test status
Simulation time 3455783982 ps
CPU time 1.67 seconds
Started Jun 27 07:12:18 PM PDT 24
Finished Jun 27 07:13:44 PM PDT 24
Peak memory 201684 kb
Host smart-7471decb-319b-4a07-8406-78476c489cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088291058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2088291058
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.820465332
Short name T27
Test name
Test status
Simulation time 6036007380 ps
CPU time 7.62 seconds
Started Jun 27 07:12:19 PM PDT 24
Finished Jun 27 07:13:51 PM PDT 24
Peak memory 201676 kb
Host smart-bdf61f95-27ce-4b59-9fe8-5706b3cf83cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820465332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.820465332
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.1969336292
Short name T42
Test name
Test status
Simulation time 353636482961 ps
CPU time 837.59 seconds
Started Jun 27 07:12:33 PM PDT 24
Finished Jun 27 07:28:12 PM PDT 24
Peak memory 201868 kb
Host smart-27226635-c231-40a2-bf71-382dea561165
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969336292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.1969336292
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.3681621739
Short name T731
Test name
Test status
Simulation time 116672273180 ps
CPU time 104.98 seconds
Started Jun 27 07:12:31 PM PDT 24
Finished Jun 27 07:15:56 PM PDT 24
Peak memory 210108 kb
Host smart-76e80e7a-9079-420f-a9a2-ea49b6bdd58a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681621739 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.3681621739
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.685608874
Short name T465
Test name
Test status
Simulation time 396223408 ps
CPU time 1.55 seconds
Started Jun 27 07:12:54 PM PDT 24
Finished Jun 27 07:14:58 PM PDT 24
Peak memory 201604 kb
Host smart-9c109ddf-10dc-4ffc-95d9-42769264aada
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685608874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.685608874
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.4074272889
Short name T299
Test name
Test status
Simulation time 519220624230 ps
CPU time 1159.75 seconds
Started Jun 27 07:12:35 PM PDT 24
Finished Jun 27 07:33:34 PM PDT 24
Peak memory 201728 kb
Host smart-c527f312-d6fd-4960-aefc-c9f9c45a43a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074272889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.4074272889
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.1551963079
Short name T666
Test name
Test status
Simulation time 482152604171 ps
CPU time 1143.92 seconds
Started Jun 27 07:12:34 PM PDT 24
Finished Jun 27 07:33:27 PM PDT 24
Peak memory 201860 kb
Host smart-bc8eeb8b-dbff-4b90-95f3-48f6387e8a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551963079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1551963079
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.2066490072
Short name T432
Test name
Test status
Simulation time 159627224376 ps
CPU time 166.29 seconds
Started Jun 27 07:12:32 PM PDT 24
Finished Jun 27 07:17:00 PM PDT 24
Peak memory 201764 kb
Host smart-7954de98-ac3c-40d9-843b-b9440f52ae9b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066490072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.2066490072
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3383162158
Short name T342
Test name
Test status
Simulation time 492568565235 ps
CPU time 578.72 seconds
Started Jun 27 07:12:33 PM PDT 24
Finished Jun 27 07:23:53 PM PDT 24
Peak memory 201928 kb
Host smart-ece72c51-2e91-4e11-8d89-b22e9319994a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383162158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3383162158
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2733255440
Short name T785
Test name
Test status
Simulation time 160835786406 ps
CPU time 382.73 seconds
Started Jun 27 07:12:32 PM PDT 24
Finished Jun 27 07:20:35 PM PDT 24
Peak memory 201864 kb
Host smart-55d74a6b-07ef-47cf-a52b-920773496d11
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733255440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2733255440
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.139860539
Short name T683
Test name
Test status
Simulation time 170566250383 ps
CPU time 92.91 seconds
Started Jun 27 07:12:32 PM PDT 24
Finished Jun 27 07:15:46 PM PDT 24
Peak memory 201872 kb
Host smart-5524613a-8f8f-476c-a886-a047e0b3952c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139860539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.139860539
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3362098851
Short name T626
Test name
Test status
Simulation time 595673689436 ps
CPU time 1266.96 seconds
Started Jun 27 07:12:31 PM PDT 24
Finished Jun 27 07:35:18 PM PDT 24
Peak memory 201848 kb
Host smart-bcf774a7-c595-4801-8138-745beb0781fe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362098851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.3362098851
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.4029449210
Short name T217
Test name
Test status
Simulation time 143471095681 ps
CPU time 489.26 seconds
Started Jun 27 07:12:35 PM PDT 24
Finished Jun 27 07:22:31 PM PDT 24
Peak memory 202256 kb
Host smart-e85b5211-5abc-47bc-949e-cbe69a59a7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029449210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.4029449210
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.3699510559
Short name T746
Test name
Test status
Simulation time 20933583675 ps
CPU time 46.68 seconds
Started Jun 27 07:13:05 PM PDT 24
Finished Jun 27 07:15:41 PM PDT 24
Peak memory 201680 kb
Host smart-002f9a43-5f60-4efa-b85e-cc3a8ba4f933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699510559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.3699510559
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.333921069
Short name T387
Test name
Test status
Simulation time 3269546601 ps
CPU time 5.04 seconds
Started Jun 27 07:12:37 PM PDT 24
Finished Jun 27 07:14:29 PM PDT 24
Peak memory 201672 kb
Host smart-14cc5892-619e-4e4d-9df2-6182e1dd3ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333921069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.333921069
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3695983496
Short name T385
Test name
Test status
Simulation time 5997254124 ps
CPU time 2.04 seconds
Started Jun 27 07:12:32 PM PDT 24
Finished Jun 27 07:14:15 PM PDT 24
Peak memory 201680 kb
Host smart-cc82ff32-17d8-407a-bf44-78b93ef6f82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695983496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3695983496
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1551856700
Short name T23
Test name
Test status
Simulation time 148879202242 ps
CPU time 84.73 seconds
Started Jun 27 07:12:32 PM PDT 24
Finished Jun 27 07:15:37 PM PDT 24
Peak memory 210140 kb
Host smart-b893fd72-522f-4152-b743-50fea16f3601
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551856700 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1551856700
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1797966884
Short name T593
Test name
Test status
Simulation time 352489036 ps
CPU time 1.45 seconds
Started Jun 27 07:13:19 PM PDT 24
Finished Jun 27 07:15:06 PM PDT 24
Peak memory 201572 kb
Host smart-2f7afc37-1c84-4bd9-a18e-6e229f660d72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797966884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1797966884
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.1936576504
Short name T211
Test name
Test status
Simulation time 322269393505 ps
CPU time 187.72 seconds
Started Jun 27 07:12:54 PM PDT 24
Finished Jun 27 07:18:04 PM PDT 24
Peak memory 201848 kb
Host smart-37a36fdf-466f-4265-8ade-74ff9681f12c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936576504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.1936576504
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.1130770425
Short name T278
Test name
Test status
Simulation time 489912361093 ps
CPU time 1126.93 seconds
Started Jun 27 07:13:13 PM PDT 24
Finished Jun 27 07:34:07 PM PDT 24
Peak memory 201912 kb
Host smart-e8b93497-1183-4f2b-a6e3-0a4893123ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130770425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.1130770425
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1071221336
Short name T210
Test name
Test status
Simulation time 498353026053 ps
CPU time 248.31 seconds
Started Jun 27 07:12:53 PM PDT 24
Finished Jun 27 07:19:28 PM PDT 24
Peak memory 201896 kb
Host smart-49ada93c-539d-46d1-a2f9-bd63ce30235a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071221336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1071221336
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.1494717558
Short name T562
Test name
Test status
Simulation time 169617235200 ps
CPU time 97.03 seconds
Started Jun 27 07:12:54 PM PDT 24
Finished Jun 27 07:16:33 PM PDT 24
Peak memory 201860 kb
Host smart-9d24ae38-d394-42b6-9679-9ad25f278390
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494717558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.1494717558
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2589721349
Short name T288
Test name
Test status
Simulation time 163376103002 ps
CPU time 177.25 seconds
Started Jun 27 07:12:53 PM PDT 24
Finished Jun 27 07:18:17 PM PDT 24
Peak memory 201900 kb
Host smart-f3263f9d-e013-469f-83ce-f74846171165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589721349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2589721349
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1862739985
Short name T482
Test name
Test status
Simulation time 327082653174 ps
CPU time 335.38 seconds
Started Jun 27 07:12:53 PM PDT 24
Finished Jun 27 07:20:55 PM PDT 24
Peak memory 201880 kb
Host smart-82f43933-4e80-4979-aab9-f2d41bf22bd3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862739985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1862739985
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1043239747
Short name T446
Test name
Test status
Simulation time 357184373080 ps
CPU time 212.77 seconds
Started Jun 27 07:12:53 PM PDT 24
Finished Jun 27 07:18:53 PM PDT 24
Peak memory 201880 kb
Host smart-2148822e-1698-48a0-826a-3e593d4a0cca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043239747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1043239747
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.4238437057
Short name T442
Test name
Test status
Simulation time 388898907775 ps
CPU time 178.01 seconds
Started Jun 27 07:12:56 PM PDT 24
Finished Jun 27 07:18:15 PM PDT 24
Peak memory 201844 kb
Host smart-083382f6-7cba-4128-9cb8-512153d19a13
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238437057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.4238437057
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.252557365
Short name T784
Test name
Test status
Simulation time 85497509951 ps
CPU time 464.71 seconds
Started Jun 27 07:13:13 PM PDT 24
Finished Jun 27 07:23:05 PM PDT 24
Peak memory 202256 kb
Host smart-4a6c4dc6-1660-4624-b73c-1eafc8faa35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252557365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.252557365
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3384331273
Short name T605
Test name
Test status
Simulation time 44873892237 ps
CPU time 105.87 seconds
Started Jun 27 07:13:16 PM PDT 24
Finished Jun 27 07:16:50 PM PDT 24
Peak memory 201676 kb
Host smart-c58589f4-bbc3-4765-97e2-fe3160bfa8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384331273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3384331273
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.3245650485
Short name T752
Test name
Test status
Simulation time 3192743724 ps
CPU time 4.43 seconds
Started Jun 27 07:13:13 PM PDT 24
Finished Jun 27 07:15:08 PM PDT 24
Peak memory 201708 kb
Host smart-994fb080-7fbe-4911-8b02-ab6234734011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245650485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3245650485
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.496279290
Short name T198
Test name
Test status
Simulation time 5921111605 ps
CPU time 4.68 seconds
Started Jun 27 07:12:53 PM PDT 24
Finished Jun 27 07:15:24 PM PDT 24
Peak memory 201684 kb
Host smart-6d1c6c26-6a7d-4882-87bd-47bbb1a27741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496279290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.496279290
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.3959455959
Short name T798
Test name
Test status
Simulation time 442170152777 ps
CPU time 714.34 seconds
Started Jun 27 07:13:19 PM PDT 24
Finished Jun 27 07:26:59 PM PDT 24
Peak memory 210436 kb
Host smart-d5a5b713-270c-485f-a594-8e5ed7c5ccd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959455959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.3959455959
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.902642008
Short name T750
Test name
Test status
Simulation time 392666959 ps
CPU time 1.36 seconds
Started Jun 27 07:13:14 PM PDT 24
Finished Jun 27 07:15:05 PM PDT 24
Peak memory 201612 kb
Host smart-49c62007-a27f-4873-93fd-729b26fa1877
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902642008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.902642008
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.2247896519
Short name T290
Test name
Test status
Simulation time 501437912999 ps
CPU time 1111.3 seconds
Started Jun 27 07:13:13 PM PDT 24
Finished Jun 27 07:33:51 PM PDT 24
Peak memory 201796 kb
Host smart-ff41b41f-ed85-4528-bb3c-40ef1ce4598e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247896519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.2247896519
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.49447324
Short name T230
Test name
Test status
Simulation time 166343574042 ps
CPU time 357.53 seconds
Started Jun 27 07:13:12 PM PDT 24
Finished Jun 27 07:21:17 PM PDT 24
Peak memory 201956 kb
Host smart-72ceae44-0e92-4757-b781-e2a8b50bbf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49447324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.49447324
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.525027393
Short name T672
Test name
Test status
Simulation time 167603353151 ps
CPU time 372.8 seconds
Started Jun 27 07:13:15 PM PDT 24
Finished Jun 27 07:21:16 PM PDT 24
Peak memory 201804 kb
Host smart-68e9f64a-dfa1-4fb0-af18-9d4b7b340c66
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=525027393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrup
t_fixed.525027393
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.1812448004
Short name T474
Test name
Test status
Simulation time 323652256178 ps
CPU time 198.31 seconds
Started Jun 27 07:13:14 PM PDT 24
Finished Jun 27 07:18:38 PM PDT 24
Peak memory 201808 kb
Host smart-e7544ab2-446e-4077-b708-cb6f24402ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812448004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.1812448004
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.4033524649
Short name T533
Test name
Test status
Simulation time 326850118364 ps
CPU time 369.65 seconds
Started Jun 27 07:13:30 PM PDT 24
Finished Jun 27 07:21:30 PM PDT 24
Peak memory 201852 kb
Host smart-f8a70445-e4af-43f2-8f89-f7fac8039a17
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033524649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.4033524649
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1142240730
Short name T696
Test name
Test status
Simulation time 429364970537 ps
CPU time 229.45 seconds
Started Jun 27 07:13:13 PM PDT 24
Finished Jun 27 07:19:09 PM PDT 24
Peak memory 201876 kb
Host smart-d379d764-13d7-4ab6-8348-ad23f3cef203
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142240730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1142240730
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3083969541
Short name T375
Test name
Test status
Simulation time 200938084371 ps
CPU time 231.42 seconds
Started Jun 27 07:13:13 PM PDT 24
Finished Jun 27 07:18:55 PM PDT 24
Peak memory 201796 kb
Host smart-72f6fb4c-a4a1-46e0-9de8-6fa549eb2126
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083969541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.3083969541
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.4158313779
Short name T711
Test name
Test status
Simulation time 141910216315 ps
CPU time 684.55 seconds
Started Jun 27 07:13:29 PM PDT 24
Finished Jun 27 07:26:45 PM PDT 24
Peak memory 202200 kb
Host smart-d40e91e5-cd77-4c4b-bf29-1a555ab0c605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158313779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.4158313779
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.1826145642
Short name T694
Test name
Test status
Simulation time 25056212188 ps
CPU time 59.86 seconds
Started Jun 27 07:13:19 PM PDT 24
Finished Jun 27 07:16:05 PM PDT 24
Peak memory 201676 kb
Host smart-d01ed45a-1a7a-4dda-b514-4f67a572b7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826145642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.1826145642
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.321089281
Short name T380
Test name
Test status
Simulation time 4508037949 ps
CPU time 3.34 seconds
Started Jun 27 07:13:14 PM PDT 24
Finished Jun 27 07:15:07 PM PDT 24
Peak memory 201676 kb
Host smart-33e8cb08-5697-48d1-bab3-e4867dc1e378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321089281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.321089281
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.1763184861
Short name T475
Test name
Test status
Simulation time 5780608917 ps
CPU time 13.01 seconds
Started Jun 27 07:13:19 PM PDT 24
Finished Jun 27 07:15:18 PM PDT 24
Peak memory 201672 kb
Host smart-6b042143-c8ce-438c-9e92-15820febaf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763184861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1763184861
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.2073323922
Short name T685
Test name
Test status
Simulation time 176615815651 ps
CPU time 397.25 seconds
Started Jun 27 07:13:15 PM PDT 24
Finished Jun 27 07:21:40 PM PDT 24
Peak memory 201928 kb
Host smart-c6155cc3-ac20-4b90-ad42-a9b9fe617a5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073323922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.2073323922
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3534404961
Short name T633
Test name
Test status
Simulation time 15939596051 ps
CPU time 39.73 seconds
Started Jun 27 07:13:19 PM PDT 24
Finished Jun 27 07:15:44 PM PDT 24
Peak memory 210500 kb
Host smart-24550510-8db6-498e-a700-410b22b1cbfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534404961 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.3534404961
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.4047238695
Short name T102
Test name
Test status
Simulation time 533238093 ps
CPU time 0.99 seconds
Started Jun 27 07:13:32 PM PDT 24
Finished Jun 27 07:15:26 PM PDT 24
Peak memory 201840 kb
Host smart-a9578045-151c-421a-b2cf-6cf4beb4ff4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047238695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.4047238695
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3163003527
Short name T238
Test name
Test status
Simulation time 318380259216 ps
CPU time 312.46 seconds
Started Jun 27 07:13:31 PM PDT 24
Finished Jun 27 07:20:33 PM PDT 24
Peak memory 201872 kb
Host smart-9ea92fec-cdfc-45d3-826b-7ab89680e779
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163003527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3163003527
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.377388999
Short name T787
Test name
Test status
Simulation time 498553697251 ps
CPU time 84.88 seconds
Started Jun 27 07:13:28 PM PDT 24
Finished Jun 27 07:16:45 PM PDT 24
Peak memory 201856 kb
Host smart-76d4a969-af41-4b4c-9d21-881088c0ade9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=377388999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrup
t_fixed.377388999
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.3931616065
Short name T312
Test name
Test status
Simulation time 490242155867 ps
CPU time 287.81 seconds
Started Jun 27 07:13:15 PM PDT 24
Finished Jun 27 07:19:51 PM PDT 24
Peak memory 201884 kb
Host smart-798bfd8f-c6f8-4166-b57d-9999ac23bd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931616065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.3931616065
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.3714997347
Short name T773
Test name
Test status
Simulation time 327305642023 ps
CPU time 184.17 seconds
Started Jun 27 07:13:31 PM PDT 24
Finished Jun 27 07:18:33 PM PDT 24
Peak memory 201740 kb
Host smart-74cb6e16-824c-4448-9e20-355567f47309
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714997347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.3714997347
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.3179942773
Short name T294
Test name
Test status
Simulation time 564152497607 ps
CPU time 1310.33 seconds
Started Jun 27 07:13:30 PM PDT 24
Finished Jun 27 07:37:19 PM PDT 24
Peak memory 201952 kb
Host smart-4d620fb8-7205-4d6a-846e-fbe6f86100fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179942773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.3179942773
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.1715757700
Short name T698
Test name
Test status
Simulation time 399208111564 ps
CPU time 489.41 seconds
Started Jun 27 07:13:30 PM PDT 24
Finished Jun 27 07:23:38 PM PDT 24
Peak memory 201840 kb
Host smart-e0e46817-3499-4c78-8c9a-b457e0f2ca65
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715757700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.1715757700
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.4233917035
Short name T554
Test name
Test status
Simulation time 76888014172 ps
CPU time 268.74 seconds
Started Jun 27 07:13:32 PM PDT 24
Finished Jun 27 07:19:54 PM PDT 24
Peak memory 202204 kb
Host smart-05e92bc5-c2bc-45c4-8d86-3cca8fbfe95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233917035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.4233917035
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.591368550
Short name T391
Test name
Test status
Simulation time 25822093593 ps
CPU time 15.27 seconds
Started Jun 27 07:13:29 PM PDT 24
Finished Jun 27 07:15:35 PM PDT 24
Peak memory 201652 kb
Host smart-88fe5ea9-de07-4275-bd53-9e0a9e71c884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591368550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.591368550
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1204163140
Short name T772
Test name
Test status
Simulation time 4146388444 ps
CPU time 9.82 seconds
Started Jun 27 07:13:30 PM PDT 24
Finished Jun 27 07:15:39 PM PDT 24
Peak memory 201676 kb
Host smart-9be6bccb-7756-4a0f-9a2f-df5f2534d334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204163140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1204163140
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1669964182
Short name T386
Test name
Test status
Simulation time 5789433499 ps
CPU time 13.86 seconds
Started Jun 27 07:13:12 PM PDT 24
Finished Jun 27 07:15:34 PM PDT 24
Peak memory 201668 kb
Host smart-3767bb5b-cbf0-4b40-a9fb-23425b5fcc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669964182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1669964182
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.686231993
Short name T325
Test name
Test status
Simulation time 370448857123 ps
CPU time 448.17 seconds
Started Jun 27 07:13:27 PM PDT 24
Finished Jun 27 07:22:48 PM PDT 24
Peak memory 201776 kb
Host smart-ed0e82ef-9a25-450c-9ed9-2a304998bb37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686231993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
686231993
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1577949869
Short name T32
Test name
Test status
Simulation time 210039236246 ps
CPU time 94.05 seconds
Started Jun 27 07:13:29 PM PDT 24
Finished Jun 27 07:16:54 PM PDT 24
Peak memory 201996 kb
Host smart-30ac1690-b0f4-4032-ada3-75c6d7999432
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577949869 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1577949869
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3574109845
Short name T601
Test name
Test status
Simulation time 292805965 ps
CPU time 0.78 seconds
Started Jun 27 07:13:45 PM PDT 24
Finished Jun 27 07:15:34 PM PDT 24
Peak memory 201624 kb
Host smart-71207969-1e5b-46ea-a08c-3e727396e735
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574109845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3574109845
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.4036964636
Short name T265
Test name
Test status
Simulation time 165165852308 ps
CPU time 14.36 seconds
Started Jun 27 07:13:32 PM PDT 24
Finished Jun 27 07:15:43 PM PDT 24
Peak memory 201856 kb
Host smart-688ceda6-0bda-4042-90a3-b78bd8ae1e6a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036964636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.4036964636
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.1907242910
Short name T186
Test name
Test status
Simulation time 162094829676 ps
CPU time 180.05 seconds
Started Jun 27 07:13:30 PM PDT 24
Finished Jun 27 07:18:21 PM PDT 24
Peak memory 201812 kb
Host smart-e08e134c-0131-4046-aae4-532161b11224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907242910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.1907242910
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3419126910
Short name T508
Test name
Test status
Simulation time 499089797489 ps
CPU time 1064.15 seconds
Started Jun 27 07:13:30 PM PDT 24
Finished Jun 27 07:33:05 PM PDT 24
Peak memory 201924 kb
Host smart-fa103e86-0eef-47e7-bfda-834a210480f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419126910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3419126910
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1615145005
Short name T586
Test name
Test status
Simulation time 485961353273 ps
CPU time 115.55 seconds
Started Jun 27 07:13:31 PM PDT 24
Finished Jun 27 07:17:25 PM PDT 24
Peak memory 201812 kb
Host smart-a09390c8-893a-4337-bc29-fe54d962fcf3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615145005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1615145005
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.619074420
Short name T237
Test name
Test status
Simulation time 321610281362 ps
CPU time 63.38 seconds
Started Jun 27 07:13:32 PM PDT 24
Finished Jun 27 07:16:35 PM PDT 24
Peak memory 201896 kb
Host smart-de3f2257-f299-4327-810c-ec199fb70aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619074420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.619074420
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.128497178
Short name T630
Test name
Test status
Simulation time 331294919480 ps
CPU time 321.28 seconds
Started Jun 27 07:13:30 PM PDT 24
Finished Jun 27 07:20:42 PM PDT 24
Peak memory 201868 kb
Host smart-796d0787-ad06-4ffb-a601-7f6143e3506b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=128497178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixe
d.128497178
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.119847530
Short name T268
Test name
Test status
Simulation time 527807446590 ps
CPU time 556.38 seconds
Started Jun 27 07:13:30 PM PDT 24
Finished Jun 27 07:24:45 PM PDT 24
Peak memory 201944 kb
Host smart-9dc6d5a8-e517-4f81-b317-4e0560dbbe8b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119847530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_
wakeup.119847530
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1591237617
Short name T770
Test name
Test status
Simulation time 190498853096 ps
CPU time 42.73 seconds
Started Jun 27 07:13:31 PM PDT 24
Finished Jun 27 07:16:12 PM PDT 24
Peak memory 201836 kb
Host smart-a1b648ca-b8a0-40c1-b449-8304fdf0fb8b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591237617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.1591237617
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3988780357
Short name T430
Test name
Test status
Simulation time 135857329136 ps
CPU time 536.21 seconds
Started Jun 27 07:13:31 PM PDT 24
Finished Jun 27 07:24:17 PM PDT 24
Peak memory 202172 kb
Host smart-cc32378a-0531-4271-b415-edf97da172eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988780357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3988780357
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.2867127874
Short name T463
Test name
Test status
Simulation time 43528564764 ps
CPU time 95.14 seconds
Started Jun 27 07:13:30 PM PDT 24
Finished Jun 27 07:17:04 PM PDT 24
Peak memory 201688 kb
Host smart-2f25fdd0-3ffe-4cf0-917e-29dad6031db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867127874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.2867127874
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.3466662462
Short name T400
Test name
Test status
Simulation time 5864643574 ps
CPU time 2.83 seconds
Started Jun 27 07:13:30 PM PDT 24
Finished Jun 27 07:15:23 PM PDT 24
Peak memory 201616 kb
Host smart-a02bbde0-4859-42ce-a0bb-99587f9f5f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466662462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.3466662462
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.1719764361
Short name T454
Test name
Test status
Simulation time 5876731372 ps
CPU time 6.9 seconds
Started Jun 27 07:13:32 PM PDT 24
Finished Jun 27 07:15:32 PM PDT 24
Peak memory 201664 kb
Host smart-b1ace621-96a0-4da6-b04b-606deef30ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719764361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.1719764361
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.291695560
Short name T218
Test name
Test status
Simulation time 527732813912 ps
CPU time 1423.98 seconds
Started Jun 27 07:13:46 PM PDT 24
Finished Jun 27 07:39:18 PM PDT 24
Peak memory 210344 kb
Host smart-6c3791ac-c799-483f-9c77-6013d7f3d0e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291695560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.
291695560
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3432885304
Short name T115
Test name
Test status
Simulation time 4578053474 ps
CPU time 12.77 seconds
Started Jun 27 07:13:31 PM PDT 24
Finished Jun 27 07:15:42 PM PDT 24
Peak memory 210420 kb
Host smart-5ceb9189-996f-4276-8a44-e085b05f9f66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432885304 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3432885304
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.3434050794
Short name T703
Test name
Test status
Simulation time 551811946 ps
CPU time 0.92 seconds
Started Jun 27 07:06:43 PM PDT 24
Finished Jun 27 07:06:53 PM PDT 24
Peak memory 201544 kb
Host smart-7a3d76f4-a375-4919-93fa-1145985782de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434050794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.3434050794
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.3644187128
Short name T181
Test name
Test status
Simulation time 533743447620 ps
CPU time 149.17 seconds
Started Jun 27 07:06:39 PM PDT 24
Finished Jun 27 07:09:16 PM PDT 24
Peak memory 201868 kb
Host smart-21a98d1b-d049-4fc7-b7ee-c06ef68bdfa5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644187128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.3644187128
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.264280896
Short name T344
Test name
Test status
Simulation time 544832276139 ps
CPU time 334.67 seconds
Started Jun 27 07:06:40 PM PDT 24
Finished Jun 27 07:12:22 PM PDT 24
Peak memory 201904 kb
Host smart-9fb6987d-77cf-44e9-9eeb-334d05c204b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264280896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.264280896
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1721451602
Short name T411
Test name
Test status
Simulation time 162576614050 ps
CPU time 358.93 seconds
Started Jun 27 07:06:39 PM PDT 24
Finished Jun 27 07:12:46 PM PDT 24
Peak memory 201844 kb
Host smart-3fc3899d-a511-4a93-a07f-afbdea88d9ac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721451602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.1721451602
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3246439643
Short name T151
Test name
Test status
Simulation time 331931728164 ps
CPU time 732.94 seconds
Started Jun 27 07:06:40 PM PDT 24
Finished Jun 27 07:19:02 PM PDT 24
Peak memory 201964 kb
Host smart-24a066b6-d6e0-4f23-a9e1-b6227a733b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246439643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3246439643
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3062382471
Short name T656
Test name
Test status
Simulation time 333306408780 ps
CPU time 732.12 seconds
Started Jun 27 07:06:39 PM PDT 24
Finished Jun 27 07:19:00 PM PDT 24
Peak memory 201936 kb
Host smart-281e8d68-3491-40f2-a8f7-88e41361d8c7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062382471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3062382471
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1091184583
Short name T280
Test name
Test status
Simulation time 560947540010 ps
CPU time 719.53 seconds
Started Jun 27 07:06:40 PM PDT 24
Finished Jun 27 07:18:49 PM PDT 24
Peak memory 201924 kb
Host smart-7503787e-395c-4909-ac23-2d93d95a6ef0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091184583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1091184583
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2525357515
Short name T160
Test name
Test status
Simulation time 201430867562 ps
CPU time 209.47 seconds
Started Jun 27 07:06:40 PM PDT 24
Finished Jun 27 07:10:19 PM PDT 24
Peak memory 201872 kb
Host smart-85885ddb-dc1a-498f-bdc9-20adb07159a1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525357515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2525357515
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.2546082367
Short name T29
Test name
Test status
Simulation time 76729450433 ps
CPU time 264.37 seconds
Started Jun 27 07:06:42 PM PDT 24
Finished Jun 27 07:11:16 PM PDT 24
Peak memory 202200 kb
Host smart-bbdfc4ee-4d14-410e-be4c-344d61803b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546082367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2546082367
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1907682123
Short name T682
Test name
Test status
Simulation time 29801540464 ps
CPU time 16.76 seconds
Started Jun 27 07:06:41 PM PDT 24
Finished Jun 27 07:07:07 PM PDT 24
Peak memory 201684 kb
Host smart-22669645-89f1-49d0-a291-5099eec87a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907682123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1907682123
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3145454557
Short name T523
Test name
Test status
Simulation time 4604451309 ps
CPU time 3.51 seconds
Started Jun 27 07:06:40 PM PDT 24
Finished Jun 27 07:06:52 PM PDT 24
Peak memory 201696 kb
Host smart-88df0289-631a-49d2-a8c5-45054f044501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145454557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3145454557
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.1781575977
Short name T577
Test name
Test status
Simulation time 5913744128 ps
CPU time 7.9 seconds
Started Jun 27 07:06:39 PM PDT 24
Finished Jun 27 07:06:55 PM PDT 24
Peak memory 201648 kb
Host smart-ac47795a-ac79-4f19-becf-aa8eb6e586c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781575977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1781575977
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2775913274
Short name T429
Test name
Test status
Simulation time 34473954080 ps
CPU time 80.53 seconds
Started Jun 27 07:06:41 PM PDT 24
Finished Jun 27 07:08:11 PM PDT 24
Peak memory 201668 kb
Host smart-e0704734-5cd8-4688-a1b3-ee2fb4fc00ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775913274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2775913274
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2843135750
Short name T38
Test name
Test status
Simulation time 127517237996 ps
CPU time 342.96 seconds
Started Jun 27 07:06:42 PM PDT 24
Finished Jun 27 07:12:35 PM PDT 24
Peak memory 210516 kb
Host smart-d78e92fd-3402-4f7a-ba3f-1b86a4b86c19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843135750 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2843135750
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.4151221898
Short name T542
Test name
Test status
Simulation time 353355077 ps
CPU time 1.38 seconds
Started Jun 27 07:06:46 PM PDT 24
Finished Jun 27 07:06:55 PM PDT 24
Peak memory 201624 kb
Host smart-c8fedee9-f5a5-4daf-b030-f6f6d63ea41a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151221898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.4151221898
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2692313141
Short name T177
Test name
Test status
Simulation time 511153366478 ps
CPU time 207.4 seconds
Started Jun 27 07:06:52 PM PDT 24
Finished Jun 27 07:10:24 PM PDT 24
Peak memory 201864 kb
Host smart-7910b6ac-da3c-4a75-877a-6dc41ef31bdc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692313141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2692313141
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3926060807
Short name T308
Test name
Test status
Simulation time 181054730730 ps
CPU time 377.31 seconds
Started Jun 27 07:06:51 PM PDT 24
Finished Jun 27 07:13:14 PM PDT 24
Peak memory 201968 kb
Host smart-d0592849-46e7-4203-8c68-d4cc163cf9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926060807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3926060807
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.870909270
Short name T149
Test name
Test status
Simulation time 167686819571 ps
CPU time 109.02 seconds
Started Jun 27 07:06:43 PM PDT 24
Finished Jun 27 07:08:41 PM PDT 24
Peak memory 201776 kb
Host smart-3aeb393c-e49a-4ad5-9c8d-12465068fe06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870909270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.870909270
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3913232317
Short name T492
Test name
Test status
Simulation time 325379138404 ps
CPU time 657.95 seconds
Started Jun 27 07:06:42 PM PDT 24
Finished Jun 27 07:17:50 PM PDT 24
Peak memory 201900 kb
Host smart-fed624d9-b45e-43c7-82aa-0f745bec17b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913232317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3913232317
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3469215751
Short name T496
Test name
Test status
Simulation time 166765582955 ps
CPU time 200.84 seconds
Started Jun 27 07:06:43 PM PDT 24
Finished Jun 27 07:10:13 PM PDT 24
Peak memory 201936 kb
Host smart-0a4af898-7718-42a8-8f57-239a2b426732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469215751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3469215751
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3037431384
Short name T560
Test name
Test status
Simulation time 161146286277 ps
CPU time 346.27 seconds
Started Jun 27 07:06:43 PM PDT 24
Finished Jun 27 07:12:39 PM PDT 24
Peak memory 201860 kb
Host smart-0016f6be-b379-4efa-8e5a-72d36b67807a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037431384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3037431384
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.4098613562
Short name T269
Test name
Test status
Simulation time 362516993680 ps
CPU time 685.85 seconds
Started Jun 27 07:06:43 PM PDT 24
Finished Jun 27 07:18:19 PM PDT 24
Peak memory 201840 kb
Host smart-22957bb5-4524-4899-b208-4bb31416fa08
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098613562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.4098613562
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.734395653
Short name T613
Test name
Test status
Simulation time 409344861655 ps
CPU time 940.85 seconds
Started Jun 27 07:06:59 PM PDT 24
Finished Jun 27 07:22:43 PM PDT 24
Peak memory 201772 kb
Host smart-f5457707-c628-40f0-b7dc-2fc57edd4374
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734395653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.a
dc_ctrl_filters_wakeup_fixed.734395653
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.1514836632
Short name T405
Test name
Test status
Simulation time 130344111850 ps
CPU time 644.36 seconds
Started Jun 27 07:06:56 PM PDT 24
Finished Jun 27 07:17:43 PM PDT 24
Peak memory 202228 kb
Host smart-52d4ec22-634c-44e4-bc01-ecc5f8f8a21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514836632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.1514836632
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1173410534
Short name T10
Test name
Test status
Simulation time 38871542445 ps
CPU time 89.54 seconds
Started Jun 27 07:06:47 PM PDT 24
Finished Jun 27 07:08:24 PM PDT 24
Peak memory 201896 kb
Host smart-7cf5a10a-9e59-4a2d-ac48-6728d4d6b283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173410534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1173410534
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1963401755
Short name T631
Test name
Test status
Simulation time 5164103791 ps
CPU time 1.34 seconds
Started Jun 27 07:06:56 PM PDT 24
Finished Jun 27 07:07:01 PM PDT 24
Peak memory 201712 kb
Host smart-1e194a85-e780-4b03-bbd8-31dd273ab4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963401755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1963401755
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.3536546378
Short name T24
Test name
Test status
Simulation time 5985717811 ps
CPU time 14.47 seconds
Started Jun 27 07:06:42 PM PDT 24
Finished Jun 27 07:07:07 PM PDT 24
Peak memory 201664 kb
Host smart-572a1a7a-5e8d-4c52-aea2-6eeb5918367b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536546378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3536546378
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.2218755466
Short name T180
Test name
Test status
Simulation time 204217509407 ps
CPU time 94.12 seconds
Started Jun 27 07:06:59 PM PDT 24
Finished Jun 27 07:08:36 PM PDT 24
Peak memory 201844 kb
Host smart-9a80858c-24c5-4e44-a9a8-684cf7d08520
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218755466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
2218755466
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3798526360
Short name T484
Test name
Test status
Simulation time 65561980631 ps
CPU time 159.04 seconds
Started Jun 27 07:06:45 PM PDT 24
Finished Jun 27 07:09:33 PM PDT 24
Peak memory 210556 kb
Host smart-751d86ff-5d1b-430d-92b0-fc42c99201d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798526360 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3798526360
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.754028065
Short name T788
Test name
Test status
Simulation time 447409772 ps
CPU time 1.57 seconds
Started Jun 27 07:06:56 PM PDT 24
Finished Jun 27 07:07:01 PM PDT 24
Peak memory 201460 kb
Host smart-3de8cbb4-c710-4656-899e-2234af84c901
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754028065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.754028065
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.126744285
Short name T501
Test name
Test status
Simulation time 191911041114 ps
CPU time 401.53 seconds
Started Jun 27 07:06:46 PM PDT 24
Finished Jun 27 07:13:36 PM PDT 24
Peak memory 201780 kb
Host smart-affce5cd-526b-45a3-8bfc-f1268ca9d994
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126744285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gatin
g.126744285
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.3579500274
Short name T790
Test name
Test status
Simulation time 345820722301 ps
CPU time 420.98 seconds
Started Jun 27 07:06:46 PM PDT 24
Finished Jun 27 07:13:55 PM PDT 24
Peak memory 201876 kb
Host smart-0be18b2f-4b13-45c7-9a0a-82cfdd1254ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579500274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3579500274
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1076983087
Short name T679
Test name
Test status
Simulation time 169405754694 ps
CPU time 403 seconds
Started Jun 27 07:06:57 PM PDT 24
Finished Jun 27 07:13:43 PM PDT 24
Peak memory 201840 kb
Host smart-2b21d946-223a-4499-9d87-d7f26ff959e6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076983087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.1076983087
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.1809361214
Short name T534
Test name
Test status
Simulation time 160981072376 ps
CPU time 93.31 seconds
Started Jun 27 07:06:49 PM PDT 24
Finished Jun 27 07:08:29 PM PDT 24
Peak memory 201948 kb
Host smart-249a196b-5e37-4a31-8e38-5823d0985079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809361214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1809361214
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.1524306235
Short name T82
Test name
Test status
Simulation time 492073313112 ps
CPU time 591.12 seconds
Started Jun 27 07:06:48 PM PDT 24
Finished Jun 27 07:16:47 PM PDT 24
Peak memory 201868 kb
Host smart-b0100bdc-2254-47f7-953d-aa770f14b789
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524306235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.1524306235
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.3138432422
Short name T566
Test name
Test status
Simulation time 350074468400 ps
CPU time 210.44 seconds
Started Jun 27 07:06:56 PM PDT 24
Finished Jun 27 07:10:30 PM PDT 24
Peak memory 201880 kb
Host smart-7d31d5df-6243-4196-a0f4-1aa44a295075
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138432422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.3138432422
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.556313037
Short name T457
Test name
Test status
Simulation time 196027624631 ps
CPU time 419.95 seconds
Started Jun 27 07:06:46 PM PDT 24
Finished Jun 27 07:13:54 PM PDT 24
Peak memory 201860 kb
Host smart-246aa298-acfd-448e-8c44-c27ac90829be
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556313037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.a
dc_ctrl_filters_wakeup_fixed.556313037
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3984477066
Short name T227
Test name
Test status
Simulation time 110806738341 ps
CPU time 641.51 seconds
Started Jun 27 07:06:57 PM PDT 24
Finished Jun 27 07:17:42 PM PDT 24
Peak memory 202044 kb
Host smart-b9040fe9-7da7-4236-bf69-4b77bbce2dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984477066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3984477066
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.2531202020
Short name T753
Test name
Test status
Simulation time 33854660115 ps
CPU time 76.61 seconds
Started Jun 27 07:06:54 PM PDT 24
Finished Jun 27 07:08:15 PM PDT 24
Peak memory 201688 kb
Host smart-0c7a14a2-7fd2-49b6-8e49-5b4a02ca7869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531202020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2531202020
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.2309107195
Short name T366
Test name
Test status
Simulation time 5132299615 ps
CPU time 2.42 seconds
Started Jun 27 07:06:47 PM PDT 24
Finished Jun 27 07:06:57 PM PDT 24
Peak memory 201620 kb
Host smart-52de627e-ef7b-4bdc-9d29-f430269a3f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309107195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.2309107195
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.1918713236
Short name T552
Test name
Test status
Simulation time 5781802606 ps
CPU time 15.06 seconds
Started Jun 27 07:06:50 PM PDT 24
Finished Jun 27 07:07:11 PM PDT 24
Peak memory 201680 kb
Host smart-5d1d31ce-0fcc-400f-86a6-1e3528a71e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918713236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1918713236
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.3329454940
Short name T617
Test name
Test status
Simulation time 170596568968 ps
CPU time 99.68 seconds
Started Jun 27 07:06:49 PM PDT 24
Finished Jun 27 07:08:35 PM PDT 24
Peak memory 201876 kb
Host smart-94371eec-87d8-4bfa-872f-0b63ec429de0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329454940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
3329454940
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.4238606045
Short name T518
Test name
Test status
Simulation time 337693779 ps
CPU time 0.71 seconds
Started Jun 27 07:06:56 PM PDT 24
Finished Jun 27 07:07:00 PM PDT 24
Peak memory 201648 kb
Host smart-d4453177-99d1-4d99-9098-56650d76b994
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238606045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.4238606045
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1431912663
Short name T266
Test name
Test status
Simulation time 523914018974 ps
CPU time 346.87 seconds
Started Jun 27 07:06:52 PM PDT 24
Finished Jun 27 07:12:44 PM PDT 24
Peak memory 201864 kb
Host smart-a6fc1055-3493-4ef4-9b6f-754d733c37e6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431912663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1431912663
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.1305477383
Short name T628
Test name
Test status
Simulation time 183052848421 ps
CPU time 428.31 seconds
Started Jun 27 07:06:54 PM PDT 24
Finished Jun 27 07:14:07 PM PDT 24
Peak memory 201872 kb
Host smart-2c4d1848-a7c6-4638-9382-43bafdd56cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305477383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1305477383
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.3347997908
Short name T258
Test name
Test status
Simulation time 165140452822 ps
CPU time 29.7 seconds
Started Jun 27 07:06:49 PM PDT 24
Finished Jun 27 07:07:26 PM PDT 24
Peak memory 201932 kb
Host smart-531ee324-f35a-49a2-9e2b-d5c5111c98db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347997908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.3347997908
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.582138617
Short name T418
Test name
Test status
Simulation time 161701052039 ps
CPU time 116.01 seconds
Started Jun 27 07:06:46 PM PDT 24
Finished Jun 27 07:08:50 PM PDT 24
Peak memory 201836 kb
Host smart-4acbb479-22e6-4039-aed3-bdc5d32c90ad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=582138617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt
_fixed.582138617
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2961489838
Short name T11
Test name
Test status
Simulation time 162876943433 ps
CPU time 247.18 seconds
Started Jun 27 07:06:53 PM PDT 24
Finished Jun 27 07:11:05 PM PDT 24
Peak memory 201948 kb
Host smart-bc144f65-84f1-4fcc-b730-96b05e5ca4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961489838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2961489838
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2032515857
Short name T384
Test name
Test status
Simulation time 480376969785 ps
CPU time 1035.54 seconds
Started Jun 27 07:06:55 PM PDT 24
Finished Jun 27 07:24:14 PM PDT 24
Peak memory 201868 kb
Host smart-595e55ab-425a-4bc2-96d6-3b428aed0781
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032515857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2032515857
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.1946899205
Short name T170
Test name
Test status
Simulation time 172650228386 ps
CPU time 207.73 seconds
Started Jun 27 07:06:49 PM PDT 24
Finished Jun 27 07:10:23 PM PDT 24
Peak memory 201872 kb
Host smart-71ecacb8-be2a-47fd-95ef-c7cb6975dc55
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946899205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.1946899205
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3672441759
Short name T547
Test name
Test status
Simulation time 613421624891 ps
CPU time 1442.01 seconds
Started Jun 27 07:06:55 PM PDT 24
Finished Jun 27 07:31:01 PM PDT 24
Peak memory 201676 kb
Host smart-811d22fd-9c38-4bbf-aa19-e1e7d77b148f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672441759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3672441759
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.2008429883
Short name T708
Test name
Test status
Simulation time 24030491382 ps
CPU time 55.09 seconds
Started Jun 27 07:06:52 PM PDT 24
Finished Jun 27 07:07:52 PM PDT 24
Peak memory 201708 kb
Host smart-15139b99-fea2-4281-b127-13568877f048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008429883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.2008429883
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.1380409880
Short name T550
Test name
Test status
Simulation time 5333808310 ps
CPU time 13.12 seconds
Started Jun 27 07:06:55 PM PDT 24
Finished Jun 27 07:07:12 PM PDT 24
Peak memory 201484 kb
Host smart-76640536-5a6d-4370-8ea2-bb0f271851a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380409880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.1380409880
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.2257480342
Short name T406
Test name
Test status
Simulation time 5959056795 ps
CPU time 4.47 seconds
Started Jun 27 07:06:55 PM PDT 24
Finished Jun 27 07:07:03 PM PDT 24
Peak memory 201660 kb
Host smart-88c22388-12a2-4a34-a40a-439ae7604203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257480342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2257480342
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.3921552473
Short name T609
Test name
Test status
Simulation time 328187288529 ps
CPU time 185.22 seconds
Started Jun 27 07:06:56 PM PDT 24
Finished Jun 27 07:10:04 PM PDT 24
Peak memory 201928 kb
Host smart-df62dcc9-f133-46bb-bfab-df833fa08b9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921552473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
3921552473
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1357076676
Short name T116
Test name
Test status
Simulation time 120157004132 ps
CPU time 70.16 seconds
Started Jun 27 07:06:51 PM PDT 24
Finished Jun 27 07:08:07 PM PDT 24
Peak memory 202072 kb
Host smart-d4eb4132-6606-4853-b18b-5296a1794559
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357076676 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.1357076676
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3444049999
Short name T481
Test name
Test status
Simulation time 422797654 ps
CPU time 1.59 seconds
Started Jun 27 07:06:56 PM PDT 24
Finished Jun 27 07:07:01 PM PDT 24
Peak memory 201628 kb
Host smart-13f3608f-4923-44fb-bf31-ce22979d124c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444049999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3444049999
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.2472891776
Short name T655
Test name
Test status
Simulation time 170356960933 ps
CPU time 384.68 seconds
Started Jun 27 07:06:56 PM PDT 24
Finished Jun 27 07:13:24 PM PDT 24
Peak memory 201956 kb
Host smart-952f6944-a764-4d4b-bd62-f4563a938d5e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472891776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.2472891776
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3746761021
Short name T720
Test name
Test status
Simulation time 495559770548 ps
CPU time 562.45 seconds
Started Jun 27 07:06:56 PM PDT 24
Finished Jun 27 07:16:21 PM PDT 24
Peak memory 201832 kb
Host smart-828d9103-b2cb-4970-b45f-c12e0dd3f970
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746761021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.3746761021
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.1895456571
Short name T296
Test name
Test status
Simulation time 492093535007 ps
CPU time 1138.32 seconds
Started Jun 27 07:06:49 PM PDT 24
Finished Jun 27 07:25:54 PM PDT 24
Peak memory 201964 kb
Host smart-a4cd790e-2783-42ae-beba-cc68c312ed78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895456571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.1895456571
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.1477144948
Short name T781
Test name
Test status
Simulation time 172143452731 ps
CPU time 339.67 seconds
Started Jun 27 07:06:47 PM PDT 24
Finished Jun 27 07:12:35 PM PDT 24
Peak memory 201856 kb
Host smart-d4a2c464-c0f7-4819-8e76-593079473f77
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477144948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.1477144948
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.3504737558
Short name T398
Test name
Test status
Simulation time 398811563982 ps
CPU time 231.24 seconds
Started Jun 27 07:06:54 PM PDT 24
Finished Jun 27 07:10:49 PM PDT 24
Peak memory 201864 kb
Host smart-3dd545cc-3ed2-406c-9428-a5295cbf482f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504737558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.3504737558
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3866823077
Short name T743
Test name
Test status
Simulation time 110209004408 ps
CPU time 598.3 seconds
Started Jun 27 07:07:00 PM PDT 24
Finished Jun 27 07:17:01 PM PDT 24
Peak memory 202220 kb
Host smart-f70ffb43-7d3b-46b4-8d46-b60365905ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866823077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3866823077
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.4085578201
Short name T156
Test name
Test status
Simulation time 43056929780 ps
CPU time 50.63 seconds
Started Jun 27 07:06:57 PM PDT 24
Finished Jun 27 07:07:51 PM PDT 24
Peak memory 201680 kb
Host smart-1f7a4b23-17c0-400b-a927-be95d5ecb2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085578201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.4085578201
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.3767268735
Short name T574
Test name
Test status
Simulation time 4820990500 ps
CPU time 11.45 seconds
Started Jun 27 07:06:55 PM PDT 24
Finished Jun 27 07:07:10 PM PDT 24
Peak memory 201672 kb
Host smart-511b2cfd-0e38-40db-b85e-5ed44f103da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767268735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3767268735
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.107110843
Short name T6
Test name
Test status
Simulation time 5942743343 ps
CPU time 16.17 seconds
Started Jun 27 07:06:55 PM PDT 24
Finished Jun 27 07:07:15 PM PDT 24
Peak memory 201680 kb
Host smart-7fd3ada6-86e5-4614-9a84-9c13c5489083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107110843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.107110843
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2557699503
Short name T681
Test name
Test status
Simulation time 202968214577 ps
CPU time 81.83 seconds
Started Jun 27 07:06:49 PM PDT 24
Finished Jun 27 07:08:17 PM PDT 24
Peak memory 201924 kb
Host smart-c191b96a-41d8-493d-9d45-effa9ec40007
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557699503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2557699503
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2004123575
Short name T729
Test name
Test status
Simulation time 238923758849 ps
CPU time 438.23 seconds
Started Jun 27 07:06:56 PM PDT 24
Finished Jun 27 07:14:18 PM PDT 24
Peak memory 210508 kb
Host smart-346c51d5-6259-4da8-b8da-fdf39a704cc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004123575 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2004123575
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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