Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

---

Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7205	1			T3	62		T6	20		T9	77
testmodes[AdcCtrlTestmodeNormal]	5615	1			T2	3		T3	42		T4	3
testmodes[AdcCtrlTestmodeLowpower]	5973	1			T1	1		T3	33		T5	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3906	1			T3	37		T6	19		T9	38
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1810	1			T3	14		T9	21		T10	4
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1383	1			T3	11		T9	18		T11	5
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1811	1			T3	11		T9	19		T10	5
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2002	1			T2	2		T3	14		T4	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1461	1			T3	16		T9	21		T11	3
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1388	1			T3	13		T9	19		T11	4
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1446	1			T3	14		T7	1		T9	20
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2887	1			T3	6		T9	19		T11	3