Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26420

1

T1

17

T2

23

T3

176

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22957

1

T2

23

T3

162

T4

3

auto[ADC_CTRL_FILTER_COND_OUT]

3463

1

T1

17

T3

14

T9

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20884

1

T3

148

T6

20

T7

23

auto[1]

5536

1

T1

17

T2

23

T3

28

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22773

1

T1

9

T2

3

T3

155

auto[1]

3647

1

T1

8

T2

20

T3

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	42	1			T22	16		T231	26		-	-
values[0]	44	1			T9	1		T143	19		T232	1
values[1]	680	1			T22	21		T35	10		T84	13
values[2]	542	1			T11	5		T34	4		T55	21
values[3]	718	1			T42	7		T122	48		T76	13
values[4]	649	1			T3	42		T233	1		T83	40
values[5]	2687	1			T2	23		T4	3		T5	5
values[6]	633	1			T7	44		T26	20		T122	1
values[7]	608	1			T9	1		T27	1		T234	1
values[8]	772	1			T1	17		T25	28		T26	24
values[9]	1182	1			T34	3		T234	1		T54	25
minimum	17863	1			T3	134		T6	20		T9	203

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	856	1			T9	1		T22	21		T35	10
values[1]	532	1			T11	5		T42	7		T34	4
values[2]	780	1			T3	14		T122	48		T123	15
values[3]	2714	1			T2	23		T3	28		T4	3
values[4]	587	1			T7	21		T25	1		T26	20
values[5]	589	1			T7	23		T92	3		T84	2
values[6]	696	1			T9	1		T27	1		T234	1
values[7]	803	1			T1	17		T25	28		T26	24
values[8]	865	1			T22	16		T34	3		T54	25
values[9]	135	1			T39	2		T127	1		T235	2
minimum	17863	1			T3	134		T6	20		T9	203

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22440

1

T1

9

T2

23

T3

158

auto[1]

3980

1

T1

8

T3

18

T5

4

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T9	1		T22	11		T35	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T84	11		T123	5		T236	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T11	2		T42	1		T55	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T34	3		T163	1		T40	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	1		T122	10		T123	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T122	12		T237	10		T238	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1436	1			T2	3		T3	10		T4	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T3	10		T13	2		T36	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T7	8		T26	12		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T25	1		T122	7		T128	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	14		T92	1		T143	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T84	1		T239	2		T240	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T27	1		T234	1		T216	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T9	1		T129	12		T37	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T25	11		T26	13		T234	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T1	9		T25	2		T216	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T22	9		T34	2		T54	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T54	14		T241	1		T78	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T39	2		T127	1		T235	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T192	18		T242	1		T159	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17754	1			T3	134		T6	20		T9	201
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T22	10		T35	3		T92	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T84	2		T123	5		T236	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T11	3		T42	6		T55	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T34	1		T40	1		T243	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T3	13		T122	12		T123	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T122	14		T237	9		T238	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	864	1			T2	20		T3	4		T244	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	4		T13	1		T36	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T7	13		T26	8		T133	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T154	8		T150	10		T245	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T7	9		T92	2		T157	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T84	1		T239	24		T139	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T76	2		T213	12		T246	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T129	11		T37	6		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T25	10		T26	11		T247	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T1	8		T25	5		T125	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T22	7		T34	1		T54	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T54	2		T78	16		T84	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T235	1		T136	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T192	14		T248	11		T249	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	2		T11	2		T36	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T22	9		T231	16		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T9	1		T232	1		T189	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T143	19		T250	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T22	11		T35	7		T38	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T84	11		T123	5		T236	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T11	2		T55	12		T36	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T34	3		T238	1		T40	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T42	1		T122	10		T76	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T122	12		T237	10		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T3	11		T233	1		T83	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	10		T83	11		T132	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1476	1			T2	3		T4	3		T5	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T25	1		T122	7		T13	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	22		T26	12		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T84	1		T130	1		T239	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T27	1		T234	1		T213	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T9	1		T129	12		T37	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T25	11		T26	13		T247	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T1	9		T25	2		T216	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T34	2		T234	1		T54	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	371	1			T54	14		T241	1		T78	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17754	1			T3	134		T6	20		T9	201
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T22	7		T231	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T189	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T22	10		T35	3		T38	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T84	2		T123	5		T236	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T11	3		T55	9		T36	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T34	1		T238	1		T40	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T42	6		T122	12		T76	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T122	14		T237	9		T251	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	17		T83	12		T37	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T3	4		T83	8		T132	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	849	1			T2	20		T244	10		T252	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	1		T36	1		T154	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	22		T26	8		T92	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T84	1		T239	24		T139	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T213	12		T253	16		T254	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T129	11		T37	6		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T25	10		T26	11		T247	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T1	8		T25	5		T136	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T34	1		T54	4		T55	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T54	2		T78	16		T84	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	2		T11	2		T36	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T9	1		T22	12		T35	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T84	3		T123	6		T236	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	5		T42	7		T55	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T34	3		T163	1		T40	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T3	14		T122	13		T123	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T122	15		T237	10		T238	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1189	1			T2	23		T3	5		T4	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T3	5		T13	3		T36	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	14		T26	9		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T25	1		T122	1		T128	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	10		T92	3		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T84	2		T239	26		T240	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T27	1		T234	1		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T9	1		T129	13		T37	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T25	11		T26	12		T234	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	9		T25	7		T216	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T22	8		T34	2		T54	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T54	3		T241	1		T78	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T39	2		T127	1		T235	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T192	15		T242	1		T159	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17863	1			T3	134		T6	20		T9	203
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T22	9		T35	1		T38	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T84	10		T123	4		T236	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T55	11		T45	3		T255	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T34	1		T144	8		T243	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T122	9		T123	7		T134	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T122	11		T237	9		T251	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1111	1			T3	9		T5	4		T12	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	9		T83	10		T132	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T7	7		T26	11		T133	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T122	6		T128	12		T236	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T7	13		T143	5		T210	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T142	13		T256	10		T257	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T216	10		T258	3		T246	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T129	10		T37	9		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T25	10		T26	12		T247	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	8		T216	10		T125	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T22	8		T34	1		T54	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T54	13		T259	8		T258	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T136	4		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T192	17		T159	16		T260	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T22	8		T231	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T9	1		T232	1		T189	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T143	1		T250	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T22	12		T35	9		T38	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T84	3		T123	6		T236	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	5		T55	10		T36	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T34	3		T238	2		T40	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T42	7		T122	13		T76	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T122	15		T237	10		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T3	19		T233	1		T83	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T3	5		T83	9		T132	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1167	1			T2	23		T4	3		T5	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T25	1		T122	1		T13	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T7	24		T26	9		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T84	2		T130	1		T239	26
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T27	1		T234	1		T213	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T9	1		T129	13		T37	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T25	11		T26	12		T247	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T1	9		T25	7		T216	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T34	2		T234	1		T54	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T54	3		T241	1		T78	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17863	1			T3	134		T6	20		T9	203
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T22	8		T231	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T143	18		T250	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T22	9		T35	1		T38	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T84	10		T123	4		T236	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T55	11		T143	9		T45	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T34	1		T40	1		T154	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T122	9		T123	7		T134	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T122	11		T237	9		T251	27
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T3	9		T83	8		T37	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T3	9		T83	10		T132	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1158	1			T5	4		T12	8		T124	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T122	6		T128	12		T236	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T7	20		T26	11		T133	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T142	13		T261	8		T262	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T253	15		T263	11		T161	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T129	10		T37	9		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T25	10		T26	12		T247	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T1	8		T216	10		T264	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T34	1		T54	4		T55	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T54	13		T125	11		T133	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22440

1

T1

9

T2

23

T3

158

auto[1]

auto[0]

3980

1

T1

8

T3

18

T5

4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26420

1

T1

17

T2

23

T3

176

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22950

1

T2

23

T3

162

T4

3

auto[ADC_CTRL_FILTER_COND_OUT]

3470

1

T1

17

T3

14

T11

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20961

1

T3

176

T6

20

T7

44

auto[1]

5459

1

T1

17

T2

23

T4

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22773

1

T1

9

T2

3

T3

155

auto[1]

3647

1

T1

8

T2

20

T3

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	12	1			T265	12		-	-		-	-
values[0]	25	1			T266	10		T142	14		T267	1
values[1]	573	1			T3	14		T27	1		T122	22
values[2]	586	1			T25	21		T122	1		T13	3
values[3]	682	1			T1	17		T3	14		T26	24
values[4]	527	1			T22	1		T25	7		T122	7
values[5]	820	1			T7	23		T9	1		T11	5
values[6]	670	1			T34	3		T122	26		T216	11
values[7]	606	1			T26	20		T27	1		T41	1
values[8]	704	1			T22	36		T153	1		T76	13
values[9]	3352	1			T2	23		T3	14		T4	3
minimum	17863	1			T3	134		T6	20		T9	203

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	760	1			T3	14		T25	21		T27	1
values[1]	584	1			T1	17		T233	1		T37	25
values[2]	639	1			T3	14		T25	7		T26	24
values[3]	711	1			T22	1		T122	7		T54	9
values[4]	717	1			T7	23		T11	5		T34	3
values[5]	700	1			T9	1		T26	20		T27	1
values[6]	2606	1			T2	23		T4	3		T5	5
values[7]	681	1			T9	1		T22	16		T234	1
values[8]	956	1			T3	14		T25	1		T128	13
values[9]	202	1			T7	21		T42	7		T38	18
minimum	17864	1			T3	134		T6	20		T9	203

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22440

1

T1

9

T2

23

T3

158

auto[1]

3980

1

T1

8

T3

18

T5

4

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	10		T13	2		T55	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T25	11		T27	1		T122	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T233	1		T127	1		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T1	9		T37	17		T237	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T35	7		T123	8		T39	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T3	1		T25	2		T26	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T122	7		T92	1		T129	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T22	1		T54	5		T241	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T7	14		T216	22		T84	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T11	2		T34	2		T122	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T9	1		T27	1		T84	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T26	12		T83	9		T239	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1438	1			T2	3		T4	3		T5	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T22	10		T34	3		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	1		T234	1		T84	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T22	9		T76	1		T80	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T3	10		T128	13		T55	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T25	1		T234	1		T55	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T7	8		T42	1		T133	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T38	10		T268	10		T269	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17755	1			T3	134		T6	20		T9	201
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T3	4		T13	1		T55	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T25	10		T122	12		T129	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T270	9		T14	4		T271	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T1	8		T37	8		T237	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T35	3		T123	7		T157	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T3	13		T25	5		T26	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T92	16		T129	10		T202	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T54	4		T83	8		T40	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T7	9		T84	1		T238	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T11	3		T34	1		T122	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T84	4		T259	9		T135	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T26	8		T83	12		T239	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	833	1			T2	20		T244	10		T252	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T22	10		T34	1		T272	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T84	2		T243	13		T157	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T22	7		T76	12		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T3	4		T55	9		T125	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T55	9		T78	16		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T7	13		T42	6		T133	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T38	8		T268	13		T269	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	2		T11	2		T36	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T265	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T142	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T266	1		T267	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T3	10		T55	12		T36	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T27	1		T122	10		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T13	2		T233	1		T123	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T25	11		T122	1		T37	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T35	7		T92	1		T123	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T1	9		T3	1		T26	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T122	7		T129	11		T39	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T22	1		T25	2		T54	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T7	14		T9	1		T216	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T11	2		T54	5		T36	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T216	11		T84	2		T135	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T34	2		T122	12		T92	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T27	1		T41	1		T92	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T26	12		T34	3		T273	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T84	11		T274	1		T275	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T22	19		T153	1		T76	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1656	1			T2	3		T3	10		T4	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T25	1		T234	1		T55	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17754	1			T3	134		T6	20		T9	201
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T265	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T266	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T3	4		T55	9		T36	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T122	12		T129	1		T276	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T13	1		T123	5		T134	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T25	10		T37	8		T132	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T35	3		T92	16		T123	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T1	8		T3	13		T26	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T129	10		T157	4		T192	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T25	5		T54	2		T251	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T7	9		T238	1		T202	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	3		T54	4		T36	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T84	5		T135	3		T158	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T34	1		T122	14		T92	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T92	2		T259	9		T277	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T26	8		T34	1		T235	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T84	2		T243	13		T157	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T22	17		T76	12		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1052	1			T2	20		T3	4		T7	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T55	9		T78	16		T38	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	2		T11	2		T36	1